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Author SHA1 Message Date
Imants Pulkstenis f3fcc5688d minor changes 2020-06-10 21:39:29 +03:00
Imants Pulkstenis 532a247850 minor changes 2020-06-10 21:39:10 +03:00
Imants Pulkstenis cdb68967c9 FIR and IIR filter and test benches are now working 2020-06-10 18:29:47 +03:00
Imants Pulkstenis 7b8c2a59cc matlab file updates 2020-06-10 12:03:18 +03:00
Imants Pulkstenis bcfcc84975 Still need to work on FIR, but IIR is working. 2020-06-10 01:30:00 +03:00
Imants Pulkstenis 682207dfa1 Add files for FIR and IIR filter - not tested 2020-06-09 22:28:53 +03:00
imants 01e4a4b6d3 Signal sum and signal sum test bench now working. 
Added overflow check logic
 2020-06-09 14:40:44 +03:00
Imants Pulkstenis 56e16842e4 summ not finished 2020-06-09 01:03:07 +03:00
Imants Pulkstenis 13a5336975 Added clock divider 22050Hz. Tested! 2020-06-09 00:04:30 +03:00
Imants Pulkstenis af6516eb85 Signal generators are working. Tested on TestBench 2020-06-08 20:45:20 +03:00
Imants Pulkstenis 9c73fa1193 direction and start stop now working 2020-04-13 19:23:11 +03:00
Imants Pulkstenis 45652812e3 add aditional modules for start/stop 
and for up down counter
 2020-04-13 00:25:43 +03:00
Imants Pulkstenis 9a6c90c0b2 Timming now correct and also 
7-segmet display also working now
 2020-04-12 22:44:24 +03:00
Imants Pulkstenis be0c2ab376 renaming file 2020-04-01 22:58:27 +03:00
Imants Pulkstenis 2aeeb295f7 rename files 2020-04-01 22:54:51 +03:00
Imants Pulkstenis 7b0caf4bb5 Add aditional simulations and simulation results 2020-04-01 22:28:53 +03:00
Imants Pulkstenis 1598022c70 DDS module and test bench finished 2020-04-01 21:35:27 +03:00
Imants Pulkstenis c8581dbe68 ps4 added 2020-03-29 21:08:14 +03:00
Imants Pulkstenis f19b7c8ca1 Add Lab work No2 2020-03-25 00:08:31 +02:00
Imants Pulkstenis 27e63599f4 Add Lab work No1 2020-03-24 20:23:39 +02:00
Imants Pulkstenis 8ee46486e8 add *.vcd file for GTKWave 2020-02-27 20:50:56 +02:00
Imants Pulkstenis a29e888084 FSM picture 2020-02-24 00:53:46 +02:00
Imants Pulkstenis 5d5a40afe4 minor changes 2020-02-24 00:18:10 +02:00
Imants Pulkstenis 71b037e9fe file raname 2020-02-24 00:14:20 +02:00
Imants Pulkstenis 22851efc71 VHDL Problem set 3 2020-02-23 23:58:12 +02:00
Imants Pulkstenis fcc5a0b050 Compleated Verilog file and started working un VHDL 2020-02-23 22:40:30 +02:00
Imants Pulkstenis 470628a6ac readme.md 2020-02-23 19:28:46 +02:00
Imants Pulkstenis d766660062 changes in readme.md 2020-02-23 19:22:15 +02:00
Imants Pulkstenis c42e0654da add aditional else if for MR_GREEN_1 state 2020-02-23 19:18:36 +02:00
Imants Pulkstenis e6cbc865aa Add Problem set 3 2020-02-23 19:12:32 +02:00
Imants Pulkstenis 40fa3d7bda ALU NAND and NOR rework 2020-02-16 18:40:37 +02:00
Imants Pulkstenis 6d158867bb remove overflow flag 2020-02-16 18:36:07 +02:00
Imants Pulkstenis 818b11e338 add ps02_siggen. file 2020-02-16 16:11:37 +02:00
Imants Pulkstenis 23c36a292b code debug 2020-02-16 15:28:19 +02:00
Imants Pulkstenis 4b4e427c4a ALU flag operation added 2020-02-16 15:26:56 +02:00
Imants Pulkstenis c715347ee5 Merge branch 'master' of https://github.com/Clockfix/RTR532 2020-02-16 13:26:05 +02:00
Imants Pulkstenis 3c38cb75a8 Task 2 - done 2020-02-16 13:22:57 +02:00
Imants Pulkstenis db3eac9c03 add decription 2020-02-16 13:13:02 +02:00
Imants Pulkstenis e2311d5b73 add alu.v file 2020-02-16 13:11:07 +02:00
Imants Pulkstenis 609a9292b3 Task1 done. Code debuging 2020-02-16 12:20:58 +02:00
Imants Pulkstenis 4eb5c37b4f add ps02.v top module in Verilog 2020-02-16 12:09:38 +02:00
Imants Pulkstenis 804dc0eca7 Merge branch 'master' of https://github.com/Clockfix/RTR532 2020-02-16 11:35:51 +02:00
Imants Pulkstenis 9d51d87b7f Problem set 2 added 2020-02-16 11:34:03 +02:00
Imants PulkstenisandGitHub cb0b531452 Update README.md 2020-02-10 23:13:24 +02:00
Imants PulkstenisandGitHub d73a12f3ab Update ps01q.vhd 2020-02-10 23:07:59 +02:00
Imants Pulkstenis 8def5cd7c0 changes in vhdl file and add LUT.jpg file 2020-02-10 22:58:48 +02:00
Imants Pulkstenis 1f0ce57d47 initial commit 2020-02-10 22:03:20 +02:00
Imants Pulkstenis b6f75f6297 Initial commit 2020-02-10 21:40:50 +02:00
Imants PulkstenisandGitHub 16d8573236 Update README.md 2020-02-10 21:33:12 +02:00
Imants PulkstenisandGitHub 6a702cbbb7 Update README.md 2020-02-10 21:31:58 +02:00