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Imants Pulkstenis 56e16842e4 summ not finished
2020-06-09 01:03:07 +03:00
ld1
Add Lab work No1
2020-03-24 20:23:39 +02:00
ld2
Signal generators are working. Tested on TestBench
2020-06-08 20:45:20 +03:00
ld3
summ not finished
2020-06-09 01:03:07 +03:00
ps1
Update ps01q.vhd
2020-02-10 23:07:59 +02:00
ps2/ps02q
DDS module and test bench finished
2020-04-01 21:35:27 +03:00
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ps4 added
2020-03-29 21:08:14 +03:00
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renaming file
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README.md
VHDL Problem set 3
2020-02-23 23:58:12 +02:00

README.md

RTR532

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Rīgas Tehniskā Universitāte kurss RTR532 19/20 pavasaris

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Description
RTU kurss RTR532 19/20
Readme MIT
3.4 MiB
Languages
VHDL 66.4%
Verilog 16.1%
Tcl 8.9%
Shell 4.3%
MATLAB 3.2%
Other 1%