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Imants Pulkstenis fcc5a0b050 Compleated Verilog file and started working un VHDL
2020-02-23 22:40:30 +02:00
ld1
Initial commit
2020-02-10 21:40:50 +02:00
ps1
Update ps01q.vhd
2020-02-10 23:07:59 +02:00
ps2/ps02q
ALU NAND and NOR rework
2020-02-16 18:40:37 +02:00
ps3
Compleated Verilog file and started working un VHDL
2020-02-23 22:40:30 +02:00
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README.md
readme.md
2020-02-23 19:28:46 +02:00

README.md

RTR532

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Rīgas Tehniskā Universitāte kurss RTR532 19/20 pavasaris

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Description
RTU kurss RTR532 19/20
Readme MIT
3.4 MiB
Languages
VHDL 66.4%
Verilog 16.1%
Tcl 8.9%
Shell 4.3%
MATLAB 3.2%
Other 1%