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VHDL Problem set 3

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Imants Pulkstenis
2020-02-23 23:58:12 +02:00
parent fcc5a0b050
commit 22851efc71
5 changed files with 70 additions and 40 deletions
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README.md
+1 -1
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@@ -2,7 +2,7 @@
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Rīgas Tehniskā Universitāte kurss RTR532 19/20 pavasaris
ps3/ps02q/fsm_training_traffic.vhd → ps3/ps03q/fsm_training_traffic.vhd
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ps3/ps02q/tlc_tb.v → ps3/ps03q/tlc_tb.v
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ps3/ps02q/traffic_light_controler.v → ps3/ps03q/traffic_light_controler.v
+11 -14
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@@ -60,15 +60,14 @@ module smart_tl_ctl #( parameter
//-------------Internal Constants---------------------------
localparam [2:0] IDLE = 'h0,
MR_GREEN_A = 'h1,
MR_GREEN_B = 'h2,
MR_GREEN_1 = 'h1,
MR_GREEN_2 = 'h2,
MR_YELLOW = 'h3,
SR_GREEN = 'h4,
SR_YELLOW = 'h5;
//-------------Internal signals and components--------------
reg [2:0] r_state = IDLE,
r_next = MR_GREEN_A;
reg [2:0] r_state = IDLE;
reg [4:0] r_cnt = 'b0;
reg [1:0] r_MR_ctl = 'b0,
r_SR_ctl = 'b0;
@@ -85,20 +84,20 @@ always@(posedge clk) begin
IDLE: begin
r_MR_ctl <= 'b00;
r_SR_ctl <= 'b00;
r_state <= MR_GREEN_A;
r_state <= MR_GREEN_1;
r_cnt <= 'd0;
end
MR_GREEN_A: begin
MR_GREEN_1: begin
r_MR_ctl <= 'b11;
r_SR_ctl <= 'b01;
if (r_cnt >= MR_GREEN_TIME) begin
if (MR_cars == 0) begin
r_cnt <= 0;
r_state <= MR_GREEN_A;
r_state <= MR_GREEN_1;
end
else if (MR_cars < PARAMETER) begin
r_cnt <= 0;
r_state <= MR_GREEN_B;
r_state <= MR_GREEN_2;
end
else if (MR_cars >= PARAMETER) begin
r_cnt <= 0;
@@ -106,11 +105,11 @@ always@(posedge clk) begin
end
end
else begin
r_state <= MR_GREEN_A;
r_state <= MR_GREEN_1;
r_cnt <= r_cnt + 1;
end
end
MR_GREEN_B: begin
MR_GREEN_2: begin
r_MR_ctl <= 'b11;
r_SR_ctl <= 'b01;
if (r_cnt >= MR_GREEN_TIME) begin
@@ -119,7 +118,7 @@ always@(posedge clk) begin
end
else begin
r_cnt <= r_cnt + 1;
r_state <= MR_GREEN_B;
r_state <= MR_GREEN_2;
end
end
MR_YELLOW: begin
@@ -132,7 +131,6 @@ always@(posedge clk) begin
else begin
r_cnt <= r_cnt + 1;
r_state <= MR_YELLOW;
end
end
SR_GREEN: begin
@@ -152,7 +150,7 @@ always@(posedge clk) begin
r_SR_ctl <= 'b10;
if (r_cnt >= YELLOW_TIME) begin
r_cnt = 0;
r_state <= MR_GREEN_A;
r_state <= MR_GREEN_1;
end
else begin
r_cnt <= r_cnt + 1;
@@ -164,7 +162,6 @@ always@(posedge clk) begin
end
else begin
r_state <= IDLE;
r_MR_ctl <= 'b00;
r_SR_ctl <= 'b00;
r_cnt <= 0;
ps3/ps02q/traffic_light_controler.vhdl → ps3/ps03q/traffic_light_controler.vhdl
+58 -25
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@@ -80,45 +80,78 @@ begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
if rst = '0' then
state <= "000";
cnt <= x"00";
else
case state is
when "000" => -- lights off secs
state <= "001";
cnt <= 0;
state <= "001";
when "001" => -- MR green light 30 secs
if cnt < 5 then
cnt <= cnt + 1;
state <= "001";
else
cnt <= 0;
state <= "010";
MR_ctl <= "00";
SR_ctl <= "00";
when "001" => -- MR green light 30 ns
MR_ctl <= "11";
SR_ctl <= "01";
if cnt >= 30 then
if MR_cars == 0 then
cnt <= 0;
state <= "001";
else if MR_cars < PARAMETER then
cnt <= 0;
state <= "010";
else
cnt <= 0;
state <= "011";
end if;
end if;
else
cnt <= cnt + 1;
state <= "001";
end if;
when "010" => -- MR green light 30 secs
when "010" => -- MR green light 30 ns
MR_ctl <= "11";
SR_ctl <= "01";
if cnt < 30 then
cnt <= cnt + 1;
state <= "10";
cnt <= cnt + 1;
state <= "010";
else
cnt <= 0;
state <= "011";
end if;
when "011" => -- MR yellow light 3 ns
MR_ctl <= "10";
SR_ctl <= "10";
if cnt < 3 then
cnt <= cnt + 1;
state <= "011";
else
cnt <= 0;
state <= "11";
cnt <= 0;
state <= "100";
end if;
when "11" => --yellow light 5 secs
if cnt < 5 then
cnt <= cnt + 1;
state <= "11";
when "100" => -- SR green light 10 ns
MR_ctl <= "01";
SR_ctl <= "11";
if cnt < 10 then
cnt <= cnt + 1;
state <= "100";
else
cnt <= 0;
state <= "00";
end if;
cnt <= 0;
state <= "101";
end if;
when "101" => -- SR yellow light 3 ns
MR_ctl <= "10";
SR_ctl <= "10";
if cnt < 3 then
cnt <= cnt + 1;
state <= "101";
else
cnt <= 0;
state <= "001";
end if;
when others =>
cnt <= 0;
state <= "00";
state <= "000";
end case;
end if;