DDS module and test bench finished
This commit is contained in:
Imants Pulkstenis
+1
-1
@@ -7,7 +7,7 @@
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// Detailed module description:
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//
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// This module generete clk signal for
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// for tom podule of ps02 project
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// top module of ps02 project
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// The test is executed using Icarus Verilog!
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//
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// The result can be evaluated in GTKwave application.
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+33
-5
@@ -26,12 +26,40 @@ module dds_vhdl#( parameter
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output [phase_width - 1:0] phase_out,
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output [data_width - 1:0] signal_out);
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// define inside of the module
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reg [phase_width - 1:0] r_phase_incr = 'd0;
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reg [phase_width - 1:0] r_phase_out = 'd0;
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// Phase increment – determines output frequency
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always@(posedge clk)begin
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if (rst) begin
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r_phase_incr <= 0; end
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else begin
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r_phase_incr <= phase_incr; end
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end
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// Phase accumulator – the «counter»
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always@(posedge clk)begin
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if (rst) begin
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r_phase_out <= 0; end
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else begin
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r_phase_out <= phase_out + phase_incr; end
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end
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// Look-up table – memory where waveform is stored
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lookuptable lookuptable (
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.in(),
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.out());
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.phase( // mux
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(control== 0) ? 4'b0 :
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(control== 1) ? {2'b0, phase_out[phase_width - 3:0] } :
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(control== 2) ? {1'b0, phase_out[phase_width - 2:0] } :
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phase_out
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// end of MUX
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),
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.sin(signal_out),
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.cos());
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assign phase_out = r_phase_out;
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endmodule
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@@ -0,0 +1,87 @@
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/////////////////////////////////////////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 01.04.2020
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// Project name - PS04
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// Module name - test bench of DDS (direct digital synthesis)
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//
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// Detailed module description:
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// This module generete clk signal for
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// top module of dds_vhdl project
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// The test is executed using Icarus Verilog!
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//
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// The result can be evaluated in GTKwave application.
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// Code:
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// iverilog -o output.vvp dds_vhdl_tb.v && vvp output.vvp
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// gtkwave -f wave.vcd
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//
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// Revision:
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// A - initial design
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// B -
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// C -
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//
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///////////////////////////////////////////////////////////////////
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//sub modules
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`include "lookuptable.v"
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//top module
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`include "dds_vhdl.v"
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//define module and connections to outside
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module dds_vhdl_tb #( parameter
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phase_width = 4,
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data_width = 8
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)();
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//define inside use signals
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reg clk = 1'b0;
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reg rst = 1'b0;
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reg [1:0] r_control = 'd3;
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reg [phase_width - 1:0] r_phase_incr = 'd1;
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//---------Test script----------------
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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//-----Unit Under test---------------
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dds_vhdl #(
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.data_width(8)
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) unit_under_test (
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.clk(clk),
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.rst(rst),
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.control(r_control),
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.phase_incr(r_phase_incr),
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.phase_out(),
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.signal_out()
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);
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//---------Test--------------------
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initial begin
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rst = 1;
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#10;
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rst = 0;
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#100
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r_control = 2;
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#100
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r_control = 1;
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#100
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r_control = 0;
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#100
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$finish();
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end
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initial begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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$display("----------------------------------------------");
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$display(" ");
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end
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endmodule
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+44
-22
@@ -1,26 +1,48 @@
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module lookuptable(
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input [7 :0] in,
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output reg [7 :0] out);
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reg [7 :0] out = 8'h0;
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module lookuptable #( parameter phase_width = 4, data_width = 8)(
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input [phase_width - 1 :0] phase,
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output reg [data_width - 1 :0] sin,
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output reg [data_width - 1 :0] cos);
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always@* begin
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case (in)
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8'd0 : out <= 8'b00000000;
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8'd1 : out <= 8'b00011001;
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8'd2 : out <= 8'b00101101;
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8'd3 : out <= 8'b00111011;
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8'd4 : out <= 8'b01000000;
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8'd5 : out <= 8'b00111011;
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8'd6 : out <= 8'b00101101;
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8'd7 : out <= 8'b00011001;
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8'd8 : out <= 8'b00000000;
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8'd9 : out <= 8'b11101000;
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8'd10 : out <= 8'b11010011;
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8'd11 : out <= 8'b11000101;
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8'd12 : out <= 8'b11000000;
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8'd13 : out <= 8'b11000101;
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8'd14 : out <= 8'b11010011;
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8'd15 : out <= 8'b11101000;
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default : out <= 8'b00000000;
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case (phase[phase_width - 1 : 0])
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4'd0 : sin[data_width - 1 : 0] <= 8'b00000000;
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4'd1 : sin[data_width - 1 : 0] <= 8'b00011001;
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4'd2 : sin[data_width - 1 : 0] <= 8'b00101101;
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4'd3 : sin[data_width - 1 : 0] <= 8'b00111011;
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4'd4 : sin[data_width - 1 : 0] <= 8'b01000000;
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4'd5 : sin[data_width - 1 : 0] <= 8'b00111011;
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4'd6 : sin[data_width - 1 : 0] <= 8'b00101101;
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4'd7 : sin[data_width - 1 : 0] <= 8'b00011001;
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4'd8 : sin[data_width - 1 : 0] <= 8'b00000000;
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4'd9 : sin[data_width - 1 : 0] <= 8'b11101000;
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4'd10 : sin[data_width - 1 : 0] <= 8'b11010011;
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4'd11 : sin[data_width - 1 : 0] <= 8'b11000101;
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4'd12 : sin[data_width - 1 : 0] <= 8'b11000000;
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4'd13 : sin[data_width - 1 : 0] <= 8'b11000101;
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4'd14 : sin[data_width - 1 : 0] <= 8'b11010011;
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4'd15 : sin[data_width - 1 : 0] <= 8'b11101000;
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default : sin[data_width - 1 : 0] <= 8'b00000000;
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endcase
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end
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always@* begin
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case (phase[phase_width - 1 : 0])
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4'd0 : cos[data_width - 1 : 0] <= 8'b01000000;
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4'd1 : cos[data_width - 1 : 0] <= 8'b00111011;
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4'd2 : cos[data_width - 1 : 0] <= 8'b00101101;
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4'd3 : cos[data_width - 1 : 0] <= 8'b00011001;
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4'd4 : cos[data_width - 1 : 0] <= 8'b00000000;
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4'd5 : cos[data_width - 1 : 0] <= 8'b11101000;
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4'd6 : cos[data_width - 1 : 0] <= 8'b11010011;
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4'd7 : cos[data_width - 1 : 0] <= 8'b11000101;
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4'd8 : cos[data_width - 1 : 0] <= 8'b11000000;
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4'd9 : cos[data_width - 1 : 0] <= 8'b11000101;
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4'd10 : cos[data_width - 1 : 0] <= 8'b11010011;
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4'd11 : cos[data_width - 1 : 0] <= 8'b11101000;
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4'd12 : cos[data_width - 1 : 0] <= 8'b00000000;
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4'd13 : cos[data_width - 1 : 0] <= 8'b00011001;
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4'd14 : cos[data_width - 1 : 0] <= 8'b00101101;
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4'd15 : cos[data_width - 1 : 0] <= 8'b00111011;
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default : cos[data_width - 1 : 0] <= 8'b01000000;
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endcase
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end
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endmodule
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+44
-22
@@ -1,26 +1,48 @@
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module lookuptable(
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input [7 :0] in,
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output reg [7 :0] out);
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reg [7 :0] out = 8'h0;
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module lookuptable #( parameter phase_width = 4, data_width = 8)(
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input [phase_width - 1 :0] phase,
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output reg [data_width - 1 :0] sin,
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output reg [data_width - 1 :0] cos);
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always@* begin
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case (in)
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8'd0 : out <= 8'b00000000;
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8'd1 : out <= 8'b00011001;
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8'd2 : out <= 8'b00101101;
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8'd3 : out <= 8'b00111011;
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8'd4 : out <= 8'b01000000;
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8'd5 : out <= 8'b00111011;
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8'd6 : out <= 8'b00101101;
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8'd7 : out <= 8'b00011001;
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8'd8 : out <= 8'b00000000;
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8'd9 : out <= 8'b11101000;
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8'd10 : out <= 8'b11010011;
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8'd11 : out <= 8'b11000101;
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8'd12 : out <= 8'b11000000;
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8'd13 : out <= 8'b11000101;
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8'd14 : out <= 8'b11010011;
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8'd15 : out <= 8'b11101000;
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default : out <= 8'b00000000;
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case (phase[phase_width - 1 : 0])
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4'd0 : sin[data_width - 1 : 0] <= 8'b00000000;
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4'd1 : sin[data_width - 1 : 0] <= 8'b00011001;
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4'd2 : sin[data_width - 1 : 0] <= 8'b00101101;
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4'd3 : sin[data_width - 1 : 0] <= 8'b00111011;
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4'd4 : sin[data_width - 1 : 0] <= 8'b01000000;
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4'd5 : sin[data_width - 1 : 0] <= 8'b00111011;
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4'd6 : sin[data_width - 1 : 0] <= 8'b00101101;
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4'd7 : sin[data_width - 1 : 0] <= 8'b00011001;
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4'd8 : sin[data_width - 1 : 0] <= 8'b00000000;
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4'd9 : sin[data_width - 1 : 0] <= 8'b11101000;
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4'd10 : sin[data_width - 1 : 0] <= 8'b11010011;
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4'd11 : sin[data_width - 1 : 0] <= 8'b11000101;
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4'd12 : sin[data_width - 1 : 0] <= 8'b11000000;
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4'd13 : sin[data_width - 1 : 0] <= 8'b11000101;
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4'd14 : sin[data_width - 1 : 0] <= 8'b11010011;
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4'd15 : sin[data_width - 1 : 0] <= 8'b11101000;
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default : sin[data_width - 1 : 0] <= 8'b00000000;
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endcase
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end
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always@* begin
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case (phase[phase_width - 1 : 0])
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4'd0 : cos[data_width - 1 : 0] <= 8'b01000000;
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4'd1 : cos[data_width - 1 : 0] <= 8'b00111011;
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4'd2 : cos[data_width - 1 : 0] <= 8'b00101101;
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4'd3 : cos[data_width - 1 : 0] <= 8'b00011001;
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4'd4 : cos[data_width - 1 : 0] <= 8'b00000000;
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4'd5 : cos[data_width - 1 : 0] <= 8'b11101000;
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4'd6 : cos[data_width - 1 : 0] <= 8'b11010011;
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4'd7 : cos[data_width - 1 : 0] <= 8'b11000101;
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4'd8 : cos[data_width - 1 : 0] <= 8'b11000000;
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4'd9 : cos[data_width - 1 : 0] <= 8'b11000101;
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4'd10 : cos[data_width - 1 : 0] <= 8'b11010011;
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4'd11 : cos[data_width - 1 : 0] <= 8'b11101000;
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4'd12 : cos[data_width - 1 : 0] <= 8'b00000000;
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4'd13 : cos[data_width - 1 : 0] <= 8'b00011001;
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4'd14 : cos[data_width - 1 : 0] <= 8'b00101101;
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4'd15 : cos[data_width - 1 : 0] <= 8'b00111011;
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default : cos[data_width - 1 : 0] <= 8'b01000000;
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endcase
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end
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endmodule
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+37
-17
@@ -5,11 +5,11 @@
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% Module name - DDS (direct digital synthesis)
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%
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% Detailed module description:
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% This file generates lock up table with SIN values
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% This file generates lock up table with SIN and COS values
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%
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% Revision:
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% A - initial design
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% B -
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% B - add COS output
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% C -
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%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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@@ -18,30 +18,50 @@ word_lenght = 8;
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table_size = 4; % 2^n
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x = linspace(0, (2*pi - 2*pi/2^table_size) , 2^table_size);
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sin_x = sin(x);
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sin_x = round(sin_x * 2^word_lenght) / 2^word_lenght;
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sin_x = round(sin_x * 2^word_lenght) / 2^word_lenght; % round values
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%% Print values in hex
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hex = [];
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cos_x = cos(x);
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cos_x = round(cos_x * 2^word_lenght) / 2^word_lenght; % round values
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%% Print values in HEX
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hex_sin = [];
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hex_cos = [];
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for i=1:2^table_size
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a = sfi(sin_x(i),word_lenght,word_lenght-2);
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hex = [hex; a.bin];
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a = sfi(sin_x(i),word_lenght,word_lenght-2);
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b = sfi(cos_x(i),word_lenght,word_lenght-2);
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hex_sin = [hex_sin; a.bin];
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hex_cos = [hex_cos; b.bin];
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end
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hex,
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%hex_sin,
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%hex_cos,
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fid = fopen('lookuptable.v', 'wt');
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fprintf(fid, 'module lookuptable(\n');
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fprintf(fid, '\tinput [%d :0] in,\n',word_lenght-1);
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fprintf(fid, '\toutput reg [%d :0] out);\n',word_lenght-1);
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fprintf(fid, 'module lookuptable #( parameter phase_width = %d, data_width = %d)(\n', table_size, word_lenght);
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fprintf(fid, '\tinput [phase_width - 1 :0] phase,\n');
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fprintf(fid, '\toutput reg [data_width - 1 :0] sin,\n');
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fprintf(fid, '\toutput reg [data_width - 1 :0] cos);\n');
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fprintf(fid, 'reg [%d :0] out = %d''h0; \n', word_lenght-1,word_lenght);
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% fprintf(fid, 'reg [%d :0] sin = %d''h0; \n', word_lenght-1,word_lenght);
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fprintf(fid, 'always@* begin\n');
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fprintf(fid, 'case (in)\n');
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fprintf(fid, 'case (phase[phase_width - 1 : 0])\n');
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for i=1:length(hex)
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temp = hex(i,1:word_lenght);
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fprintf(fid, '\t%d''d%d : out <= %d''b%s;\n',word_lenght, i-1 ,word_lenght, hex(i,1:word_lenght) );
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for i=1:length(hex_sin)
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temp = hex_sin(i,1:word_lenght);
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fprintf(fid, '\t%d''d%d : sin[data_width - 1 : 0] <= %d''b%s;\n',table_size, i-1 ,word_lenght, hex_sin(i,1:word_lenght) );
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end
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fprintf(fid, '\tdefault : out <= %d''b%s;\n ',word_lenght, hex(1,1:word_lenght) );
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fprintf(fid, '\tdefault : sin[data_width - 1 : 0] <= %d''b%s;\n ',word_lenght, hex_sin(1,1:word_lenght) );
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fprintf(fid, 'endcase\n');
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fprintf(fid, 'end\n');
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fprintf(fid, ' \n');
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fprintf(fid, 'always@* begin\n');
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fprintf(fid, 'case (phase[phase_width - 1 : 0])\n');
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for i=1:length(hex_cos)
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temp = hex_cos(i,1:word_lenght);
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fprintf(fid, '\t%d''d%d : cos[data_width - 1 : 0] <= %d''b%s;\n',table_size, i-1 , word_lenght, hex_cos(i,1:word_lenght) );
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end
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fprintf(fid, '\tdefault : cos[data_width - 1 : 0] <= %d''b%s;\n ',word_lenght, hex_cos(1,1:word_lenght) );
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fprintf(fid, 'endcase\n');
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fprintf(fid, 'end\n');
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fprintf(fid, 'endmodule');
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