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Imants Pulkstenis
2020-03-29 21:08:14 +03:00
parent f19b7c8ca1
commit c8581dbe68
9 changed files with 436 additions and 19747 deletions
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ps3/ps03q/wave.vcd
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ps4/dds_vhdl/dds_vhdl.qpf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
# Date created = 22:16:23 March 21, 2018
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "15.0"
DATE = "22:16:23 March 21, 2018"
# Revisions
PROJECT_REVISION = "dds_vhdl"
ps4/dds_vhdl/dds_vhdl.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
# Date created = 22:16:23 March 21, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# dds_vhdl_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
set_global_assignment -name TOP_LEVEL_ENTITY dds_vhdl
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:16:23 MARCH 21, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name VHDL_FILE dds_vhdl_tb.vhd
set_global_assignment -name VHDL_FILE dds_vhdl.vhd
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
ps4/dds_vhdl/dds_vhdl.v
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/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 29.03.2020
// Project name - PS04
// Module name - DDS (direct digital synthesis)
//
// Detailed module description:
// Aim of this problem set – to practice Direct Digital Synthesis in FPGA
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
// define connections to outside
module dds_vhdl#( parameter
phase_width = 4,
data_width = 8
)(
input clk, //100mhz clock
input rst, //rst
input [1:0] control,
input [phase_width - 1:0] phase_incr, //"frequency"
output [phase_width - 1:0] phase_out,
output [data_width - 1:0] signal_out);
// define inside of the module
lookuptable lookuptable (
.in(),
.out());
endmodule
ps4/dds_vhdl/dds_vhdl.vhd
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-----------------------------
-- Author -
-- Date -
-- Project name -
-- Module name -
--
-- Detailed module description
--
-- Revision:
-- A - initial design
-- B -
--
-----------------------------
library ieee; --always use this library
use ieee.std_logic_1164.all; --always use this library
use ieee.numeric_std.all; --use this library if arithmetic required
--define connections to outside
entity dds_vhdl is
generic
(
phase_width : integer := 4;
data_width : integer := 8
);
port
(
clk : in std_logic; --100mhz clock
rst : in std_logic; --rst
phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
phase_out : out std_Logic_vector(phase_width - 1 downto 0);
signal_out : out std_Logic_vector(data_width - 1 downto 0)
);
end dds_vhdl;
--define inside of the module
architecture behavioral of dds_vhdl is
--define inside use signals
type rom_table is array ( 0 to 2**phase_width - 1) of std_logic_vector(data_width - 1 downto 0);
constant signal_rom_table : rom_table :=
(
0 => x"FF",
1 => x"FF",
2 => x"FF",
3 => x"FF",
4 => x"FF",
5 => x"FF",
6 => x"FF",
7 => x"FF",
8 => x"00",
9 => x"00",
10 => x"00",
11 => x"00",
12 => x"00",
13 => x"00",
14 => x"00",
15 => x"00"
);
-- phase counter
signal phase_cnt : unsigned(phase_width - 1 downto 0) := (others => '0');
begin --define the operation of the module!
--phase output for debugging
phase_out <= std_logic_Vector(phase_cnt);
--phase counter
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
phase_cnt <=
else
phase_cnt <=
end if;
end if;
end process;
--data output
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
signal_out <=
else
--assign value from table
signal_out <=
end if;
end if;
end process;
end behavioral;
ps4/dds_vhdl/dds_vhdl_tb.vhd
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-----------------------------
-- Author
-- Date
-- Project name
-- Module name
--
-- Detailed module description
--
--
--
--
--
--
--
-- Revision:
-- A - initial design
-- B -
--
-----------------------------
library ieee; --always use this library
use ieee.std_logic_1164.all; --always use this library
use ieee.numeric_std.all; --use this library if arithmetic required
--define connections to outside
entity dds_vhdl_tb is
generic
(
phase_width : integer := 4;
data_width : integer := 8
);
end dds_vhdl_tb;
--define inside of the module
architecture behavioral of dds_vhdl_tb is
--signals
signal clk : std_logic := '0'; --100mhz clock
signal rst : std_logic := '0'; --rst
signal phase_incr : std_Logic_vector(phase_width - 1 downto 0) := (others => '0'); --"frequency"
signal phase_out : std_Logic_vector(phase_width - 1 downto 0) := (others => '0');
signal signal_out : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
--define components to use
component dds_vhdl is
generic
(
phase_width : integer := 4;
data_width : integer := 8
);
port
(
clk : in std_logic; --100mhz clock
rst : in std_logic; --rst
phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
phase_out : out std_Logic_vector(phase_width - 1 downto 0);
signal_out : out std_Logic_vector(data_width - 1 downto 0)
);
end component;
constant clk_period : time := 10 ns;
begin
clk <= not clk after clk_period/2;
uut : dds_vhdl
generic map
(
phase_width => phase_width,
data_width => data_width
)
port map
(
clk => clk,
rst => rst,
phase_incr => phase_incr,
phase_out => phase_out,
signal_out => signal_out
);
--tb process
process
begin
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period/2;
--phase_incr <= (0 => '1', others => '0'); --1
phase_incr <= (1 => '1', others => '0'); --2
wait;
end process;
end behavioral;
ps4/dds_vhdl/lookuptable.v
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module lookuptable(
input [7 :0] in,
output reg [7 :0] out);
reg [7 :0] out = 8'h0;
always@* begin
case (in)
8'd0 : out <= 8'b00000000;
8'd1 : out <= 8'b00011001;
8'd2 : out <= 8'b00101101;
8'd3 : out <= 8'b00111011;
8'd4 : out <= 8'b01000000;
8'd5 : out <= 8'b00111011;
8'd6 : out <= 8'b00101101;
8'd7 : out <= 8'b00011001;
8'd8 : out <= 8'b00000000;
8'd9 : out <= 8'b11101000;
8'd10 : out <= 8'b11010011;
8'd11 : out <= 8'b11000101;
8'd12 : out <= 8'b11000000;
8'd13 : out <= 8'b11000101;
8'd14 : out <= 8'b11010011;
8'd15 : out <= 8'b11101000;
default : out <= 8'b00000000;
endcase
end
endmodule
ps4/lookuptable.v
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module lookuptable(
input [7 :0] in,
output reg [7 :0] out);
reg [7 :0] out = 8'h0;
always@* begin
case (in)
8'd0 : out <= 8'b00000000;
8'd1 : out <= 8'b00011001;
8'd2 : out <= 8'b00101101;
8'd3 : out <= 8'b00111011;
8'd4 : out <= 8'b01000000;
8'd5 : out <= 8'b00111011;
8'd6 : out <= 8'b00101101;
8'd7 : out <= 8'b00011001;
8'd8 : out <= 8'b00000000;
8'd9 : out <= 8'b11101000;
8'd10 : out <= 8'b11010011;
8'd11 : out <= 8'b11000101;
8'd12 : out <= 8'b11000000;
8'd13 : out <= 8'b11000101;
8'd14 : out <= 8'b11010011;
8'd15 : out <= 8'b11101000;
default : out <= 8'b00000000;
endcase
end
endmodule
ps4/table_gen.m
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Author - Imants Pulkstenis
% Date - 29.03.2020
% Project name - PS04
% Module name - DDS (direct digital synthesis)
%
% Detailed module description:
% This file generates lock up table with SIN values
%
% Revision:
% A - initial design
% B -
% C -
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
word_lenght = 8;
table_size = 4; % 2^n
x = linspace(0, (2*pi - 2*pi/2^table_size) , 2^table_size);
sin_x = sin(x);
sin_x = round(sin_x * 2^word_lenght) / 2^word_lenght;
%% Print values in hex
hex = [];
for i=1:2^table_size
a = sfi(sin_x(i),word_lenght,word_lenght-2);
hex = [hex; a.bin];
end
hex,
fid = fopen('lookuptable.v', 'wt');
fprintf(fid, 'module lookuptable(\n');
fprintf(fid, '\tinput [%d :0] in,\n',word_lenght-1);
fprintf(fid, '\toutput reg [%d :0] out);\n',word_lenght-1);
fprintf(fid, 'reg [%d :0] out = %d''h0; \n', word_lenght-1,word_lenght);
fprintf(fid, 'always@* begin\n');
fprintf(fid, 'case (in)\n');
for i=1:length(hex)
temp = hex(i,1:word_lenght);
fprintf(fid, '\t%d''d%d : out <= %d''b%s;\n',word_lenght, i-1 ,word_lenght, hex(i,1:word_lenght) );
end
fprintf(fid, '\tdefault : out <= %d''b%s;\n ',word_lenght, hex(1,1:word_lenght) );
fprintf(fid, 'endcase\n');
fprintf(fid, 'end\n');
fprintf(fid, 'endmodule');
disp('Text files write done');disp(' ');
fclose(fid);