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Problem set 2 added

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Imants Pulkstenis
2020-02-16 11:34:03 +02:00
parent d73a12f3ab
commit 9d51d87b7f
5 changed files with 359 additions and 0 deletions
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ps2/ps02q/alu.vhd
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----------------------------- info header [part 1 of the VHDL file]
-- Author
-- Date
-- Project name
-- Module name
--
-- Detailed module description
--
--
--
--
--
--
--
-- Revision:
-- A - initial design
-- B -
--
-----------------------------
-- define libraries to be used [part 2 of the VHDL file]
library ieee; --always use this library
use ieee.std_logic_1164.all; --always use this library
use ieee.numeric_std.all; --use this library if arithmetic required
--Entity declaration [part 3 of the VHDL file].
entity alu is
generic
(
data_width : integer := 32
);
port
(
clk : in std_logic;
A : in std_Logic_vector(data_width - 1 downto 0);
B : in std_logic_vector(data_width - 1 downto 0);
op : in std_logic_vector(3 downto 0);
R : out std_logic_vector(data_width - 1 downto 0);
flag : out std_logic
);
end alu;
--define inside of the module
architecture behavioral of alu is
--define inside use signals and components [part 4 of the VHDL file]
begin
--define the operation of the module! [part 5 of the VHDL file]
flag <= '0'; --optional
end behavioral;
ps2/ps02q/ps02.qpf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
# Date created = 11:44:45 February 25, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "15.0"
DATE = "11:44:45 February 25, 2017"
# Revisions
PROJECT_REVISION = "ps02"
ps2/ps02q/ps02.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
# Date created = 11:44:46 February 25, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ps02_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY ps02
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:44:46 FEBRUARY 25, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_FILE alu.vhd
set_global_assignment -name VHDL_FILE ps02.vhd
set_global_assignment -name VHDL_FILE ps02_siggen.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
ps2/ps02q/ps02.vhd
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-----------------------------
-- Author
-- Date
-- Project name
-- Module name
--
-- Detailed module description
--
--
--
--
--
--
--
-- Revision:
-- A - initial design
-- B -
--
-----------------------------
library ieee; --always use this library
use ieee.std_logic_1164.all; --always use this library
use ieee.numeric_std.all; --use this library if arithmetic required
--define connections to outside
entity ps02 is
generic
(
data_width : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
R : out std_logic_vector(data_width - 1 downto 0);
flag : out std_logic
);
end ps02;
--define inside of the module
architecture behavioral of ps02 is
--define inside use signals
signal A : std_Logic_vector(data_width - 1 downto 0);
signal B : std_Logic_vector(data_width - 1 downto 0);
signal op : std_logic_vector(3 downto 0);
--component declaration for A, B, op signal generator
component ps02_siggen is
generic
(
data_width : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
A : out std_Logic_vector(data_width - 1 downto 0);
B : out std_logic_vector(data_width - 1 downto 0);
op : out std_logic_vector(3 downto 0)
);
end component;
--component declaration for alu (TASK 1)
begin
--port map for A, B, op signal generator
name_of_unit : ps02_siggen
generic map
(
data_width => data_width
)
port map
(
clk => clk,
rst => rst,
A => A,
B => B,
op => op
);
--port map for ALU (TASK 1)
end behavioral;
ps2/ps02q/ps02_siggen.vhd
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-----------------------------
-- Author - Kriss Osmanis
-- Date - 2017-02-25; 2019-02-20
-- Project name - PS02
-- Module name - PS02 signal generator
--
-- Detailed module description
-- generates values for A, B, op
--
--
-- Revision:
-- A - initial design
-- B - modified op seq
--
-----------------------------
library ieee; --always use this library
use ieee.std_logic_1164.all; --always use this library
use ieee.numeric_std.all; --use this library if arithmetic required
--define connections to outside
entity ps02_siggen is
generic
(
data_width : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
A : out std_Logic_vector(data_width - 1 downto 0);
B : out std_logic_vector(data_width - 1 downto 0);
op : out std_logic_vector(3 downto 0)
);
end ps02_siggen;
--define inside of the module
architecture behavioral of ps02_siggen is
--define inside use signals
signal op_cnt : unsigned(3 downto 0) := x"0";
type A_B_value_array is array (0 to 15) of std_logic_vector(data_width - 1 downto 0);
signal A_list : A_B_value_array :=
(
std_logic_vector(to_signed(-15,data_width)), --sub
std_logic_vector(to_signed(-14,data_width)), --add
x"0000DEAD", --nand
x"0000BEEF", --and
x"0000ABCD", --or
x"0000EFAD", --nor
x"00001279", --xor
x"00000310", --not a
x"00003010", --not b
std_logic_vector(to_signed(-1,data_width)),--incr B
std_logic_vector(to_signed(0,data_width)),--incr A
std_logic_vector(to_signed(0,data_width)),--sub A
std_logic_vector(to_signed(0,data_width)),--sub B
x"00000F0F",--sll A
x"00000000",--sll B
x"00001234"--noop
);
signal B_list : A_B_value_array :=
(
std_logic_vector(to_signed(37,data_width)), --sub
std_logic_vector(to_signed(-999,data_width)), --add
x"00001221", --nand
x"00000FF0", --and
x"0000F00F", --or
x"00008754", --nor
x"0000ADBF", --xor
x"0000FECD", --not a
x"0000CCDC", --not b
std_logic_vector(to_signed(0,data_width)),--incr B
std_logic_vector(to_signed(-1,data_width)),--incr A
std_logic_vector(to_signed(0,data_width)),--sub A
std_logic_vector(to_signed(0,data_width)),--sub B
x"0000F0F0",--sll A
x"0000ABAB",--sll B
x"00004321"--noop
);
begin
--define the operation of the module!
A <= A_list(to_integer(op_cnt));
b <= B_list(to_integer(op_cnt));
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
op_cnt <= (others => '0'); --zero counter on rst
else
op_cnt <= op_cnt + 1;
end if;
end if;
end process;
end behavioral;