Update README.md

Merge pull request #1 from Clockfix/add-license-1
Create LICENSE
2020-02-10 21:28:51 +02:00 · 2020-02-10 21:19:15 +02:00 · 2020-02-10 21:19:05 +02:00 · 2020-02-10 21:06:18 +02:00 · 2020-01-21 21:26:29 +02:00 · 2020-01-21 21:23:47 +02:00
38 changed files with 3281 additions and 360 deletions
@@ -0,0 +1,2 @@
+*.asv
+matlab/sample_code_.m
@@ -14,73 +14,73 @@ set_property PACKAGE_PIN W5 [get_ports clk]


 ## Switches
-#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
-#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
-#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
-#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
-#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
-#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
-#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
-#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
-#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
-#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
-#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
-#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
-#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
-#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
-#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
-#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+set_property PACKAGE_PIN W17 [get_ports {sw[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
+set_property PACKAGE_PIN W15 [get_ports {sw[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
+set_property PACKAGE_PIN V15 [get_ports {sw[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
+set_property PACKAGE_PIN W14 [get_ports {sw[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
+set_property PACKAGE_PIN W13 [get_ports {sw[7]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
+set_property PACKAGE_PIN V2 [get_ports {sw[8]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
+set_property PACKAGE_PIN T3 [get_ports {sw[9]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
+set_property PACKAGE_PIN T2 [get_ports {sw[10]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
+set_property PACKAGE_PIN R3 [get_ports {sw[11]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
+set_property PACKAGE_PIN W2 [get_ports {sw[12]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
+set_property PACKAGE_PIN U1 [get_ports {sw[13]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
+set_property PACKAGE_PIN T1 [get_ports {sw[14]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
+set_property PACKAGE_PIN R2 [get_ports {sw[15]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
 

-## LEDs
-#set_property PACKAGE_PIN U16 [get_ports {led[0]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
-#set_property PACKAGE_PIN E19 [get_ports {led[1]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
-#set_property PACKAGE_PIN U19 [get_ports {led[2]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
-#set_property PACKAGE_PIN V19 [get_ports {led[3]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
-#set_property PACKAGE_PIN W18 [get_ports {led[4]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
-#set_property PACKAGE_PIN U15 [get_ports {led[5]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
-#set_property PACKAGE_PIN U14 [get_ports {led[6]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
-#set_property PACKAGE_PIN V14 [get_ports {led[7]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
-#set_property PACKAGE_PIN V13 [get_ports {led[8]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
-#set_property PACKAGE_PIN V3 [get_ports {led[9]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
-#set_property PACKAGE_PIN W3 [get_ports {led[10]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
-#set_property PACKAGE_PIN U3 [get_ports {led[11]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
-#set_property PACKAGE_PIN P3 [get_ports {led[12]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
-#set_property PACKAGE_PIN N3 [get_ports {led[13]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
-#set_property PACKAGE_PIN P1 [get_ports {led[14]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
-#set_property PACKAGE_PIN L1 [get_ports {led[15]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
+# LEDs
+set_property PACKAGE_PIN U16 [get_ports {led[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property PACKAGE_PIN E19 [get_ports {led[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property PACKAGE_PIN U19 [get_ports {led[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property PACKAGE_PIN V19 [get_ports {led[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+set_property PACKAGE_PIN W18 [get_ports {led[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
+set_property PACKAGE_PIN U15 [get_ports {led[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
+set_property PACKAGE_PIN U14 [get_ports {led[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
+set_property PACKAGE_PIN V14 [get_ports {led[7]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
+set_property PACKAGE_PIN V13 [get_ports {led[8]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
+set_property PACKAGE_PIN V3 [get_ports {led[9]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
+set_property PACKAGE_PIN W3 [get_ports {led[10]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
+set_property PACKAGE_PIN U3 [get_ports {led[11]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
+set_property PACKAGE_PIN P3 [get_ports {led[12]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
+set_property PACKAGE_PIN N3 [get_ports {led[13]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
+set_property PACKAGE_PIN P1 [get_ports {led[14]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
+set_property PACKAGE_PIN L1 [get_ports {led[15]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
 	
 	
 ##7 segment display
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2020 Imants Pulkstenis
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
@@ -1,3 +1,7 @@
+[![MIT license](https://img.shields.io/badge/License-MIT-blue.svg?style=plastic)](https://lbesson.mit-license.org/)
+![GitHub commit activity](https://img.shields.io/github/commit-activity/m/clockfix/audio_effects_FPGA?style=plastic)
+![GitHub last commit](https://img.shields.io/github/last-commit/clockfix/audio_effects_FPGA?style=plastic)
+![GitHub contributors](https://img.shields.io/github/contributors/clockfix/audio_effects_FPGA?style=plastic)
 # Audio effects on FPGA

 Audio effect synthesizer on FPGA
@@ -6,9 +10,17 @@ Audio hardware

 ![PMOD_I2S2](https://euborw.bl.files.1drv.com/y4mwscr7u3Q0WJKuOjfrLSFswmMhJFcQz_qvUDQmWPsWANUPPx3s-RrdHahplWN4MPxWtFJAZCzZokzS9oG3hJRHTa8-hztUF-5ix6DoEZ3FbW79HuWuWykaC6-vPQCz_jN-qtZzENmEM_CL7x6Fu-V3fVBwSbUUZ1B4FpyTJbHc2y09jmmIoznP9JKdHkloQC22fRvzkGEwn-uEL7m5GIYtg/pmod_i2s2.jpg) ![PMOD_I2S2_package](https://jhuenw.bl.files.1drv.com/y4mh-JRwzfInJGsB7npvB02QFP4E8O0fYseJrh7mCKZPhDtrRKAkyIU4vrSgIPZ57SPrRugP-CoS5pu-_W9fq1E2gV9SOYeyPc2In_a5uqQzCtwXbUYRvOQnHEt-zomphOLXn2Uw7RpaKbKLNvgQfF-pJNqbiX5LAaW5zODYNF66IESQ3uHqDSOCEtjt620oITZFzO71EyDkpSPB3bvZ61J6Q/pmod_i2s2_package.png)

+i2s timing diagram from PulseView
+![i2s timing diagram](https://jxuqnw.ch.files.1drv.com/y4m-dZeGZ7098LnxNfhcXYLc_boX5bUNKolrZoOikvJ15bhmx83OEfjXsL0DOx4bJQwo9Nj8JhPdbH3-p2_NsPtkQLQMjqqvHQD1aoTLU4iCGlzmuDkeRaJ4hOWEjlSxfPTpLuJmFxd3Co8m7PUNAHw-lSomMgNqrO4Sw_8E4K-vfiS2ijUOfIdlW4VUDLv0Dku1zcMel3jQGcMSIH0GiQyRA/i2s-loopback.png?psid=1)

 Top module
-![Top module_sh](https://sqtelw.bl.files.1drv.com/y4m3crragNjKRiiBnam_JQ72R1capMF7J4KFYmU9IC8ejan87w2KHOPl_SzV9Hyi6joKVl75qHteBc-DM81evlTdlBqJ8cgvCm6ISM2YxCEOrbJ7jEZR11jLt_6sS8Alucgz6lbZa-jescBHfFhU9g2CnuQqXTLzn9F3EoO2W4vQHQX8-6efsKfu73ZbmjWOWr9vgFpp42JJJO0DL6gPKsWxA/top-audio-effects.png?psid=1)
+![Top module_sh](https://sqtelw.ch.files.1drv.com/y4mxBDwlvgiYYZpsOjIUey0ctL7StvY-ymQdAxhs5_GToLB8sdDlbh9qd3IBUiguuYbraYpqDg2BVUclm8n7UIdIcLIz0468d-e_VIgsLgY13Z839dn2THBu_PKbq3MLZOmwJNjH0Jz8qq0SNr2UjZkyJjSmdmESf44Qv5DrNMVEhvl6jLvw0FxN23E7dme2MloArlCMLJ9PznU9qzNhD2RLw/top-audio-effects.png?psid=1)

-i2s timing diagram
-![i2s timing diagram](https://jxuqnw.ch.files.1drv.com/y4m-dZeGZ7098LnxNfhcXYLc_boX5bUNKolrZoOikvJ15bhmx83OEfjXsL0DOx4bJQwo9Nj8JhPdbH3-p2_NsPtkQLQMjqqvHQD1aoTLU4iCGlzmuDkeRaJ4hOWEjlSxfPTpLuJmFxd3Co8m7PUNAHw-lSomMgNqrO4Sw_8E4K-vfiS2ijUOfIdlW4VUDLv0Dku1zcMel3jQGcMSIH0GiQyRA/i2s-loopback.png?psid=1)
+Edited effect control module - now it has input and output FIFO memory
+![efect_controler](https://pgow6w.ch.files.1drv.com/y4mG--fP9LI78p-SQYukYLlqkbHOkXCmfO6cLVgHcND0Z5G7J7-75dlO2Yva33k0KdAt6DBWdQDT_TH_6L_pjNxXHaczVTaUecui2-qpfOD4EW0GP8TtewGPuC7wsESNzd0Nsl4QSDfLzFV8uZZWeq2_VTadlnqPmQRSfs9115fiK8yLqdl17fzZZ4Q0LuhbOlbFV0aOpUqC0zBi6_FxK_xtw/efect_controler.png?psid=1)
+
+IO module
+![io_module](https://b6w9pw.ch.files.1drv.com/y4mgPXnMZOMUJWVUBhbHNP217wE84t29_bt9uDZ7lbozZTPFiq3Ncan_uSvk7YjRzmkIPma5t_dcwxAvLgd8ZV5n1GBIzJ5cCEiS1gCR0y7y4x5brYBBRXjJh5VXI0ITpQRCvlggTSzNZE4b7Ux8hvzoxa586RGty8d-a1eblClQE3GD4QAiPMV0CrT-ROt7axdN_ArKMn0HKHCYomtW3Gu4A/io_module.png?psid=4)
+
+Effects module with one clipping effect
+![io_module](https://py4mqq.ch.files.1drv.com/y4m3dgfUf1rxceMtUYiJ-Y9GBDS-E2vBBSFrZIh3-UEhRQifIn5Lq2OAAWUWKqsSTMDNNwTtkgEVy9ThtV3UNbjI1OdDDeFvC1tHPhXdbbpdPpasInNJgWDzTLhCE88uy48NYx_IRecy4zoXUrYg9_SaEWggmjloEwWd4KuSFBtSyopP0pHQ07nnUMuo4OyEhdZOfptzF-PS-J2ufYQSEVheg/effect_module.png?psid=1)
@@ -0,0 +1,40 @@
+// Code from:
+// Vivado Design Suite
+// User Guide
+// Synthesis
+// UG901 (v2018.3) December 19, 2018
+//
+// Dual-Port Block RAM with Two Write Ports
+// File: blobkram.v
+
+module rams_tdp_rf_rf #( parameter
+    DEPTH =  16,
+    ADDR_WIDTH = 4, 
+    DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
+
+input                       clka,clkb,ena,enb,wea,web;
+input   [ADDR_WIDTH-1:0]    addra,addrb;
+input   [DATA_WIDTH-1:0]    dia,dib;
+output  [DATA_WIDTH-1:0]    doa,dob;
+reg     [DATA_WIDTH-1:0]    ram     [ DEPTH - 1 :0];
+reg     [DATA_WIDTH-1:0]    doa,dob;
+
+always @(posedge clka)
+begin
+    if (ena)
+    begin
+        if (wea)
+            ram[addra] <= dia;
+            doa <= ram[addra];
+        end
+    end
+always @(posedge clkb)
+begin
+    if (enb)
+    begin
+        if (web)
+            ram[addrb] <= dib;
+            dob <= ram[addrb];
+    end
+end
+endmodule
@@ -0,0 +1,107 @@
+module clipping_effect #( parameter
+    data_width = 16          // data width 
+)(
+    input                                   clk,
+    input                                   reset,
+    input   signed      [data_width-1: 0]   i_data,
+    output  signed      [data_width-1: 0]   o_data,
+    input   signed      [data_width-1: 0]   i_treshhold,
+    input                                   i_read_done,
+    output                                  o_read_enable,
+    output                                  o_data_valid,
+    input                                   i_data_ready
+);
+
+//-------------Internal Constants---------------------------
+localparam [1:0]        IDLE         = 'd0,
+                        CLIP         = 'd1,
+                        OUTPUT       = 'd2,
+                        CLEAR        = 'd3;
+
+reg [1:0] r_state=IDLE, r_next=IDLE;
+
+reg   signed      [data_width-1: 0]     r_data = 'b0;
+reg         [data_width-1: 0]     r_treshhold_p = 'b0;
+reg         [data_width-1: 0]     r_treshhold_n = 'b0;
+reg                                     r_read_enable = 0;
+reg                                     r_data_valid = 0;
+
+assign  o_read_enable   = r_read_enable;
+assign  o_data_valid    = r_data_valid;
+assign  o_data          = r_data;
+
+
+//---------state register sequential always block-----------
+always @(posedge clk ) begin
+    if (~reset) begin
+        r_state <= r_next;
+    end 
+end
+
+//----next state & outputs, combinational always block------
+
+always @(posedge clk ) begin
+    if (reset) begin
+        r_next <= IDLE;
+        r_read_enable <= 0;     // redy to read data
+        r_data_valid <= 0;
+    end   
+    else begin  
+    case(r_state)
+        IDLE    :   begin
+                        if (i_data_ready == 1) begin
+                            r_next <= CLIP;
+                            r_data <= i_data;
+                            r_treshhold_p <= i_treshhold;
+                            r_treshhold_n <= (~i_treshhold) + 1; // two compliment
+                            r_read_enable <= 0;
+                            r_data_valid <= 0;
+                        end
+                        else begin
+                            r_next <= IDLE;
+                            r_read_enable <= 1;     // redy to read data
+                            r_data_valid <= 0;
+                        end                     
+                    end
+        CLIP    :   begin
+                        case (r_data[data_width-1]) 
+                            0   :   begin           // positive number
+                                        if (r_data > r_treshhold_p) begin
+                                            r_data <= r_treshhold_p; end
+                                    end
+                            1   :   begin           // negative number               
+                                        if (r_data < r_treshhold_n) begin
+                                            r_data <= r_treshhold_n; end
+                                    end                  
+                        endcase
+                        r_next <= OUTPUT;
+                        r_data_valid <= 0;
+                        r_read_enable <= 0;     // read disable
+                    end
+        OUTPUT  :   begin
+                        if (i_read_done == 1) begin
+                            r_next <= CLEAR;
+                            r_data_valid <= 0;
+                            r_read_enable <= 0;
+                        end
+                        else begin
+                            r_next <= OUTPUT;
+                            r_data_valid <= 1;
+                            r_read_enable <= 0;     // read disable
+                        end
+                    end
+        CLEAR   :   begin
+                        r_next <= IDLE;
+                        r_data_valid  <= 0;
+                        r_read_enable <= 1;
+                    end
+        default:    begin
+                        r_next <= IDLE;          // on error
+                    end
+    endcase 
+    end
+end
+
+
+
+endmodule
@@ -0,0 +1,85 @@
+// This file is Test Bench for clipping module
+//  
+// 
+
+// 100MHz clock on Basys3 -> 10ns period
+// 50% duty cycle 5ns HIGH and 5ns LOW
+//`timescale [time unit] / [time precision]
+`timescale 10 ns / 1ns
+
+//sub modules
+`include "clipping.v"
+
+module clipping_tb#( parameter
+    data_width = 16          // data width 
+)();
+
+reg clk = 1'b0;
+reg signed [data_width-1 : 0]  i_data = 'b0; 
+reg i_read_done = 0;
+reg i_data_ready = 0;
+
+// 50% duty cycle clock
+always #0.5 clk <= ~clk;
+
+clipping_effect  #(
+    .data_width(data_width)                // data width
+) UUT (
+    .clk(clk),
+    .reset(1'b0),
+    .i_treshhold( 16'haff ),
+    .i_data(i_data),
+    .i_read_done(i_read_done),         // read done from effects controler
+    .i_data_ready(i_data_ready),
+    .o_data(),
+    .o_read_enable(),
+    .o_data_valid()  
+);
+
+initial begin
+    #030; 
+    i_data  = 'haaa;
+    #005;
+    i_data_ready = 1;
+    #005;
+    i_data  = 'h0fa;
+    #002;
+    i_read_done = 1;
+    #001;
+    i_read_done = 0;
+    #005;
+    i_data  =  -16'd3000;
+    #002;
+    i_read_done = 1;
+    #001;
+    i_read_done = 0;
+    #005;
+    i_data  =  852;
+    #002;
+    i_read_done = 1;
+    #001;
+    i_read_done = 0;
+end
+
+
+initial begin
+    #030_000; 
+    $display("*");
+
+    $display(" ");
+    $display("Use this command to open timing diagram:");
+    $display("gtkwave -f wave.vcd");
+    $display("----------------------------------------------");
+    $finish();
+end
+
+initial 
+  begin 
+    $display(" ");
+    $display("----------------------------------------------");
+    $display("          Starting Testbench...");
+    $dumpfile("wave.vcd");
+    $dumpvars(0);
+end
+
+endmodule
@@ -7,13 +7,13 @@ module clock_divider #(
    parameter DIVIDER =2,
    parameter WIDTH =2
 ) (
-    input clk,
+    input clk_in,
    output clk_out);

 reg state=1'b0, next_state=1'b1;
 reg [WIDTH-1:0] counter = DIVIDER-1 ; 

-always@(posedge clk)begin
+always@(posedge clk_in)begin
    state <= next_state;
    if ( counter == 0) begin
        next_state <= ~next_state;
@@ -0,0 +1,14 @@
+module d_flipflop_sync_rst(
+    input       D,
+    output  reg Q,
+    input       clk,
+    input       reset);
+
+always@(posedge clk, posedge reset)
+begin
+    if(reset)
+        Q <= 1'd0;
+    else
+        Q <= D;     
+end
+endmodule
@@ -1,23 +1,108 @@
 module effect_controler #( parameter
-    d_width = 24                // data width
+    d_width = 24,                // data width
+    address_width = 4,           // 
+    ram_depth = 16,              //
+    memory_d_width = 16          // 
 )(
-//    input clk,
-    input signed [d_width-1: 0] i_l_data,
-    input signed  [d_width-1: 0] i_r_data,
-    output reg signed [d_width-1: 0] o_l_data,
-    output  reg signed [d_width-1: 0] o_r_data
+    input                               mclk,   // io_module clock
+    input                               clk,    // main clock   
+    input                               reset,
+    input   signed      [d_width-1: 0]  i_l_data,
+    input   signed      [d_width-1: 0]  i_r_data,   // not used
+    output  signed      [d_width-1: 0]  o_l_data,
+    output  signed      [d_width-1: 0]  o_r_data,
+
+    output                                      o_read_done,    // read done from effects module
+    output                                      o_read_ready,   // ready read from effects module
+
+
+    input               [1:0]           sw,             // effect control swiches
+
+    output  signed      [memory_d_width-1: 0]   o_data_to_eff,     // Data output to effects module
+    output                                      o_data_valid,         // data valid to read (FIFO not empty). data valid signal to effect module
+    input                                       i_read_enable,          // enable read from input fifo 
+    input  signed      [memory_d_width-1: 0]    i_data_from_eff_sw0,     // Data output to effects module
+    input  signed      [memory_d_width-1: 0]    i_data_from_eff_sw1,     // Data output to effects module
+
+    input                                       i_dv_from_eff         // data valid to read (FIFO not empty). data valid signal to effect module
+     
 );

-always@* begin
-    o_l_data <= i_l_data;
-    o_r_data <= i_r_data;
-end
+wire signed [memory_d_width-1: 0]  w_o_data;        //output data to io_module 
+
+//wire signed [memory_d_width-1: 0]  w_o_data_eff;    //output data to effects module 
+
+wire                            w_empty_in, w_full_in;
+wire                            w_empty_out, w_full_out;
+
+wire  [memory_d_width-1:0]       w_data_to_fifo;         // wire connets mixer to output fifo
+
+wire  [address_width-1:0]       w_data_fill_input;      // shows how full are in FIFO memmory for intput
+wire  [address_width-1:0]       w_data_fill_output;     // shows how full are in FIFO memmory for output
+
+wire                            w_data_valid_to_fifo;   // data valid to write output FIFO from mixer           
+
+assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data;         // only left chanal are used in controler
+assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data;         // same as left
+
+assign o_data_valid = ~w_empty_in;
+
+// Input FIFO
+sync_fifo #( 
+   .ram_depth(ram_depth),               // ram memory depth
+   .address_width(address_width),       // ram memory address width
+   .data_width(memory_d_width)          // memory data width
+) fifo_input (
+   .data_out(o_data_to_eff),
+   .full(w_full_in),
+   .empty(w_empty_in),
+   .data_fill(w_data_fill_input),
+   .data_in(i_l_data[ d_width-1 : d_width - memory_d_width ]),       
+   .w_clk(mclk),
+   .r_clk(clk),
+   .reset(reset),
+   .wr_en( w_full_in  ? 1'b0 : 1'b1 ),          // checking is FIFO full
+   .rd_en( w_empty_in ? 1'b0 : i_read_enable )           // checking is FIFO empty
+);
+
+// Output FIFO
+sync_fifo #( 
+   .ram_depth(ram_depth),               // ram memory depth
+   .address_width(address_width),       // ram memory address width
+   .data_width(memory_d_width)          // memory data width
+) fifo_output (
+   .data_out(w_o_data),
+   .full(w_full_out),
+   .empty(w_empty_out),
+   .data_fill(w_data_fill),
+   .data_in(w_data_to_fifo),       
+   .w_clk(clk),
+   .r_clk(mclk),
+   .reset(reset),
+   .wr_en( w_data_valid_to_fifo ),     // checking of FIFO full are performing mixer module
+   .rd_en( w_empty_out ? 1'b0 : 1'b1 )                  // checking is FIFO empty
+);
+
+
+
+// Effect mixer, performs audio data  merging 
+effect_mixer #( 
+    .data_width(memory_d_width)             // memory data width
+) effect_mixer (
+    .sw(sw),
+    .clk(clk),
+    .reset(reset),
+    .i_fifo_full(w_full_out),
+    .o_read_done(o_read_done),              // read from effect module done
+    .o_read_ready(o_read_ready),            // ready to read from effect module
+    .o_data(w_data_to_fifo),                // data to output FIFO memory
+    .o_data_valid(w_data_valid_to_fifo),
+    .i_dv_from_eff(i_dv_from_eff),
+    .i_data_from_eff_sw0(i_data_from_eff_sw0),     // Data output to effects module
+    .i_data_from_eff_sw1(i_data_from_eff_sw1) 
+);

-//assign o_l_data = i_l_data;
-//assign o_r_data = i_r_data;


-//assign o_l_data = 24'h000000;
-//assign o_r_data = 24'h400008;

 endmodule
@@ -0,0 +1,130 @@
+module effect_mixer #( parameter
+    data_width = 16          // data width
+)(
+    input                                       clk,
+    input   [1:0]                               sw,
+    input                                       reset,
+    input                                       i_fifo_full,
+    output  signed      [data_width-1: 0]       o_data,
+    output                                      o_read_done,            // read from effect module done
+    output                                      o_read_ready,           // ready to read from effect module                    
+    output                                      o_data_valid,           // data valit to write in FIFO memory
+    input                                       i_dv_from_eff,
+    input  signed      [data_width-1: 0]    i_data_from_eff_sw0,     // Data output to effects module
+    input  signed      [data_width-1: 0]    i_data_from_eff_sw1 
+);
+
+//-------------Internal Constants---------------------------
+localparam [2:0]        IDLE         = 'd0,
+                        ADD          = 'd1,
+                        NORM         = 'd2,
+                        OUTPUT       = 'd3;
+
+reg [2:0] r_state=IDLE, r_next=IDLE;
+
+reg   signed      [data_width-1: 0]     r_data_sw0 = 'b0;
+reg   signed      [data_width-1: 0]     r_data_sw1 = 'b0;
+
+reg   signed      [data_width: 0]       r_data_add = 'b0;
+
+reg   signed      [data_width-1: 0]     r_data_norm = 'b0;
+
+reg     r_read_done = 0;
+reg     r_read_ready = 0;
+reg     r_data_valid = 0;
+
+assign o_read_done = r_read_done;
+assign o_data_valid = r_data_valid;
+assign o_data = r_data_norm;
+assign o_read_ready = r_read_ready;
+
+
+//---------state register sequential always block-----------
+always @(posedge clk ) begin
+    if (reset == 1) begin
+        // clear state
+        r_state <= IDLE;
+        r_next <= IDLE;
+    end
+    else begin
+        r_state <= r_next;
+    end 
+end
+
+//----next state & outputs, combinational always block------
+
+always @(posedge clk ) begin
+    
+    case(r_state)
+        IDLE    :   begin
+                        if (i_dv_from_eff == 1) begin
+                            r_next <= ADD;
+                            r_data_sw0 <= i_data_from_eff_sw0;
+                            r_data_sw1 <= i_data_from_eff_sw1;
+                            r_data_norm <= 'b0;
+                            r_read_done <= 1;
+                            r_read_ready <= 0;
+                            r_data_valid <= 0;
+                        end
+                        else begin
+                            r_next <= IDLE;
+                            r_read_ready <= 1;     // redy to read data
+                            r_data_valid <= 0;
+                        end                         
+                    end
+        ADD     :   begin
+                        case ( sw ) 
+                            0   :   begin           // off all sound
+                                        r_data_add <= 0;    
+                                    end
+                            1   :   begin           // no effect only             
+                                        r_data_add <= r_data_sw0;    
+                                    end
+                            2   :   begin           // clipping effect only               
+                                        r_data_add <= r_data_sw1;
+                                    end
+                            3   :   begin           // no effect and clipping effect               
+                                        r_data_add <= r_data_sw0 + r_data_sw1;
+                                    end                
+                        endcase
+                        r_next <= NORM;
+                        r_read_done <= 0; 
+                    end
+        NORM    :   begin
+                        case ( sw ) 
+                            0   :   begin           // off all sound
+                                        r_data_norm <= 0;    
+                                    end
+                            1   :   begin           // no effect only             
+                                        r_data_norm <= r_data_add[data_width-1: 0];    
+                                    end
+                            2   :   begin           // clipping effect only               
+                                        r_data_norm <= r_data_add[data_width-1: 0];
+                                    end
+                            3   :   begin           // no effect and clipping effect               
+                                        r_data_norm <= r_data_add[data_width  : 1] ;     // Shift Right
+                                    end                
+                        endcase
+                        r_next <= OUTPUT;
+                    end
+        OUTPUT  :   begin
+                        if ((i_fifo_full == 1) & (i_dv_from_eff == 1)) begin     // wait for FIFO memory and data valid in effect module 
+                            r_next          <= OUTPUT;
+                            r_read_done     <= 0;
+                            r_read_ready    <= 0;
+                            r_data_valid    <= 0;
+                        end
+                        else begin
+                            r_next          <= IDLE;
+                            r_read_ready    <= 0;     // redy to read data
+                            r_data_valid    <= 1;       // data valid to write in FIFO
+                        end  
+                    end
+        default: r_next <= IDLE;          // on error
+    endcase 
+end
+
+
+
+
+endmodule
@@ -0,0 +1,73 @@
+module effect_module #( parameter
+    d_width = 16                // data width
+)(
+    input                               clk,
+    input                               reset,
+    input               [1:0]           sw,             // effect control switches
+    input               [13:0]          i_treshhold,      // treshhold from switches
+    input                               i_data_ready,   // data ready to read
+    input   signed      [d_width-1: 0]  i_data,         // data input form effect controler
+    input                               i_read_done,    // read done from effects controler
+
+    output                              o_data_valid,
+    output                              o_read_enable,
+    // SW0 no effect
+    output  signed      [d_width-1: 0]  o_data_sw0,         // data output form effect controler
+    // SW1 clipping effect
+    output  signed      [d_width-1: 0]  o_data_sw1          // data output form effect controler
+
+
+    );
+
+// Wires for cliping effect
+wire  signed      [d_width-1: 0]        w_data_sw0;
+wire                                    w_read_enable_sw0;
+wire                                    w_data_valid_sw0;
+
+wire  signed      [d_width-1: 0]        w_data_sw1;
+wire                                    w_read_enable_sw1;
+wire                                    w_data_valid_sw1;
+
+// asynchronous logic ---------------------------------------
+
+assign o_data_sw0 = w_data_sw0;
+assign o_data_sw1 = w_data_sw1;
+
+assign o_read_enable = w_read_enable_sw0 & w_read_enable_sw1;
+assign o_data_valid = w_data_valid_sw0 & w_data_valid_sw1;
+
+// Individual effect modules -----------------------------
+
+// no effect    SW0
+no_effect #(
+    .data_width(d_width)               // data width
+) no_effect (
+    .clk(clk),
+    .reset(reset),
+    .i_data(i_data),
+    .i_read_done(i_read_done),         // read done from effects controler
+    .i_data_ready(i_data_ready),
+    .o_data(w_data_sw0),
+    .o_read_enable(w_read_enable_sw0),
+    .o_data_valid(w_data_valid_sw0)    
+);
+
+
+
+// clipping effect    SW1
+clipping_effect #(
+    .data_width(d_width)               // data width
+) clipping_effect (
+    .clk(clk),
+    .reset(reset),
+    .i_treshhold( {2'b00, i_treshhold } ),
+    .i_data(i_data),
+    .i_read_done(i_read_done),         // read done from effects controler
+    .i_data_ready(i_data_ready),
+    .o_data(w_data_sw1),
+    .o_read_enable(w_read_enable_sw1),
+    .o_data_valid(w_data_valid_sw1)   
+);
+
+
+endmodule
@@ -0,0 +1,95 @@
+// This file is Test Bench for clipping module
+//  
+// 
+// 100MHz clock on Basys3 -> 10ns period
+// 50% duty cycle 5ns HIGH and 5ns LOW
+//`timescale [time unit] / [time precision]
+`timescale 10 ns / 1ns
+
+//sub modules
+`include "clipping.v"
+`include "no_effect.v"
+
+//top module
+`include "effect_module.v"    
+
+module effect_tb#( parameter
+    data_width = 16          // data width 
+)();
+
+reg clk = 1'b0;
+reg signed [data_width-1 : 0]  i_data = 'b0; 
+reg i_read_done = 0;
+reg i_data_ready = 0;
+reg [1 : 0]  sw = 2'b01; 
+
+
+// 50% duty cycle clock
+always #0.5 clk <= ~clk;
+
+//Effect module contains all individual effects  
+effect_module #(
+    .d_width(data_width)                        // data width
+) effect_module (
+    .clk(clk),
+    .reset(1'b0),
+    .sw(sw),                                    // effect control swiches
+    .i_treshhold(14'h0ff),
+    .i_data_ready(i_data_ready),                // data ready to read
+    .i_read_done(i_read_done),                  // read done from effects controler
+    .i_data(i_data),                            // data input form effect controler
+    .o_read_enable(),                           // enable data reading
+    .o_data_valid(),
+    .o_data_sw0(),
+    .o_data_sw1()
+
+);
+
+initial begin
+    #030; 
+    i_data  = 'haaa;
+    #005;
+    i_data_ready = 1;
+    #005;
+    i_data  = 'h0fa;
+    i_data_ready = 0;
+    #002;
+    i_read_done = 1;
+    #001;
+    i_read_done = 0;
+    #005;
+    i_data  =  -16'd3000;
+    #002;
+    i_read_done = 1;
+    #001;
+    i_read_done = 0;
+    #005;
+    i_data  =  852;
+    #002;
+    i_read_done = 1;
+    #001;
+    i_read_done = 0;
+end
+
+
+initial begin
+    #030_000; 
+    $display("*");
+
+    $display(" ");
+    $display("Use this command to open timing diagram:");
+    $display("gtkwave -f wave.vcd");
+    $display("----------------------------------------------");
+    $finish();
+end
+
+initial 
+  begin 
+    $display(" ");
+    $display("----------------------------------------------");
+    $display("          Starting Testbench...");
+    $dumpfile("wave.vcd");
+    $dumpvars(0);
+end
+
+endmodule
@@ -1,4 +1,4 @@
-// This I2S Playback design uses the common 44.1 kHz 
+// This I2S design uses the common 44.1 kHz 
 // sampling frequency.  
 // From Figure 2 in Section 4.1.1 of the CS5343 
 // Datasheet, it is appropriate to use an SCLK/LRCK 
@@ -0,0 +1,90 @@
+module io_module #( parameter
+    sclk_ws_ratio = 64,         // number of sclk periods per word select period
+    mclk_sclk_ratio = 4,        // number of mclk periods per sclk period
+    d_width = 24                // data width
+)(
+    //output reset,                             //asynchronous active low reset
+    input  mclk,                                //master clock
+    output ad_sclk,                             //serial clock (or bit clock)
+    output ad_ws,                               //word select (or left-right clock)
+    output da_sclk,                             //serial clock (or bit clock)
+    output da_ws,                               //word select (or left-right clock)
+    output sd_tx,                               //serial data transmit
+    input  sd_rx,                               //serial data receive
+
+    input signed [d_width-1: 0] l_data_tx,      //left channel data to transmit
+    input signed [d_width-1: 0] r_data_tx,      //right channel data to transmit
+
+    output signed [d_width-1: 0] l_data_rx,            //left channel data received
+    output signed [d_width-1: 0] r_data_rx,             //right channel data received   
+
+    input reset,
+    
+    // // inputs to logic analyzer
+    // input           ch0,
+    // input           ch1,
+    // input           ch2,
+    // input           ch3,
+    // input           ch4,
+    // input           ch5,
+    // input           ch6,
+    // input           ch7,
+
+    output  [7: 0]  JXADC      // output for logic analizer
+
+    );
+
+
+
+i2s_sender  #(
+    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
+    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
+    .d_width(d_width)                       //data width
+) i2s_sender (
+    .reset_n(reset),        //asynchronous active high reset
+    .mclk(mclk),            //master clock
+    .sclk(da_sclk),         //serial clock (or bit clock)
+    .ws(da_ws),             //word select (or left-right clock)
+    .sd_tx(sd_tx),          //serial data transmit
+    .l_data_tx(l_data_tx),  //left channel data to transmit
+    .r_data_tx(r_data_tx)   //right channel data to transmit
+);
+
+
+
+i2s_receicer  #(
+    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
+    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
+    .d_width(d_width)                       //data width
+) i2s_receicer (
+    .reset_n(reset),            //asynchronous active high reset
+    .mclk(mclk),                //master clock
+    .sclk(ad_sclk),             //serial clock (or bit clock)
+    .ws(ad_ws),                 //word select (or left-right clock)
+    .sd_rx(sd_rx),              //serial data receive
+    .l_data_rx(l_data_rx),      //left channel data received
+    .r_data_rx(r_data_rx)       //right channel data received
+);
+
+
+// connecting signals to JXADC PMOD to monitor them with signal analyzer
+JXADC_controler JXADC_controler(
+    .ch0(mclk),
+    .ch1(ad_sclk),
+    .ch2(ad_ws),
+    .ch3(sd_rx),        // serial data in
+    .ch4(mclk),
+    .ch5(da_sclk),
+    .ch6(da_ws),
+    .ch7(sd_tx),        // serial data out
+    .JXADC(JXADC)       // output for logic analizer   
+);
+
+// // debounce reset button
+// debounce_switch debounce_switch_reset(
+//     .clk(mclk),
+//     .i_switch(btnC),
+//     .o_switch(reset_n)
+// );
+
+endmodule
@@ -0,0 +1,659 @@
+
+<!DOCTYPE html
+  PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head>
+      <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+   <!--
+This HTML was auto-generated from MATLAB code.
+To make changes, update the MATLAB code and republish this document.
+      --><title>myfft3</title><meta name="generator" content="MATLAB 9.3"><link rel="schema.DC" href="http://purl.org/dc/elements/1.1/"><meta name="DC.date" content="2019-12-27"><meta name="DC.source" content="myfft3.m"><style type="text/css">
+html,body,div,span,applet,object,iframe,h1,h2,h3,h4,h5,h6,p,blockquote,pre,a,abbr,acronym,address,big,cite,code,del,dfn,em,font,img,ins,kbd,q,s,samp,small,strike,strong,sub,sup,tt,var,b,u,i,center,dl,dt,dd,ol,ul,li,fieldset,form,label,legend,table,caption,tbody,tfoot,thead,tr,th,td{margin:0;padding:0;border:0;outline:0;font-size:100%;vertical-align:baseline;background:transparent}body{line-height:1}ol,ul{list-style:none}blockquote,q{quotes:none}blockquote:before,blockquote:after,q:before,q:after{content:'';content:none}:focus{outine:0}ins{text-decoration:none}del{text-decoration:line-through}table{border-collapse:collapse;border-spacing:0}
+
+html { min-height:100%; margin-bottom:1px; }
+html body { height:100%; margin:0px; font-family:Arial, Helvetica, sans-serif; font-size:10px; color:#000; line-height:140%; background:#fff none; overflow-y:scroll; }
+html body td { vertical-align:top; text-align:left; }
+
+h1 { padding:0px; margin:0px 0px 25px; font-family:Arial, Helvetica, sans-serif; font-size:1.5em; color:#d55000; line-height:100%; font-weight:normal; }
+h2 { padding:0px; margin:0px 0px 8px; font-family:Arial, Helvetica, sans-serif; font-size:1.2em; color:#000; font-weight:bold; line-height:140%; border-bottom:1px solid #d6d4d4; display:block; }
+h3 { padding:0px; margin:0px 0px 5px; font-family:Arial, Helvetica, sans-serif; font-size:1.1em; color:#000; font-weight:bold; line-height:140%; }
+
+a { color:#005fce; text-decoration:none; }
+a:hover { color:#005fce; text-decoration:underline; }
+a:visited { color:#004aa0; text-decoration:none; }
+
+p { padding:0px; margin:0px 0px 20px; }
+img { padding:0px; margin:0px 0px 20px; border:none; }
+p img, pre img, tt img, li img, h1 img, h2 img { margin-bottom:0px; } 
+
+ul { padding:0px; margin:0px 0px 20px 23px; list-style:square; }
+ul li { padding:0px; margin:0px 0px 7px 0px; }
+ul li ul { padding:5px 0px 0px; margin:0px 0px 7px 23px; }
+ul li ol li { list-style:decimal; }
+ol { padding:0px; margin:0px 0px 20px 0px; list-style:decimal; }
+ol li { padding:0px; margin:0px 0px 7px 23px; list-style-type:decimal; }
+ol li ol { padding:5px 0px 0px; margin:0px 0px 7px 0px; }
+ol li ol li { list-style-type:lower-alpha; }
+ol li ul { padding-top:7px; }
+ol li ul li { list-style:square; }
+
+.content { font-size:1.2em; line-height:140%; padding: 20px; }
+
+pre, code { font-size:12px; }
+tt { font-size: 1.2em; }
+pre { margin:0px 0px 20px; }
+pre.codeinput { padding:10px; border:1px solid #d3d3d3; background:#f7f7f7; }
+pre.codeoutput { padding:10px 11px; margin:0px 0px 20px; color:#4c4c4c; }
+pre.error { color:red; }
+
+@media print { pre.codeinput, pre.codeoutput { word-wrap:break-word; width:100%; } }
+
+span.keyword { color:#0000FF }
+span.comment { color:#228B22 }
+span.string { color:#A020F0 }
+span.untermstring { color:#B20000 }
+span.syscmd { color:#B28C00 }
+
+.footer { width:auto; padding:10px 0px; margin:25px 0px 0px; border-top:1px dotted #878787; font-size:0.8em; line-height:140%; font-style:italic; color:#878787; text-align:left; float:none; }
+.footer p { margin:0px; }
+.footer a { color:#878787; }
+.footer a:hover { color:#878787; text-decoration:underline; }
+.footer a:visited { color:#878787; }
+
+table th { padding:7px 5px; text-align:left; vertical-align:middle; border: 1px solid #d6d4d4; font-weight:bold; }
+table td { padding:7px 5px; text-align:left; vertical-align:top; border:1px solid #d6d4d4; }
+
+
+
+
+
+  </style></head><body><div class="content"><h2>Contents</h2><div><ul><li><a href="#1">FFT algoritm</a></li><li><a href="#2">Data preparation for FFT</a></li><li><a href="#3">First stage</a></li><li><a href="#4">Second stage</a></li><li><a href="#5">Therd stage</a></li><li><a href="#6">4th stage</a></li><li><a href="#7">5th stage</a></li><li><a href="#8">Ploting out</a></li></ul></div><h2 id="1">FFT algoritm</h2><pre class="codeinput">clear;                      <span class="comment">% clears all previus values from memory</span>
+clc;                        <span class="comment">% clear command window</span>
+fs =  44100;                <span class="comment">% samplinf freq.</span>
+fftLength=32;               <span class="comment">% windowlength</span>
+
+<span class="comment">% signal frequencies</span>
+data_length = 8;           <span class="comment">% data length in FPGA calculations</span>
+max = 2^(data_length-1) - 1 ;            <span class="comment">% max aplitude 2^n  /2</span>
+
+f1 = 1000;
+a1 = max/2;
+
+f2 = 0;
+a2 = max/4;
+
+f3 = 8000;
+a3 = max/2;
+
+<span class="comment">% calculating signals</span>
+comp1 = a1 * cos(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * cos(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * cos(2*pi*f3*[0:1/fs:1]);
+
+<span class="comment">% calculatin vector values for step function</span>
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+<span class="comment">%data = [ d1 , d2];                  % creates vector with step function</span>
+data = comp1 + comp2 + comp3;      <span class="comment">% creates vector from 3 sin functions</span>
+
+figure(1)               <span class="comment">% plots separete sin functions</span>
+plot ( comp1, <span class="string">'-'</span>);
+hold <span class="string">on</span>;
+plot ( comp2, <span class="string">'-'</span>);
+plot ( comp3, <span class="string">'-'</span>);
+xlim([1 50])
+title(<span class="string">'Separete SIN functions'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'time'</span>)
+hold <span class="string">off</span>;
+
+figure(2)               <span class="comment">% plots signal for fft</span>
+plot ( data);
+title(<span class="string">'Signal for FFT analysis FFT'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'time'</span>)
+xlim([1 100])
+
+figure(3)               <span class="comment">% plots resultinf fft from Matlab functions</span>
+ft =fft(data,fftLength);
+ftMag=abs(ft(1:fftLength/2));
+stem (ftMag)
+title(<span class="string">'Linear Magnitude FFT'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'kHz'</span>)
+
+xt = xticks;        <span class="comment">% returns the current x-axis tick values as a vector</span>
+fstep = fs/fftLength;       <span class="comment">% tick of f axis in f domain</span>
+xtnew = round((xt-1)*fstep/1000, 1) ;   <span class="comment">% calculate new tick in kHz</span>
+xticklabels(xtnew)      <span class="comment">% set new tick labels</span>
+
+<span class="comment">% figure(4)               % plots resultinf fft(in dB)  from Matlab functions</span>
+<span class="comment">% ft =fft(data,fftLength);</span>
+<span class="comment">% ftMag=abs(ft(1:fftLength/2));</span>
+<span class="comment">% plot (20*log10(ftMag))</span>
+<span class="comment">% title('dB Magnitude')</span>
+<span class="comment">% ylabel('dB'), xlabel('kHz')</span>
+<span class="comment">%</span>
+<span class="comment">% xt = xticks;        % returns the current x-axis tick values as a vector</span>
+<span class="comment">% fstep = fs/fftLength;       % tick of f axis in f domain</span>
+<span class="comment">% xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz</span>
+<span class="comment">% xticklabels(xtnew)      % set new tick labels</span>
+</pre><img vspace="5" hspace="5" src="myfft3_01.png" alt=""> <img vspace="5" hspace="5" src="myfft3_02.png" alt=""> <img vspace="5" hspace="5" src="myfft3_03.png" alt=""> <h2 id="2">Data preparation for FFT</h2><pre class="codeinput"><span class="comment">% reverse bit calulation</span>
+bits = length(dec2bin( fftLength - 1 ));    <span class="comment">% how many bits in binary number</span>
+rev_bit_dec = zeros(1,fftLength);           <span class="comment">% create vektor size of fftlength</span>
+
+<span class="keyword">for</span> n=1:fftLength
+    bin_num = dec2bin(n-1 , bits);          <span class="comment">% converting to binary number</span>
+    rev_bit = [];                           <span class="comment">% create empty vector</span>
+    <span class="keyword">for</span> k=bits:-1:1
+       rev_bit = [rev_bit , bin_num(k)];
+    <span class="keyword">end</span>
+    rev_bit_dec(n) = bin2dec(rev_bit) ;     <span class="comment">% add 1 to match Matlab numbering</span>
+<span class="keyword">end</span>
+
+<span class="comment">%  creating array</span>
+<span class="comment">%  create empty array to store values in reverse bit order</span>
+stage = zeros(bits + 1,fftLength);
+
+<span class="keyword">for</span> n=1:fftLength
+     stage(1,n)  =  data(rev_bit_dec(n)+1);
+<span class="keyword">end</span>
+
+<span class="comment">% Calculating W twiddling factor for all stages</span>
+<span class="keyword">for</span> n = 1 : fftLength/2
+    W(n)  = exp(-1i * (n-1) * 2 * pi/ fftLength );
+<span class="keyword">end</span>
+
+<span class="comment">% convert to fixed point mumber -&gt; sfi(v,w,f) returns a signed fixed-point object with value v, word length w, and fraction length f.</span>
+Wr = sfi(real(W),data_length,data_length-2);
+Wi = sfi(imag(W),data_length,data_length-2);
+
+st_real = sfi(real(stage) , data_length + 3 , 0);
+st_imag = sfi(imag(stage) , data_length + 3 , 0);
+<span class="comment">% temp values for multiplaying with W twiddling factor</span>
+st_real_tmp = sfi(real(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+st_imag_tmp = sfi(imag(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+</pre><h2 id="3">First stage</h2><pre class="codeinput"><span class="keyword">for</span> n = 1 : 2^1 : fftLength
+    <span class="comment">% Even</span>
+    stage(2,n)    = stage(1,n) + stage(1,n+1);
+    <span class="comment">% Odd</span>
+    stage(2,n+1)  = stage(1,n) - stage(1,n+1);
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^1 : fftLength
+    <span class="comment">% Even</span>
+    st_real(2,n)    = st_real(1,n) + st_real(1,n+1);
+    <span class="comment">% imag is 0</span>
+    <span class="comment">% Odd</span>
+    st_real(2,n+1)  = st_real(1,n) - st_real(1,n+1);
+    <span class="comment">% imag is 0</span>
+<span class="keyword">end</span>
+</pre><h2 id="4">Second stage</h2><pre class="codeinput"><span class="comment">% Calculating W twiddling factor</span>
+<span class="keyword">for</span> n = 1 : 2
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 4 );
+<span class="keyword">end</span>
+
+<span class="comment">% calculate next stage values</span>
+<span class="keyword">for</span> n = 1 : 2^2 : fftLength
+    <span class="comment">% Even pair</span>
+        stage(3,n+0)   = stage(2,n+0) + Wn(1)*stage(2,n+2);
+        stage(3,n+1)   = stage(2,n+1) + Wn(2)*stage(2,n+3);
+    <span class="comment">% Odd par</span>
+        stage(3,n+2)   = stage(2,n+0) - Wn(1)*stage(2,n+2);
+        stage(3,n+3)   = stage(2,n+1) - Wn(2)*stage(2,n+3);
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^2 : fftLength
+    <span class="comment">% Even pair</span>
+        st_real(3,n+0)   = st_real(2,n+0) + st_real(2,n+2);
+        <span class="comment">% imag is 0</span>
+        st_real(3,n+1)   = st_real(2,n+1) ;         <span class="comment">% real is 0</span>
+        st_imag(3,n+1)   = -1 * st_real(2,n+3);     <span class="comment">% mult -j</span>
+    <span class="comment">% Odd par</span>
+        st_real(3,n+2)   = st_real(2,n+0) - st_real(2,n+2);
+        <span class="comment">% imag is 0</span>
+        st_real(3,n+3)   = st_real(2,n+1) ;         <span class="comment">% real is 0</span>
+        st_imag(3,n+3)   = st_real(2,n+3);          <span class="comment">% mult -j</span>
+<span class="keyword">end</span>
+</pre><h2 id="5">Therd stage</h2><pre class="codeinput"><span class="comment">% Calculating W twiddling factor</span>
+<span class="keyword">for</span> n = 1 : 4
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 8 );
+<span class="keyword">end</span>
+
+<span class="comment">% calculate next stage values</span>
+<span class="keyword">for</span> n = 1 : 2^3 : fftLength
+    <span class="keyword">for</span> k = 0 : 3
+        <span class="comment">% Even pair</span>
+        stage(4,n+k)   = stage(3,n+k) + Wn(k+1)*stage(3,n+k+4);
+        <span class="comment">% Odd par</span>
+        stage(4,n+k+4) = stage(3,n+k) - Wn(k+1)*stage(3,n+k+4);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^3 : fftLength
+    <span class="keyword">for</span> k = 0 : 3
+        st_real_tmp(3,n+k+4) = ( Wr(k*4+1) * st_real(3,n+k+4) ) - (  Wi(k*4+1) * st_imag(3,n+k+4) );
+        st_imag_tmp(3,n+k+4) = ( Wi(k*4+1) * st_real(3,n+k+4) ) + (  Wr(k*4+1) * st_imag(3,n+k+4) );
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+<span class="keyword">for</span> n = 1 : 2^3 : fftLength
+    <span class="keyword">for</span> k = 0 : 3
+        <span class="comment">% Even pair</span>
+        st_real(4,n+k)   = st_real(3,n+k) + st_real_tmp(3,n+k+4);
+        st_imag(4,n+k)   = st_imag(3,n+k) + st_imag_tmp(3,n+k+4);
+        <span class="comment">% Odd par</span>
+        st_real(4,n+k+4) = st_real(3,n+k) - st_real_tmp(3,n+k+4);
+        st_imag(4,n+k+4) = st_imag(3,n+k) - st_imag_tmp(3,n+k+4);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+</pre><h2 id="6">4th stage</h2><pre class="codeinput"><span class="comment">% Calculating W twiddling factor</span>
+<span class="keyword">for</span> n = 1 : 8
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 16 );
+<span class="keyword">end</span>
+
+<span class="comment">% calculate next stage values</span>
+<span class="keyword">for</span> n = 1 : 2^4 : fftLength
+    <span class="keyword">for</span> k = 0 : 7
+        <span class="comment">% Even pair</span>
+        stage(5,n+k)    = stage(4,n+k) + Wn(k+1)*stage(4,n+k+8);
+        <span class="comment">% Odd par</span>
+        stage(5,n+k+8)  = stage(4,n+k) - Wn(k+1)*stage(4,n+k+8);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^4 : fftLength
+    <span class="keyword">for</span> k = 0 : 7
+         st_real_tmp(4,n+k+8) = ( Wr(k*2+1) * st_real(4,n+k+8) ) - (  Wi(k*2+1) * st_imag(4,n+k+8) );
+         st_imag_tmp(4,n+k+8) = ( Wi(k*2+1) * st_real(4,n+k+8) ) + (  Wr(k*2+1) * st_imag(4,n+k+8) );
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+<span class="keyword">for</span> n = 1 : 2^4 : fftLength
+    <span class="keyword">for</span> k = 0 : 7
+        <span class="comment">% Even pair</span>
+        st_real(5,n+k)    = st_real(4,n+k) + st_real_tmp(4,n+k+8);
+        st_imag(5,n+k)    = st_imag(4,n+k) + st_imag_tmp(4,n+k+8);
+        <span class="comment">% Odd par</span>
+        st_real(5,n+k+8)  = st_real(4,n+k) - st_real_tmp(4,n+k+8);
+        st_imag(5,n+k+8)  = st_imag(4,n+k) - st_imag_tmp(4,n+k+8);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+</pre><h2 id="7">5th stage</h2><pre class="codeinput"><span class="comment">% Calculating W twiddling factor</span>
+<span class="keyword">for</span> n = 1 : 16
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 32 );
+<span class="keyword">end</span>
+
+<span class="comment">% calculate next stage values</span>
+<span class="keyword">for</span> n = 1 : 2^5 : fftLength
+    <span class="keyword">for</span> k = 0 : 15
+        <span class="comment">% Even pair</span>
+        stage(6,n+k)    = stage(5,n+k) + Wn(k+1)*stage(5,n+k+16);
+        <span class="comment">% Odd par</span>
+        stage(6,n+k+16)  = stage(5,n+k) - Wn(k+1)*stage(5,n+k+16);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^5 : fftLength
+    <span class="keyword">for</span> k = 0 : 15
+         st_real_tmp(5,n+k+16) = ( Wr(k*1+1) * st_real(5,n+k+16) ) - (  Wi(k*1+1) * st_imag(5,n+k+16) );
+         st_imag_tmp(5,n+k+16) = ( Wi(k*1+1) * st_real(5,n+k+16) ) + (  Wr(k*1+1) * st_imag(5,n+k+16) );
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+<span class="keyword">for</span> n = 1 : 2^5 : fftLength
+    <span class="keyword">for</span> k = 0 : 15
+        <span class="comment">% Even pair</span>
+        st_real(6,n+k)    = st_real(5,n+k) + st_real_tmp(5,n+k+16);
+        st_imag(6,n+k)    = st_imag(5,n+k) + st_imag_tmp(5,n+k+16);
+        <span class="comment">% Odd par</span>
+        st_real(6,n+k+16)  = st_real(5,n+k) - st_real_tmp(5,n+k+16);
+        st_imag(6,n+k+16)  = st_imag(5,n+k) - st_imag_tmp(5,n+k+16);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+</pre><h2 id="8">Ploting out</h2><p>slowly plot result</p><pre class="codeinput">figure(5)
+<span class="keyword">for</span> n = 1 : bits +1
+    <span class="comment">%plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );</span>
+    stem( abs( stage(n,1:fftLength/2) ) );
+<span class="comment">%     pause(1);</span>
+<span class="keyword">end</span>
+xt = xticks;        <span class="comment">% returns the current x-axis tick values as a vector</span>
+fstep = fs/fftLength;       <span class="comment">% tick of f axis in f domain</span>
+xtnew = round((xt-1)*fstep/1000, 1) ;   <span class="comment">% calculate new tick in kHz</span>
+xticklabels(xtnew)      <span class="comment">% set new tick labels</span>
+title(<span class="string">'FFT using custom function'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'kHz'</span>)
+
+figure(6)
+<span class="keyword">for</span> n = 1 : bits +1
+    <span class="comment">%plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );</span>
+    temp = st_real + 1i * st_imag;
+    stem( abs( temp(n,1:fftLength/2) ) );
+<span class="comment">%      pause(1);</span>
+<span class="keyword">end</span>
+xt = xticks;        <span class="comment">% returns the current x-axis tick values as a vector</span>
+fstep = fs/fftLength;       <span class="comment">% tick of f axis in f domain</span>
+xtnew = round((xt-1)*fstep/1000, 1) ;   <span class="comment">% calculate new tick in kHz</span>
+xticklabels(xtnew)      <span class="comment">% set new tick labels</span>
+title(<span class="string">'FFT using custom function real/imag separate'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'kHz'</span>)
+
+figure(7)
+dif2 = 100* abs(temp(bits +1,1:fftLength/2) - ft(1:fftLength/2))./abs(ft(1:fftLength/2)) ;
+plot(dif2, <span class="string">'blue'</span>)
+title(<span class="string">'Difference in calculations'</span>)
+xt = xticks;        <span class="comment">% returns the current x-axis tick values as a vector</span>
+fstep = fs/fftLength;       <span class="comment">% tick of f axis in f domain</span>
+xtnew = round((xt-1)*fstep/1000, 1) ;   <span class="comment">% calculate new tick in kHz</span>
+xticklabels(xtnew)      <span class="comment">% set new tick labels</span>
+ylabel(<span class="string">'percents, %'</span>), xlabel(<span class="string">'kHz'</span>)
+</pre><img vspace="5" hspace="5" src="myfft3_04.png" alt=""> <img vspace="5" hspace="5" src="myfft3_05.png" alt=""> <img vspace="5" hspace="5" src="myfft3_06.png" alt=""> <p class="footer"><br><a href="http://www.mathworks.com/products/matlab/">Published with MATLAB&reg; R2017b</a><br></p></div><!--
+##### SOURCE BEGIN #####
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=32;               % windowlength 
+
+% signal frequencies
+data_length = 8;           % data length in FPGA calculations 
+max = 2^(data_length-1) - 1 ;            % max aplitude 2^n  /2 
+
+f1 = 1000;
+a1 = max/2;
+
+f2 = 0;
+a2 = max/4;
+
+f3 = 8000;
+a3 = max/2;
+
+% calculating signals 
+comp1 = a1 * cos(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * cos(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * cos(2*pi*f3*[0:1/fs:1]);
+
+% calculatin vector values for step function
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+%data = [ d1 , d2];                  % creates vector with step function
+data = comp1 + comp2 + comp3;      % creates vector from 3 sin functions
+
+figure(1)               % plots separete sin functions
+plot ( comp1, '-');
+hold on;
+plot ( comp2, '-');
+plot ( comp3, '-');
+xlim([1 50])
+title('Separete SIN functions') 
+ylabel('magnitude'), xlabel('time') 
+hold off;
+
+figure(2)               % plots signal for fft
+plot ( data);
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+xlim([1 100])
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft =fft(data,fftLength); 
+ftMag=abs(ft(1:fftLength/2)); 
+stem (ftMag)
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
+
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+
+% figure(4)               % plots resultinf fft(in dB)  from Matlab functions
+% ft =fft(data,fftLength); 
+% ftMag=abs(ft(1:fftLength/2)); 
+% plot (20*log10(ftMag))
+% title('dB Magnitude') 
+% ylabel('dB'), xlabel('kHz') 
+% 
+% xt = xticks;        % returns the current x-axis tick values as a vector
+% fstep = fs/fftLength;       % tick of f axis in f domain 
+% xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+% xticklabels(xtnew)      % set new tick labels
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);           % create vektor size of fftlength
+
+for n=1:fftLength
+    bin_num = dec2bin(n-1 , bits);          % converting to binary number
+    rev_bit = [];                           % create empty vector
+    for k=bits:-1:1
+       rev_bit = [rev_bit , bin_num(k)];
+    end
+    rev_bit_dec(n) = bin2dec(rev_bit) ;     % add 1 to match Matlab numbering   
+end
+
+%  creating array
+%  create empty array to store values in reverse bit order
+stage = zeros(bits + 1,fftLength);
+
+for n=1:fftLength
+     stage(1,n)  =  data(rev_bit_dec(n)+1);
+end
+
+% Calculating W twiddling factor for all stages 
+for n = 1 : fftLength/2 
+    W(n)  = exp(-1i * (n-1) * 2 * pi/ fftLength );
+end
+
+% convert to fixed point mumber -> sfi(v,w,f) returns a signed fixed-point object with value v, word length w, and fraction length f.
+Wr = sfi(real(W),data_length,data_length-2);       
+Wi = sfi(imag(W),data_length,data_length-2);
+
+st_real = sfi(real(stage) , data_length + 3 , 0);
+st_imag = sfi(imag(stage) , data_length + 3 , 0);
+% temp values for multiplaying with W twiddling factor
+st_real_tmp = sfi(real(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+st_imag_tmp = sfi(imag(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+
+%% First stage
+
+for n = 1 : 2^1 : fftLength 
+    % Even
+    stage(2,n)    = stage(1,n) + stage(1,n+1);
+    % Odd
+    stage(2,n+1)  = stage(1,n) - stage(1,n+1);
+end
+
+% calculations using separate real and imaginary numbers 
+for n = 1 : 2^1 : fftLength 
+    % Even
+    st_real(2,n)    = st_real(1,n) + st_real(1,n+1);
+    % imag is 0
+    % Odd
+    st_real(2,n+1)  = st_real(1,n) - st_real(1,n+1);
+    % imag is 0
+end
+
+%% Second stage
+
+% Calculating W twiddling factor 
+for n = 1 : 2 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 4 );
+end
+
+% calculate next stage values
+for n = 1 : 2^2 : fftLength 
+    % Even pair
+        stage(3,n+0)   = stage(2,n+0) + Wn(1)*stage(2,n+2); 
+        stage(3,n+1)   = stage(2,n+1) + Wn(2)*stage(2,n+3); 
+    % Odd par
+        stage(3,n+2)   = stage(2,n+0) - Wn(1)*stage(2,n+2); 
+        stage(3,n+3)   = stage(2,n+1) - Wn(2)*stage(2,n+3); 
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^2 : fftLength 
+    % Even pair
+        st_real(3,n+0)   = st_real(2,n+0) + st_real(2,n+2); 
+        % imag is 0
+        st_real(3,n+1)   = st_real(2,n+1) ;         % real is 0
+        st_imag(3,n+1)   = -1 * st_real(2,n+3);     % mult -j
+    % Odd par
+        st_real(3,n+2)   = st_real(2,n+0) - st_real(2,n+2); 
+        % imag is 0
+        st_real(3,n+3)   = st_real(2,n+1) ;         % real is 0
+        st_imag(3,n+3)   = st_real(2,n+3);          % mult -j
+end
+
+
+%% Therd stage
+
+% Calculating W twiddling factor 
+for n = 1 : 4 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 8 );
+end
+
+% calculate next stage values
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        % Even pair
+        stage(4,n+k)   = stage(3,n+k) + Wn(k+1)*stage(3,n+k+4);   
+        % Odd par
+        stage(4,n+k+4) = stage(3,n+k) - Wn(k+1)*stage(3,n+k+4); 
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        st_real_tmp(3,n+k+4) = ( Wr(k*4+1) * st_real(3,n+k+4) ) - (  Wi(k*4+1) * st_imag(3,n+k+4) );   
+        st_imag_tmp(3,n+k+4) = ( Wi(k*4+1) * st_real(3,n+k+4) ) + (  Wr(k*4+1) * st_imag(3,n+k+4) ); 
+    end
+end
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        % Even pair
+        st_real(4,n+k)   = st_real(3,n+k) + st_real_tmp(3,n+k+4);  
+        st_imag(4,n+k)   = st_imag(3,n+k) + st_imag_tmp(3,n+k+4);
+        % Odd par
+        st_real(4,n+k+4) = st_real(3,n+k) - st_real_tmp(3,n+k+4); 
+        st_imag(4,n+k+4) = st_imag(3,n+k) - st_imag_tmp(3,n+k+4); 
+    end
+end
+
+
+%% 4th stage  
+
+% Calculating W twiddling factor 
+for n = 1 : 8 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 16 );
+end
+
+% calculate next stage values
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+        % Even pair
+        stage(5,n+k)    = stage(4,n+k) + Wn(k+1)*stage(4,n+k+8);     
+        % Odd par
+        stage(5,n+k+8)  = stage(4,n+k) - Wn(k+1)*stage(4,n+k+8);  
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+         st_real_tmp(4,n+k+8) = ( Wr(k*2+1) * st_real(4,n+k+8) ) - (  Wi(k*2+1) * st_imag(4,n+k+8) );   
+         st_imag_tmp(4,n+k+8) = ( Wi(k*2+1) * st_real(4,n+k+8) ) + (  Wr(k*2+1) * st_imag(4,n+k+8) ); 
+    end
+end
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+        % Even pair
+        st_real(5,n+k)    = st_real(4,n+k) + st_real_tmp(4,n+k+8); 
+        st_imag(5,n+k)    = st_imag(4,n+k) + st_imag_tmp(4,n+k+8);
+        % Odd par
+        st_real(5,n+k+8)  = st_real(4,n+k) - st_real_tmp(4,n+k+8);
+        st_imag(5,n+k+8)  = st_imag(4,n+k) - st_imag_tmp(4,n+k+8);
+    end
+end
+
+%% 5th stage  
+
+% Calculating W twiddling factor 
+for n = 1 : 16 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 32 );
+end
+
+% calculate next stage values
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+        % Even pair
+        stage(6,n+k)    = stage(5,n+k) + Wn(k+1)*stage(5,n+k+16);     
+        % Odd par
+        stage(6,n+k+16)  = stage(5,n+k) - Wn(k+1)*stage(5,n+k+16);  
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+         st_real_tmp(5,n+k+16) = ( Wr(k*1+1) * st_real(5,n+k+16) ) - (  Wi(k*1+1) * st_imag(5,n+k+16) );   
+         st_imag_tmp(5,n+k+16) = ( Wi(k*1+1) * st_real(5,n+k+16) ) + (  Wr(k*1+1) * st_imag(5,n+k+16) );
+    end
+end
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+        % Even pair
+        st_real(6,n+k)    = st_real(5,n+k) + st_real_tmp(5,n+k+16); 
+        st_imag(6,n+k)    = st_imag(5,n+k) + st_imag_tmp(5,n+k+16); 
+        % Odd par
+        st_real(6,n+k+16)  = st_real(5,n+k) - st_real_tmp(5,n+k+16); 
+        st_imag(6,n+k+16)  = st_imag(5,n+k) - st_imag_tmp(5,n+k+16);
+    end
+end
+
+
+
+%% Ploting out
+% slowly plot result
+figure(5)
+for n = 1 : bits +1
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    stem( abs( stage(n,1:fftLength/2) ) );
+%     pause(1);
+end
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+title('FFT using custom function') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(6)
+for n = 1 : bits +1
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    temp = st_real + 1i * st_imag;
+    stem( abs( temp(n,1:fftLength/2) ) );
+%      pause(1);
+end
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+title('FFT using custom function real/imag separate') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(7)
+dif2 = 100* abs(temp(bits +1,1:fftLength/2) - ft(1:fftLength/2))./abs(ft(1:fftLength/2)) ;
+plot(dif2, 'blue')
+title('Difference in calculations') 
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+ylabel('percents, %'), xlabel('kHz') 
+
+##### SOURCE END #####
+--></body></html>
@@ -1,11 +1,11 @@
 %% FFT algoritm
 clear;  % clear all data from memmory
 start_time = 0;
-number_of_samples = 8;
+number_of_samples = 32;
 end_time = number_of_samples - 1;
 n = linspace(start_time, end_time , number_of_samples ); 

-f1 = 1;
+f1 = 2;
 a1 = 0.2;

 f2 = 2;
@@ -66,7 +66,6 @@ stage = zeros(bits,number_of_samples);

 for i=1:number_of_samples
     stage(1,i) =  data((i)); 
-    
 end


@@ -82,41 +81,41 @@ stage(2,6) = stage(1,5) -  stage(1,6);
 stage(2,7) = (stage(1,7) +  stage(1,8)) * exp(-j * 0 * 2 * pi/ 4 );
 stage(2,8) = (stage(1,7) -  stage(1,8)) * exp(-j * 1 * 2 * pi/ 4 );

-% stage(2,9) = stage(1,9) + stage(1,10);
-% stage(2,10) = stage(1,9) -  stage(1,10);
-% 
-% stage(2,11) = (stage(1,11) +  stage(1,12)) * exp(-j * 0 * 2 * pi/ 4 );
-% stage(2,12) = (stage(1,11) -  stage(1,12)) * exp(-j * 1 * 2 * pi/ 4 );
-% 
-% stage(2,13) = stage(1,13) +  stage(1,14);
-% stage(2,14) = stage(1,13) -  stage(1,14);
-% 
-% stage(2,15) = (stage(1,15) +  stage(1,16)) * exp(-j * 0 * 2 * pi/ 4 );
-% stage(2,16) = (stage(1,15) -  stage(1,16)) * exp(-j * 1 * 2 * pi/ 4 );
+stage(2,9) = stage(1,9) + stage(1,10);
+stage(2,10) = stage(1,9) -  stage(1,10);

-% stage(2,17) = stage(1,17) +  stage(1,18);
-% stage(2,18) = stage(1,17) -  stage(1,18)) * exp(-j * 1 * 2 * pi/ 4 );
-% 
-% stage(2,19) = stage(1,19) +  stage(1,20);
-% stage(2,20) = stage(1,19) -  stage(1,20)) * exp(-j * 1 * 2 * pi/ 4 );
-% 
-% stage(2,21) = stage(1,21) +  stage(1,22);
-% stage(2,22) = stage(1,21) -  stage(1,22);
-% 
-% stage(2,23) = stage(1,23) +  stage(1,24);
-% stage(2,24) = stage(1,23) -  stage(1,24);
-% 
-% stage(2,25) = stage(1,25) +  stage(1,26);
-% stage(2,26) = stage(1,25) -  stage(1,26);
-% 
-% stage(2,27) = stage(1,27) +  stage(1,28);
-% stage(2,28) = stage(1,27) -  stage(1,28);
-% 
-% stage(2,29) = stage(1,29) +  stage(1,30);
-% stage(2,30) = stage(1,29) -  stage(1,30);
-% 
-% stage(2,31) = stage(1,31) +  stage(1,32);
-% stage(2,32) = stage(1,31) -  stage(1,32);
+stage(2,11) = (stage(1,11) +  stage(1,12)) * exp(-j * 0 * 2 * pi/ 4 );
+stage(2,12) = (stage(1,11) -  stage(1,12)) * exp(-j * 1 * 2 * pi/ 4 );
+
+stage(2,13) = stage(1,13) +  stage(1,14);
+stage(2,14) = stage(1,13) -  stage(1,14);
+
+stage(2,15) = (stage(1,15) +  stage(1,16)) * exp(-j * 0 * 2 * pi/ 4 );
+stage(2,16) = (stage(1,15) -  stage(1,16)) * exp(-j * 1 * 2 * pi/ 4 );
+
+stage(2,17) = stage(1,17) +  stage(1,18);
+stage(2,18) = (stage(1,17) -  stage(1,18)) * exp(-j * 1 * 2 * pi/ 4 );
+
+stage(2,19) = stage(1,19) +  stage(1,20);
+stage(2,20) = (stage(1,19) -  stage(1,20)) * exp(-j * 1 * 2 * pi/ 4 );
+
+stage(2,21) = stage(1,21) +  stage(1,22);
+stage(2,22) = stage(1,21) -  stage(1,22);
+
+stage(2,23) = stage(1,23) +  stage(1,24);
+stage(2,24) = stage(1,23) -  stage(1,24);
+
+stage(2,25) = stage(1,25) +  stage(1,26);
+stage(2,26) = stage(1,25) -  stage(1,26);
+
+stage(2,27) = stage(1,27) +  stage(1,28);
+stage(2,28) = stage(1,27) -  stage(1,28);
+
+stage(2,29) = stage(1,29) +  stage(1,30);
+stage(2,30) = stage(1,29) -  stage(1,30);
+
+stage(2,31) = stage(1,31) +  stage(1,32);
+stage(2,32) = stage(1,31) -  stage(1,32);


 % stage,
@@ -134,35 +133,35 @@ stage(2,6) = (stage(1,6) +  stage(1,8)) * exp(-j * 1 * 2 * pi/ 8 );
 stage(2,7) = (stage(1,5) -  stage(1,7)) * exp(-j * 2 * 2 * pi/ 8 );
 stage(2,8) = (stage(1,6) -  stage(1,8)) * exp(-j * 3 * 2 * pi/ 8 );

-% stage(2,9) = stage(1,9) +   stage(1,11);
-% stage(2,10) = stage(1,10) + stage(1,12);
-% stage(2,11) = stage(1,9) - stage(1,11);
-% stage(2,12) = stage(1,10) - stage(1,12);
-% 
-% stage(2,13) = (stage(1,13) + stage(1,15)) * exp(-j * 0 * 2 * pi/ 8 );
-% stage(2,14) = (stage(1,14) + stage(1,16)) * exp(-j * 1 * 2 * pi/ 8 );
-% stage(2,15) = (stage(1,13) - stage(1,15)) * exp(-j * 2 * 2 * pi/ 8 );
-% stage(2,16) = (stage(1,14) - stage(1,16)) * exp(-j * 3 * 2 * pi/ 8 );
+stage(2,9) = stage(1,9) +   stage(1,11);
+stage(2,10) = stage(1,10) + stage(1,12);
+stage(2,11) = stage(1,9) - stage(1,11);
+stage(2,12) = stage(1,10) - stage(1,12);

-% stage(2,17) = stage(1,17) + 1 * stage(1,19);
-% stage(2,18) = stage(1,18) + 1 * stage(1,20);
-% stage(2,19) = stage(1,19) - W1(1) * stage(1,17);
-% stage(2,20) = stage(1,20) - W1(2) * stage(1,18);
-% 
-% stage(2,21) = stage(1,21) + 1 * stage(1,23);
-% stage(2,22) = stage(1,22) + 1 * stage(1,24);
-% stage(2,23) = stage(1,23) - W1(1) * stage(1,21);
-% stage(2,24) = stage(1,24) - W1(2) * stage(1,22);
-% 
-% stage(2,25) = stage(1,25) + 1 * stage(1,27);
-% stage(2,26) = stage(1,26) + 1 * stage(1,28);
-% stage(2,27) = stage(1,27) - W1(1) * stage(1,25);
-% stage(2,28) = stage(1,28) - W1(2) * stage(1,26);
-% 
-% stage(2,29) = stage(1,29) + 1 * stage(1,31);
-% stage(2,30) = stage(1,30) + 1 * stage(1,32);
-% stage(2,31) = stage(1,31) - W1(1) * stage(1,29);
-% stage(2,32) = stage(1,32) - W1(2) * stage(1,30);
+stage(2,13) = (stage(1,13) + stage(1,15)) * exp(-j * 0 * 2 * pi/ 8 );
+stage(2,14) = (stage(1,14) + stage(1,16)) * exp(-j * 1 * 2 * pi/ 8 );
+stage(2,15) = (stage(1,13) - stage(1,15)) * exp(-j * 2 * 2 * pi/ 8 );
+stage(2,16) = (stage(1,14) - stage(1,16)) * exp(-j * 3 * 2 * pi/ 8 );
+
+stage(2,17) = stage(1,17) + 1 * stage(1,19);
+stage(2,18) = stage(1,18) + 1 * stage(1,20);
+stage(2,19) = stage(1,19) - W1(1) * stage(1,17);
+stage(2,20) = stage(1,20) - W1(2) * stage(1,18);
+
+stage(2,21) = stage(1,21) + 1 * stage(1,23);
+stage(2,22) = stage(1,22) + 1 * stage(1,24);
+stage(2,23) = stage(1,23) - W1(1) * stage(1,21);
+stage(2,24) = stage(1,24) - W1(2) * stage(1,22);
+
+stage(2,25) = stage(1,25) + 1 * stage(1,27);
+stage(2,26) = stage(1,26) + 1 * stage(1,28);
+stage(2,27) = stage(1,27) - W1(1) * stage(1,25);
+stage(2,28) = stage(1,28) - W1(2) * stage(1,26);
+
+stage(2,29) = stage(1,29) + 1 * stage(1,31);
+stage(2,30) = stage(1,30) + 1 * stage(1,32);
+stage(2,31) = stage(1,31) - W1(1) * stage(1,29);
+stage(2,32) = stage(1,32) - W1(2) * stage(1,30);

 % theard stage 

@@ -176,112 +175,112 @@ stage(3,6) = stage(2,2) -  stage(2,6);
 stage(3,7) = stage(2,3) -  stage(2,7);
 stage(3,8) = stage(2,4) -  stage(2,8);

-% stage(3,9) =  (stage(2,9)  +  stage(2,13)) * exp(-j * 0 * 2 * pi/ 16 );
-% stage(3,10) = (stage(2,10) +  stage(2,14)) * exp(-j * 1 * 2 * pi/ 16 );
-% stage(3,11) = (stage(2,11) +  stage(2,15)) * exp(-j * 2 * 2 * pi/ 16 );
-% stage(3,12) = (stage(2,12) +  stage(2,16)) * exp(-j * 3 * 2 * pi/ 16 );
-% stage(3,13) = (stage(2,9)  -  stage(2,13)) * exp(-j * 4 * 2 * pi/ 16 );
-% stage(3,14) = (stage(2,10) -  stage(2,14)) * exp(-j * 5 * 2 * pi/ 16 );
-% stage(3,15) = (stage(2,11) -  stage(2,15)) * exp(-j * 6 * 2 * pi/ 16 );
-% stage(3,16) = (stage(2,12) -  stage(2,16)) * exp(-j * 7 * 2 * pi/ 16 );
+stage(3,9) =  (stage(2,9)  +  stage(2,13)) * exp(-j * 0 * 2 * pi/ 16 );
+stage(3,10) = (stage(2,10) +  stage(2,14)) * exp(-j * 1 * 2 * pi/ 16 );
+stage(3,11) = (stage(2,11) +  stage(2,15)) * exp(-j * 2 * 2 * pi/ 16 );
+stage(3,12) = (stage(2,12) +  stage(2,16)) * exp(-j * 3 * 2 * pi/ 16 );
+stage(3,13) = (stage(2,9)  -  stage(2,13)) * exp(-j * 4 * 2 * pi/ 16 );
+stage(3,14) = (stage(2,10) -  stage(2,14)) * exp(-j * 5 * 2 * pi/ 16 );
+stage(3,15) = (stage(2,11) -  stage(2,15)) * exp(-j * 6 * 2 * pi/ 16 );
+stage(3,16) = (stage(2,12) -  stage(2,16)) * exp(-j * 7 * 2 * pi/ 16 );



-% stage(3,17) = stage(2,17) + W2(1) * stage(2,21);
-% stage(3,18) = stage(2,18) + W2(2) * stage(2,22);
-% stage(3,19) = stage(2,19) + W2(3) * stage(2,23);
-% stage(3,20) = stage(2,20) + W2(4) * stage(2,24);
-% stage(3,21) = stage(2,21) - W2(1) * stage(2,17);
-% stage(3,22) = stage(2,22) - W2(2) * stage(2,18);
-% stage(3,23) = stage(2,23) - W2(3) * stage(2,19);
-% stage(3,24) = stage(2,24) - W2(4) * stage(2,20);
-% 
-% stage(3,25) = stage(2,25) + W2(1) * stage(2,29);
-% stage(3,26) = stage(2,26) + W2(2) * stage(2,30);
-% stage(3,27) = stage(2,27) + W2(3) * stage(2,31);
-% stage(3,28) = stage(2,28) + W2(4) * stage(2,32);
-% stage(3,29) = stage(2,29) - W2(1) * stage(2,25);
-% stage(3,30) = stage(2,30) - W2(2) * stage(2,26);
-% stage(3,31) = stage(2,31) - W2(3) * stage(2,27);
-% stage(3,32) = stage(2,32) - W2(4) * stage(2,28);
+stage(3,17) = stage(2,17) + W2(1) * stage(2,21);
+stage(3,18) = stage(2,18) + W2(2) * stage(2,22);
+stage(3,19) = stage(2,19) + W2(3) * stage(2,23);
+stage(3,20) = stage(2,20) + W2(4) * stage(2,24);
+stage(3,21) = stage(2,21) - W2(1) * stage(2,17);
+stage(3,22) = stage(2,22) - W2(2) * stage(2,18);
+stage(3,23) = stage(2,23) - W2(3) * stage(2,19);
+stage(3,24) = stage(2,24) - W2(4) * stage(2,20);
+
+stage(3,25) = stage(2,25) + W2(1) * stage(2,29);
+stage(3,26) = stage(2,26) + W2(2) * stage(2,30);
+stage(3,27) = stage(2,27) + W2(3) * stage(2,31);
+stage(3,28) = stage(2,28) + W2(4) * stage(2,32);
+stage(3,29) = stage(2,29) - W2(1) * stage(2,25);
+stage(3,30) = stage(2,30) - W2(2) * stage(2,26);
+stage(3,31) = stage(2,31) - W2(3) * stage(2,27);
+stage(3,32) = stage(2,32) - W2(4) * stage(2,28);


 % Fourt stage

 % 
-% stage(4,1) = stage(3,1) +  stage(3,9);
-% stage(4,2) = stage(3,2) +  stage(3,10);
-% stage(4,3) = stage(3,3) +  stage(3,11);
-% stage(4,4) = stage(3,4) +  stage(3,12);
-% stage(4,5) = stage(3,5) +  stage(3,13);
-% stage(4,6) = stage(3,6) +  stage(3,14);
-% stage(4,7) = stage(3,7) +  stage(3,15);
-% stage(4,8) = stage(3,8) +  stage(3,16);
-% stage(4,9)  = stage(3,1) - stage(3,9);
-% stage(4,10) = stage(3,2) -  stage(3,10);
-% stage(4,11) = stage(3,3) -  stage(3,11);
-% stage(4,12) = stage(3,4) -  stage(3,12);
-% stage(4,13) = stage(3,5) -  stage(3,13);
-% stage(4,14) = stage(3,6) -  stage(3,14);
-% stage(4,15) = stage(3,7) -  stage(3,15);
-% stage(4,16) = stage(3,8) -  stage(3,16);
+stage(4,1) = stage(3,1) +  stage(3,9);
+stage(4,2) = stage(3,2) +  stage(3,10);
+stage(4,3) = stage(3,3) +  stage(3,11);
+stage(4,4) = stage(3,4) +  stage(3,12);
+stage(4,5) = stage(3,5) +  stage(3,13);
+stage(4,6) = stage(3,6) +  stage(3,14);
+stage(4,7) = stage(3,7) +  stage(3,15);
+stage(4,8) = stage(3,8) +  stage(3,16);
+stage(4,9)  = stage(3,1) - stage(3,9);
+stage(4,10) = stage(3,2) -  stage(3,10);
+stage(4,11) = stage(3,3) -  stage(3,11);
+stage(4,12) = stage(3,4) -  stage(3,12);
+stage(4,13) = stage(3,5) -  stage(3,13);
+stage(4,14) = stage(3,6) -  stage(3,14);
+stage(4,15) = stage(3,7) -  stage(3,15);
+stage(4,16) = stage(3,8) -  stage(3,16);

-% stage(4,17) = stage(3,17) + W3(1) * stage(3,25);
-% stage(4,18) = stage(3,18) + W3(2) * stage(3,26);
-% stage(4,19) = stage(3,19) + W3(3) * stage(3,27);
-% stage(4,20) = stage(3,20) + W3(4) * stage(3,28);
-% stage(4,21) = stage(3,21) + W3(5) * stage(3,29);
-% stage(4,22) = stage(3,22) + W3(6) * stage(3,30);
-% stage(4,23) = stage(3,23) + W3(7) * stage(3,31);
-% stage(4,24) = stage(3,24) + W3(8) * stage(3,32);
-% stage(4,25) = stage(3,25) - W3(1) * stage(3,17);
-% stage(4,26) = stage(3,26) - W3(2) * stage(3,18);
-% stage(4,27) = stage(3,27) - W3(3) * stage(3,19);
-% stage(4,28) = stage(3,28) - W3(4) * stage(3,20);
-% stage(4,29) = stage(3,29) - W3(5) * stage(3,21);
-% stage(4,30) = stage(3,30) - W3(6) * stage(3,22);
-% stage(4,31) = stage(3,31) - W3(7) * stage(3,23);
-% stage(4,32) = stage(3,32) - W3(8) * stage(3,24);
+stage(4,17) = stage(3,17) + W3(1) * stage(3,25);
+stage(4,18) = stage(3,18) + W3(2) * stage(3,26);
+stage(4,19) = stage(3,19) + W3(3) * stage(3,27);
+stage(4,20) = stage(3,20) + W3(4) * stage(3,28);
+stage(4,21) = stage(3,21) + W3(5) * stage(3,29);
+stage(4,22) = stage(3,22) + W3(6) * stage(3,30);
+stage(4,23) = stage(3,23) + W3(7) * stage(3,31);
+stage(4,24) = stage(3,24) + W3(8) * stage(3,32);
+stage(4,25) = stage(3,25) - W3(1) * stage(3,17);
+stage(4,26) = stage(3,26) - W3(2) * stage(3,18);
+stage(4,27) = stage(3,27) - W3(3) * stage(3,19);
+stage(4,28) = stage(3,28) - W3(4) * stage(3,20);
+stage(4,29) = stage(3,29) - W3(5) * stage(3,21);
+stage(4,30) = stage(3,30) - W3(6) * stage(3,22);
+stage(4,31) = stage(3,31) - W3(7) * stage(3,23);
+stage(4,32) = stage(3,32) - W3(8) * stage(3,24);

 % Fifth stage

-% W4  = zeros(1,32);    % complex
-% for i = 1 : 32 
-%     W4(i)  = exp(-j * (i-1) * 2 * pi/ 32 );
-% end
-% 
-% stage(5,1) = stage(4,1) + W4(1) * stage(4,17);
-% stage(5,2) = stage(4,2) + W4(2) * stage(4,18);
-% stage(5,3) = stage(4,3) + W4(3) * stage(4,19);
-% stage(5,4) = stage(4,4) + W4(4) * stage(4,20);
-% stage(5,5) = stage(4,5) + W4(5) * stage(4,21);
-% stage(5,6) = stage(4,6) + W4(6) * stage(4,22);
-% stage(5,7) = stage(4,7) + W4(7) * stage(4,23);
-% stage(5,8) = stage(4,8) + W4(8) * stage(4,24);
-% stage(5,9)  = stage(4,9)  + W4(9) * stage(4,25);
-% stage(5,10) = stage(4,10) + W4(10) * stage(4,26);
-% stage(5,11) = stage(4,11) + W4(11) * stage(4,27);
-% stage(5,12) = stage(4,12) + W4(12) * stage(4,28);
-% stage(5,13) = stage(4,13) + W4(13) * stage(4,29);
-% stage(5,14) = stage(4,14) + W4(14) * stage(4,30);
-% stage(5,15) = stage(4,15) + W4(15) * stage(4,31);
-% stage(5,16) = stage(4,16) + W4(16) * stage(4,32);
-% stage(5,17) = stage(4,17) - W4(1) * stage(4,1);
-% stage(5,18) = stage(4,18) - W4(2) * stage(4,2);
-% stage(5,19) = stage(4,19) - W4(3) * stage(4,3);
-% stage(5,20) = stage(4,20) - W4(4) * stage(4,4);
-% stage(5,21) = stage(4,21) - W4(5) * stage(4,5);
-% stage(5,22) = stage(4,22) - W4(6) * stage(4,6);
-% stage(5,23) = stage(4,23) - W4(7) * stage(4,7);
-% stage(5,24) = stage(4,24) - W4(8) * stage(4,8);
-% stage(5,25) = stage(4,25) - W4(9) * stage(4,9);
-% stage(5,26) = stage(4,26) - W4(10) * stage(4,10);
-% stage(5,27) = stage(4,27) - W4(11) * stage(4,11);
-% stage(5,28) = stage(4,28) - W4(12) * stage(4,12);
-% stage(5,29) = stage(4,29) - W4(13) * stage(4,13);
-% stage(5,30) = stage(4,30) - W4(14) * stage(4,14);
-% stage(5,31) = stage(4,31) - W4(15) * stage(4,15);
-% stage(5,32) = stage(4,32) - W4(16) * stage(4,16);
+W4  = zeros(1,32);    % complex
+for i = 1 : 32 
+    W4(i)  = exp(-j * (i-1) * 2 * pi/ 32 );
+end
+
+stage(5,1) = stage(4,1) + W4(1) * stage(4,17);
+stage(5,2) = stage(4,2) + W4(2) * stage(4,18);
+stage(5,3) = stage(4,3) + W4(3) * stage(4,19);
+stage(5,4) = stage(4,4) + W4(4) * stage(4,20);
+stage(5,5) = stage(4,5) + W4(5) * stage(4,21);
+stage(5,6) = stage(4,6) + W4(6) * stage(4,22);
+stage(5,7) = stage(4,7) + W4(7) * stage(4,23);
+stage(5,8) = stage(4,8) + W4(8) * stage(4,24);
+stage(5,9)  = stage(4,9)  + W4(9) * stage(4,25);
+stage(5,10) = stage(4,10) + W4(10) * stage(4,26);
+stage(5,11) = stage(4,11) + W4(11) * stage(4,27);
+stage(5,12) = stage(4,12) + W4(12) * stage(4,28);
+stage(5,13) = stage(4,13) + W4(13) * stage(4,29);
+stage(5,14) = stage(4,14) + W4(14) * stage(4,30);
+stage(5,15) = stage(4,15) + W4(15) * stage(4,31);
+stage(5,16) = stage(4,16) + W4(16) * stage(4,32);
+stage(5,17) = stage(4,17) - W4(1) * stage(4,1);
+stage(5,18) = stage(4,18) - W4(2) * stage(4,2);
+stage(5,19) = stage(4,19) - W4(3) * stage(4,3);
+stage(5,20) = stage(4,20) - W4(4) * stage(4,4);
+stage(5,21) = stage(4,21) - W4(5) * stage(4,5);
+stage(5,22) = stage(4,22) - W4(6) * stage(4,6);
+stage(5,23) = stage(4,23) - W4(7) * stage(4,7);
+stage(5,24) = stage(4,24) - W4(8) * stage(4,8);
+stage(5,25) = stage(4,25) - W4(9) * stage(4,9);
+stage(5,26) = stage(4,26) - W4(10) * stage(4,10);
+stage(5,27) = stage(4,27) - W4(11) * stage(4,11);
+stage(5,28) = stage(4,28) - W4(12) * stage(4,12);
+stage(5,29) = stage(4,29) - W4(13) * stage(4,13);
+stage(5,30) = stage(4,30) - W4(14) * stage(4,14);
+stage(5,31) = stage(4,31) - W4(15) * stage(4,15);
+stage(5,32) = stage(4,32) - W4(16) * stage(4,16);



@@ -0,0 +1,510 @@
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=512;              % windowlength 
+% signal frequencies
+max = 2048 - 1 ;
+
+f1 = 430;
+a1 = 0;
+
+f2 = 8000;
+a2 = 0;
+
+f3 = 8000;
+a3 = max/2;
+
+% calculating signals 
+comp1 = a1 * sin(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * sin(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * sin(2*pi*f3*[0:1/fs:1]);
+
+% calculatin vector values for step function
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+%data = [ d1 , d2];                  % creates vector with step function
+data = comp1 + comp2 + comp3;      % creates vector from 3 sin functions
+
+figure(1)               % plots separete sin functions
+plot ( comp1, '-');
+hold on;
+plot ( comp2, '-');
+plot ( comp3, '-');
+xlim([1 50])
+title('Separete SIN functions') 
+ylabel('magnitude'), xlabel('time') 
+hold off;
+
+figure(2)               % plots signal for fft
+plot ( data);
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+xlim([1 100])
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft =fft(data,fftLength); 
+%ftMag=abs(ft(1:fftLength/2)); 
+ftMag=abs(ft);
+plot (ftMag)
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
+
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round(xt*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+
+figure(4)               % plots resultinf fft(in dB)  from Matlab functions
+ft =fft(data,fftLength); 
+%ftMag=abs(ft(1:fftLength/2));
+ftMag=abs(ft);
+plot (20*log10(ftMag))
+title('dB Magnitude') 
+ylabel('dB'), xlabel('kHz') 
+
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round(xt*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);      % create vektor size of fftlength
+
+for i=1:fftLength
+    bin_num = dec2bin(i-1 , bits);      % converting to binary number
+    rev_bit = [];                       % create empty vector
+    for k=bits:-1:1
+       rev_bit = [rev_bit , bin_num(k)];
+    end
+    rev_bit_dec(i) = bin2dec(rev_bit) + 1; % add 1 to match Matlab numbering   
+end
+
+%  creating array
+ 
+real_n = zeros(bits+1,fftLength);  % create empty array to store values in reverse bit order
+imag_n = zeros(bits+1,fftLength);
+stage = zeros(bits+1,fftLength);
+%sfi_data = sfi(data,16,0);
+for i=1:fftLength
+     real_n(1,i) =  data(rev_bit_dec(i)+1); 
+     stage(1,i)  =  data(rev_bit_dec(i)+1);
+end
+
+
+% %  W_N vector calculation
+% W  = zeros(1,fftLength);    % complex
+% Wr = zeros(1,fftLength);    % real
+% Wi = zeros(1,fftLength);    % imag
+% for i = 1 : fftLength 
+%     W(i)  = exp(-j * (i-1) * 2 * pi/ fftLength );
+%     Wr(i) = sfi(real(W(i)),16,15);
+%     Wi(i) = sfi(imag(W(i)),16,15);
+% end
+%
+% % W(30) = - W(30+256)  
+% % or
+% % W(x) = - W(x + fftLength/2)
+
+%  new W_N vector calculation this time only half
+
+W  = zeros(1,fftLength/2);    % complex
+Wr = zeros(1,fftLength/2);    % real
+Wi = zeros(1,fftLength/2);    % imag
+for i = 1 : fftLength/2 
+    W(i)  = exp(-j * (i-1) * 2 * pi/ fftLength );
+    Wr(i) = real(W(i));%sfi(real(W(i)),16,15);
+    Wi(i) = imag(W(i));%sfi(imag(W(i)),16,15);
+end
+
+
+%% FFT FSM
+
+%% First stage
+
+for i = 1 : 2^1 : fftLength 
+% %     % Even
+% %     stage(2,i)    = stage(1,i) + stage(1,i+1);
+% %     % Odd
+% %     stage(2,i+1)  = stage(1,i) - stage(1,i+1);
+    
+    % Even
+    real_n(2,i)   = real_n(1,i) + real_n(1,i+1);    
+    % Odd
+    real_n(2,i+1) = real_n(1,i) - real_n(1,i+1); 
+end
+
+
+
+%% Second stage
+
+% % % Calculating W twiddling factor 
+% % for i = 1 : 2 
+% %     Wn(i)  = exp(-j * (i-1) * 2 * pi/ 4 );
+% % end
+% % 
+% % % calculate next stage values
+% % for i = 1 : 2^2 : fftLength 
+% %     % Even pair
+% %         stage(3,i+0)   = stage(2,i+0) + Wn(1)*stage(2,i+2); 
+% %         stage(3,i+1)   = stage(2,i+1) + Wn(2)*stage(2,i+3); 
+% %     % Odd par
+% %         stage(3,i+2)   = stage(2,i+0) - Wn(1)*stage(2,i+2); 
+% %         stage(3,i+3)   = stage(2,i+1) - Wn(2)*stage(2,i+3); 
+% % end
+
+% Multiply odd pairs with W twiddling factor
+for i = 1 : 1 : fftLength 
+    i_bin = dec2bin(i-1, bits);     % calculates "i" in binary
+    
+    if i_bin(bits - 1:bits) == '11'      % Odd pair odd number(every fourth)
+        
+        imag_n(2,i) = -real_n(2,i);
+        real_n(2,i) = 0;
+        % c= real_n(2,i) + j * imag_n(2,i),
+    end 
+end
+% calculate next stage values
+for i = 1 : 2^2 : fftLength 
+    % Even pair
+    real_n(3,i+0)   = real_n(2,i+0) + real_n(2,i+2); 
+    real_n(3,i+1)   = real_n(2,i+1) + real_n(2,i+3);
+    imag_n(3,i+0)   = imag_n(2,i+0) + imag_n(2,i+2); 
+    imag_n(3,i+1)   = imag_n(2,i+1) + imag_n(2,i+3);  
+    % Odd par
+    real_n(3,i+2)   = real_n(2,i+0) - real_n(2,i+2);
+    real_n(3,i+3)   = real_n(2,i+1) - real_n(2,i+3);
+    imag_n(3,i+2)   = imag_n(2,i+0) - imag_n(2,i+2);
+    imag_n(3,i+3)   = imag_n(2,i+1) - imag_n(2,i+3);
+end
+
+%% Therd stage
+
+% % % Calculating W twiddling factor 
+% % for i = 1 : 4 
+% %     Wn(i)  = exp(-j * (i-1) * 2 * pi/ 8 );
+% % end
+% % 
+% % % calculate next stage values
+% % for i = 1 : 2^3 : fftLength 
+% %     for k = 0 : 3
+% %         % Even pair
+% %         stage(4,i+k)   = stage(3,i+k) + Wn(k+1)*stage(3,i+k+4);   
+% %         % Odd par
+% %         stage(4,i+k+4) = stage(3,i+k) - Wn(k+1)*stage(3,i+k+4); 
+% %     end
+% % end
+
+% Multiply odd pairs with W twiddling factor
+for i = 1 : 1 : fftLength 
+    i_bin = dec2bin(i-1, bits);     % calculates "i" in binary
+    
+    if i_bin(bits - 2) == '1'       % 
+        if i_bin(bits - 1: bits) == '00' 
+            % real_n(3,i) = real_n(3,i);
+            % imag_n(3,i) = imag_n(3,i);  
+        end
+        if i_bin(bits - 1: bits) == '01' 
+            real_x = real_n(3,i)*Wr(65) - imag_n(3,i)*Wi(65);
+            imag_x = real_n(3,i)*Wi(65) + Wr(65)*imag_n(3,i);
+            real_n(3,i) = real_x;
+            imag_n(3,i) = imag_x;
+        end
+        if i_bin(bits - 1: bits) == '10' 
+            real_x = real_n(3,i)*Wr(129) - imag_n(3,i)*Wi(129);
+            imag_x = real_n(3,i)*Wi(129) + Wr(129)*imag_n(3,i);
+            real_n(3,i) = real_x;
+            imag_n(3,i) = imag_x;
+        end
+        if i_bin(bits - 1: bits) == '11' 
+            real_x = real_n(3,i)*Wr(193) - imag_n(3,i)*Wi(193);
+            imag_x = real_n(3,i)*Wi(193) + Wr(193)*imag_n(3,i); 
+            real_n(3,i) = real_x;
+            imag_n(3,i) = imag_x;
+        end
+    end 
+end
+% calculate next stage values
+for i = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        % Even pair
+        real_n(4,i+k)   = real_n(3,i+k) + real_n(3,i+k+4);  
+        imag_n(4,i+k)   = imag_n(3,i+k) + imag_n(3,i+k+4);   
+        % Odd par
+        real_n(4,i+k+4) = real_n(3,i+k) - real_n(3,i+k+4); 
+        imag_n(4,i+k+4) = imag_n(3,i+k) - imag_n(3,i+k+4); 
+    end
+end
+
+%% 4th stage  
+
+% % % Calculating W twiddling factor 
+% % for i = 1 : 8 
+% %     Wn(i)  = exp(-j * (i-1) * 2 * pi/ 16 );
+% % end
+% % 
+% % % calculate next stage values
+% % for i = 1 : 2^4 : fftLength 
+% %     for k = 0 : 7
+% %         % Even pair
+% %         stage(5,i+k)    = stage(4,i+k) + Wn(k+1)*stage(4,i+k+8);     
+% %         % Odd par
+% %         stage(5,i+k+8)  = stage(4,i+k) - Wn(k+1)*stage(4,i+k+8);  
+% %     end
+% % end
+
+% Multiply odd pairs with W twiddling factor
+for i = 1 : 1 : fftLength 
+    i_bin = dec2bin(i-1, bits);     % calculates "i" in binary
+    
+    if i_bin(bits - 3) == '1'       % 
+    	n = bin2dec(i_bin(bits - 2:bits));  % converting last 3 bits to decimal
+    	real_x = real_n(4,i)*Wr(n*32+1) - imag_n(4,i)*Wi(n*32+1);
+    	imag_x = real_n(4,i)*Wi(n*32+1) + imag_n(4,i)*Wr(n*32+1); 
+        real_n(4,i) = real_x;
+        imag_n(4,i) = imag_x;
+    end 
+end
+
+% calculate next stage values
+for i = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+        %Even pair
+        real_n(5,i+k)   = real_n(4,i+k) + real_n(4,i+k+8);  
+        imag_n(5,i+k)   = imag_n(4,i+k) + imag_n(4,i+k+8);   
+        %Odd par
+        real_n(5,i+k+8) = real_n(4,i+k) - real_n(4,i+k+8); 
+        imag_n(5,i+k+8) = imag_n(4,i+k) - imag_n(4,i+k+8); 
+    end
+end
+
+%% 5th stage 
+
+% % % Calculating W twiddling factor 
+% % for i = 1 : 16 
+% %     Wn(i)  = exp(-j * (i-1) * 2 * pi/ 32 );
+% % end
+% % 
+% % % calculate next stage values
+% % for i = 1 : 2^5 : fftLength 
+% %     for k = 0 : 15
+% %         % Even pair
+% %         stage(6,i+k)     = stage(5,i+k) + Wn(k+1)*stage(5,i+k+16);     
+% %         % Odd par
+% %         stage(6,i+k+16)  = stage(5,i+k) - Wn(k+1)*stage(5,i+k+16);  
+% %     end
+% % end
+
+% Multiply odd pairs with W twiddling factor
+for i = 1 : 1 : fftLength 
+    i_bin = dec2bin(i-1, bits);     % calculates "i" in binary
+    
+    if i_bin(bits - 4) == '1'       % 
+    	n = bin2dec(i_bin(bits - 3:bits));  % converting last 4 bits to decimal
+    	real_x = real_n(5,i)*Wr(n*16+1) - imag_n(5,i)*Wi(n*16+1);
+    	imag_x = real_n(5,i)*Wi(n*16+1) + imag_n(5,i)*Wr(n*16+1);  
+        real_n(5,i) = real_x;
+        imag_n(5,i) = imag_x;
+    end 
+end
+
+% calculate next stage values
+for i = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+        % Even pair
+        real_n(6,i+k)   = real_n(5,i+k) + real_n(5,i+k+16);  
+        imag_n(6,i+k)   = imag_n(5,i+k) + imag_n(5,i+k+16);   
+        % Odd par
+        real_n(6,i+k+16)= real_n(5,i+k) - real_n(5,i+k+16); 
+        imag_n(6,i+k+16)= imag_n(5,i+k) - imag_n(5,i+k+16); 
+    end
+end
+
+%% 6th stage 
+
+% % % Calculating W twiddling factor 
+% % for i = 1 : 32 
+% %     Wn(i)  = exp(-j * (i-1) * 2 * pi/ 64 );
+% % end
+% % 
+% % % calculate next stage values
+% % for i = 1 : 2^6 : fftLength 
+% %     for k = 0 : 31
+% %         % Even pair
+% %         stage(7,i+k)     = stage(6,i+k) + Wn(k+1)*stage(6,i+k+32);     
+% %         % Odd par
+% %         stage(7,i+k+32)  = stage(6,i+k) - Wn(k+1)*stage(6,i+k+32);  
+% %     end
+% % end
+
+% Multiply odd pairs with W twiddling factor
+for i = 1 : 1 : fftLength 
+    i_bin = dec2bin(i-1, bits);     % calculates "i" in binary
+    
+    if i_bin(bits - 5) == '1'       % 
+    	n = bin2dec(i_bin(bits - 4:bits));  % converting last 5 bits to decimal
+    	real_x = real_n(6,i)*Wr(n*8+1) - imag_n(6,i)*Wi(n*8+1);
+    	imag_x = real_n(6,i)*Wi(n*8+1) + imag_n(6,i)*Wr(n*8+1); 
+        real_n(6,i) = real_x;
+        imag_n(6,i) = imag_x;
+    end 
+end
+
+% calculate next stage values
+for i = 1 : 2^6 : fftLength 
+    for k = 0 : 31
+        % Even pair
+        real_n(7,i+k)   = real_n(6,i+k) + real_n(6,i+k+32);  
+        imag_n(7,i+k)   = imag_n(6,i+k) + imag_n(6,i+k+32);   
+        % Odd par
+        real_n(7,i+k+32)= real_n(6,i+k) - real_n(6,i+k+32); 
+        imag_n(7,i+k+32)= imag_n(6,i+k) - imag_n(6,i+k+32); 
+    end
+end
+
+%% 7th stage 
+
+% % % Calculating W twiddling factor 
+% % for i = 1 : 64 
+% %     Wn(i)  = exp(-j * (i-1) * 2 * pi/ 128 );
+% % end
+% % 
+% % % calculate next stage values
+% % for i = 1 : 2^7 : fftLength 
+% %     for k = 0 : 63
+% %         % Even pair
+% %         stage(8,i+k)     = stage(7,i+k) + Wn(k+1)*stage(7,i+k+64);     
+% %         % Odd par
+% %         stage(8,i+k+64)  = stage(7,i+k) - Wn(k+1)*stage(7,i+k+64);  
+% %     end
+% % end
+
+% Multiply odd pairs with W twiddling factor
+for i = 1 : 1 : fftLength 
+    i_bin = dec2bin(i-1, bits);     % calculates "i" in binary
+    
+    if i_bin(bits - 6) == '1'       % 
+    	n = bin2dec(i_bin(bits - 5:bits));  % converting last 6 bits to decimal
+    	real_x = real_n(7,i)*Wr(n*4+1) - imag_n(7,i)*Wi(n*4+1);
+    	imag_x = real_n(7,i)*Wi(n*4+1) + imag_n(7,i)*Wr(n*4+1); 
+        real_n(7,i) = real_x;
+        imag_n(7,i) = imag_x;
+    end 
+end
+
+% calculate next stage values
+for i = 1 : 2^7 : fftLength 
+    for k = 0 : 63
+        % Even pair
+        real_n(8,i+k)   = real_n(7,i+k) + real_n(7,i+k+64);  
+        imag_n(8,i+k)   = imag_n(7,i+k) + imag_n(7,i+k+64);   
+        % Odd par
+        real_n(8,i+k+64)= real_n(7,i+k) - real_n(7,i+k+64); 
+        imag_n(8,i+k+64)= imag_n(7,i+k) - imag_n(7,i+k+64); 
+    end
+end
+
+%% 8th stage 
+
+
+% % % Calculating W twiddling factor 
+% % for i = 1 : 128 
+% %     Wn(i)  = exp(-j * (i-1) * 2 * pi/ 256 );
+% % end
+% % 
+% % % calculate next stage values
+% % for i = 1 : 2^8 : fftLength 
+% %     for k = 0 : 127
+% %         % Even pair
+% %         stage(9,i+k)      = stage(8,i+k) + Wn(k+1)*stage(8,i+k+128);     
+% %         % Odd par
+% %         stage(9,i+k+128)  = stage(8,i+k) - Wn(k+1)*stage(8,i+k+128);  
+% %     end
+% % end
+
+
+% Multiply odd pairs with W twiddling factor
+for i = 1 : 1 : fftLength 
+    i_bin = dec2bin(i-1, bits);     % calculates "i" in binary
+    
+    if i_bin(bits - 7) == '1'       % 
+    	n = bin2dec(i_bin(bits - 6:bits));  % converting last 7 bits to decimal
+    	real_x = real_n(8,i)*Wr(n*2+1) - imag_n(8,i)*Wi(n*2+1);
+    	imag_x = real_n(8,i)*Wi(n*2+1) + imag_n(8,i)*Wr(n*2+1); 
+        real_n(8,i) = real_x;
+        imag_n(8,i) = imag_x;
+    end 
+end
+
+% calculate next stage values
+for i = 1 : 2^8 : fftLength 
+    for k = 0 : 127
+        % Even pair
+        real_n(9,i+k)   = real_n(8,i+k) + real_n(8,i+k+128);  
+        imag_n(9,i+k)   = imag_n(8,i+k) + imag_n(8,i+k+128);   
+        % Odd par
+        real_n(9,i+k+128)= real_n(8,i+k) - real_n(8,i+k+128); 
+        imag_n(9,i+k+128)= imag_n(8,i+k) - imag_n(8,i+k+128); 
+    end
+end
+
+%% 9th stage 
+
+
+% % % Calculating W twiddling factor 
+% % for i = 1 : 256 
+% %     Wn(i)  = exp(-j * (i-1) * 2 * pi/ 512 );
+% % end
+% % 
+% % % calculate next stage values
+% % for i = 1 : 2^9 : fftLength 
+% %     for k = 0 : 255
+% %         % Even pair
+% %         stage(10,i+k)      = stage(9,i+k) + Wn(k+1)*stage(9,i+k+256);     
+% %         % Odd par
+% %         stage(10,i+k+256)  = stage(9,i+k) - Wn(k+1)*stage(9,i+k+256);  
+% %     end
+% % end
+
+% Multiply odd pairs with W twiddling factor
+for i = 1 : 1 : fftLength 
+    i_bin = dec2bin(i-1, bits);     % calculates "i" in binary
+    
+    if i_bin(bits - 8) == '1'       % 
+    	n = bin2dec(i_bin(bits - 7:bits));  % converting last 8 bits to decimal
+    	real_x = real_n(8,i)*Wr(n*1+1) - imag_n(8,i)*Wi(n*1+1);
+    	imag_x = real_n(8,i)*Wi(n*1+1) + imag_n(8,i)*Wr(n*1+1); 
+        real_n(8,i) = real_x;
+        imag_n(8,i) = imag_x;
+    end 
+end
+
+% calculate next stage values
+i = 1;
+    for k = 0 : 255
+        % Even pair
+        real_n(10,i+k)   = real_n(9,i+k) + real_n(9,i+k+255);  
+        imag_n(10,i+k)   = imag_n(9,i+k) + imag_n(9,i+k+255);   
+        % Odd par
+        real_n(10,i+k+255)= real_n(9,i+k) - real_n(9,i+k+255); 
+        imag_n(10,i+k+255)= imag_n(9,i+k) - imag_n(9,i+k+255); 
+    end
+
+
+
+%% Ploting out
+% slowly plot result
+figure(5)
+for i = bits : bits 
+    plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+%     plot( abs( stage(i,:) ) );
+%    pause(1);
+end
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round(xt*fstep)/1000 ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
@@ -0,0 +1,306 @@
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=32;               % windowlength 
+
+% signal frequencies
+data_length = 8;           % data length in FPGA calculations 
+max = 2^(data_length-1) - 1 ;            % max aplitude 2^n  /2 
+
+f1 = 1000;
+a1 = max/2;
+
+f2 = 0;
+a2 = max/4;
+
+f3 = 8000;
+a3 = max/2;
+
+% calculating signals 
+comp1 = a1 * cos(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * cos(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * cos(2*pi*f3*[0:1/fs:1]);
+
+% calculatin vector values for step function
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+%data = [ d1 , d2];                  % creates vector with step function
+data = comp1 + comp2 + comp3;      % creates vector from 3 sin functions
+
+figure(1)               % plots separete sin functions
+plot ( comp1, '-');
+hold on;
+plot ( comp2, '-');
+plot ( comp3, '-');
+xlim([1 50])
+title('Separete SIN functions') 
+ylabel('magnitude'), xlabel('time') 
+hold off;
+
+figure(2)               % plots signal for fft
+plot ( data);
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+xlim([1 100])
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft =fft(data,fftLength); 
+ftMag=abs(ft(1:fftLength/2)); 
+stem (ftMag)
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
+
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+
+% figure(4)               % plots resultinf fft(in dB)  from Matlab functions
+% ft =fft(data,fftLength); 
+% ftMag=abs(ft(1:fftLength/2)); 
+% plot (20*log10(ftMag))
+% title('dB Magnitude') 
+% ylabel('dB'), xlabel('kHz') 
+% 
+% xt = xticks;        % returns the current x-axis tick values as a vector
+% fstep = fs/fftLength;       % tick of f axis in f domain 
+% xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+% xticklabels(xtnew)      % set new tick labels
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);           % create vektor size of fftlength
+
+for n=1:fftLength
+    bin_num = dec2bin(n-1 , bits);          % converting to binary number
+    rev_bit = [];                           % create empty vector
+    for k=bits:-1:1
+       rev_bit = [rev_bit , bin_num(k)];
+    end
+    rev_bit_dec(n) = bin2dec(rev_bit) ;     % add 1 to match Matlab numbering   
+end
+
+%  creating array
+%  create empty array to store values in reverse bit order
+stage = zeros(bits + 1,fftLength);
+
+for n=1:fftLength
+     stage(1,n)  =  data(rev_bit_dec(n)+1);
+end
+
+% Calculating W twiddling factor for all stages 
+for n = 1 : fftLength/2 
+    W(n)  = exp(-1i * (n-1) * 2 * pi/ fftLength );
+end
+
+% convert to fixed point mumber -> sfi(v,w,f) returns a signed fixed-point object with value v, word length w, and fraction length f.
+Wr = sfi(real(W),data_length,data_length-2);       
+Wi = sfi(imag(W),data_length,data_length-2);
+
+st_real = sfi(real(stage) , data_length + 3 , 0);
+st_imag = sfi(imag(stage) , data_length + 3 , 0);
+% temp values for multiplaying with W twiddling factor
+st_real_tmp = sfi(real(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+st_imag_tmp = sfi(imag(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+
+%% First stage
+
+for n = 1 : 2^1 : fftLength 
+    % Even
+    stage(2,n)    = stage(1,n) + stage(1,n+1);
+    % Odd
+    stage(2,n+1)  = stage(1,n) - stage(1,n+1);
+end
+
+% calculations using separate real and imaginary numbers 
+for n = 1 : 2^1 : fftLength 
+    % Even
+    st_real(2,n)    = st_real(1,n) + st_real(1,n+1);
+    % imag is 0
+    % Odd
+    st_real(2,n+1)  = st_real(1,n) - st_real(1,n+1);
+    % imag is 0
+end
+
+%% Second stage
+
+% Calculating W twiddling factor 
+for n = 1 : 2 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 4 );
+end
+
+% calculate next stage values
+for n = 1 : 2^2 : fftLength 
+    % Even pair
+        stage(3,n+0)   = stage(2,n+0) + Wn(1)*stage(2,n+2); 
+        stage(3,n+1)   = stage(2,n+1) + Wn(2)*stage(2,n+3); 
+    % Odd par
+        stage(3,n+2)   = stage(2,n+0) - Wn(1)*stage(2,n+2); 
+        stage(3,n+3)   = stage(2,n+1) - Wn(2)*stage(2,n+3); 
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^2 : fftLength 
+    % Even pair
+        st_real(3,n+0)   = st_real(2,n+0) + st_real(2,n+2); 
+        % imag is 0
+        st_real(3,n+1)   = st_real(2,n+1) ;         % real is 0
+        st_imag(3,n+1)   = -1 * st_real(2,n+3);     % mult -j
+    % Odd par
+        st_real(3,n+2)   = st_real(2,n+0) - st_real(2,n+2); 
+        % imag is 0
+        st_real(3,n+3)   = st_real(2,n+1) ;         % real is 0
+        st_imag(3,n+3)   = st_real(2,n+3);          % mult -j
+end
+
+
+%% Therd stage
+
+% Calculating W twiddling factor 
+for n = 1 : 4 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 8 );
+end
+
+% calculate next stage values
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        % Even pair
+        stage(4,n+k)   = stage(3,n+k) + Wn(k+1)*stage(3,n+k+4);   
+        % Odd par
+        stage(4,n+k+4) = stage(3,n+k) - Wn(k+1)*stage(3,n+k+4); 
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        st_real_tmp(3,n+k+4) = ( Wr(k*4+1) * st_real(3,n+k+4) ) - (  Wi(k*4+1) * st_imag(3,n+k+4) );   
+        st_imag_tmp(3,n+k+4) = ( Wi(k*4+1) * st_real(3,n+k+4) ) + (  Wr(k*4+1) * st_imag(3,n+k+4) ); 
+    end
+end
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        % Even pair
+        st_real(4,n+k)   = st_real(3,n+k) + st_real_tmp(3,n+k+4);  
+        st_imag(4,n+k)   = st_imag(3,n+k) + st_imag_tmp(3,n+k+4);
+        % Odd par
+        st_real(4,n+k+4) = st_real(3,n+k) - st_real_tmp(3,n+k+4); 
+        st_imag(4,n+k+4) = st_imag(3,n+k) - st_imag_tmp(3,n+k+4); 
+    end
+end
+
+
+%% 4th stage  
+
+% Calculating W twiddling factor 
+for n = 1 : 8 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 16 );
+end
+
+% calculate next stage values
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+        % Even pair
+        stage(5,n+k)    = stage(4,n+k) + Wn(k+1)*stage(4,n+k+8);     
+        % Odd par
+        stage(5,n+k+8)  = stage(4,n+k) - Wn(k+1)*stage(4,n+k+8);  
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+         st_real_tmp(4,n+k+8) = ( Wr(k*2+1) * st_real(4,n+k+8) ) - (  Wi(k*2+1) * st_imag(4,n+k+8) );   
+         st_imag_tmp(4,n+k+8) = ( Wi(k*2+1) * st_real(4,n+k+8) ) + (  Wr(k*2+1) * st_imag(4,n+k+8) ); 
+    end
+end
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+        % Even pair
+        st_real(5,n+k)    = st_real(4,n+k) + st_real_tmp(4,n+k+8); 
+        st_imag(5,n+k)    = st_imag(4,n+k) + st_imag_tmp(4,n+k+8);
+        % Odd par
+        st_real(5,n+k+8)  = st_real(4,n+k) - st_real_tmp(4,n+k+8);
+        st_imag(5,n+k+8)  = st_imag(4,n+k) - st_imag_tmp(4,n+k+8);
+    end
+end
+
+%% 5th stage  
+
+% Calculating W twiddling factor 
+for n = 1 : 16 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 32 );
+end
+
+% calculate next stage values
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+        % Even pair
+        stage(6,n+k)    = stage(5,n+k) + Wn(k+1)*stage(5,n+k+16);     
+        % Odd par
+        stage(6,n+k+16)  = stage(5,n+k) - Wn(k+1)*stage(5,n+k+16);  
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+         st_real_tmp(5,n+k+16) = ( Wr(k*1+1) * st_real(5,n+k+16) ) - (  Wi(k*1+1) * st_imag(5,n+k+16) );   
+         st_imag_tmp(5,n+k+16) = ( Wi(k*1+1) * st_real(5,n+k+16) ) + (  Wr(k*1+1) * st_imag(5,n+k+16) );
+    end
+end
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+        % Even pair
+        st_real(6,n+k)    = st_real(5,n+k) + st_real_tmp(5,n+k+16); 
+        st_imag(6,n+k)    = st_imag(5,n+k) + st_imag_tmp(5,n+k+16); 
+        % Odd par
+        st_real(6,n+k+16)  = st_real(5,n+k) - st_real_tmp(5,n+k+16); 
+        st_imag(6,n+k+16)  = st_imag(5,n+k) - st_imag_tmp(5,n+k+16);
+    end
+end
+
+
+
+%% Ploting out
+% slowly plot result
+figure(5)
+for n = 1 : bits +1
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    stem( abs( stage(n,1:fftLength/2) ) );
+%     pause(1);
+end
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+title('FFT using custom function') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(6)
+for n = 1 : bits +1
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    temp = st_real + 1i * st_imag;
+    stem( abs( temp(n,1:fftLength/2) ) );
+%      pause(1);
+end
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+title('FFT using custom function real/imag separate') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(7)
+dif2 = 100* abs(temp(bits +1,1:fftLength/2) - ft(1:fftLength/2))./abs(ft(1:fftLength/2)) ;
+plot(dif2, 'blue')
+title('Difference in calculations') 
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+ylabel('percents, %'), xlabel('kHz') 
@@ -0,0 +1,119 @@
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=512;              % windowlength 
+stage_num = log2(fftLength);
+% signal frequencies
+max = 2048 - 1 ;
+
+f1 = 430;
+a1 = 0;
+
+f2 = 4300;
+a2 = 0;
+
+f3 = 8000;
+a3 = max/2;
+
+% calculating signals 
+comp1 = a1 * sin(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * sin(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * sin(2*pi*f3*[0:1/fs:1]);
+Length = length(comp3);
+% calculatin vector values for step function
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+%data = [ d1 , d2];                  % creates vector with step function
+data = comp1 + comp2 + comp3;      % creates vector from 3 sin functions
+%data = comp3;
+
+% Grafika nobiides
+bin_vals = [0 : fftLength-1];
+N_2 = ceil(fftLength/2);
+fax_kHz = (bin_vals-N_2)*fs/fftLength/1000;
+
+freq3 = ceil(-(fftLength)/2:1:(fftLength)/2).*(fs/fftLength)/1000;
+
+figure(1)               % plots separete sin functions
+hold off,
+%plot ( comp1, '-');
+hold on;
+%plot ( comp2, '-');
+plot ( comp3, '-'), grid minor,;
+%xlim([1 50])
+title('Separete SIN functions') 
+ylabel('magnitude'), xlabel('time') 
+hold off;
+
+figure(2)               % plots signal for fft
+plot ( data), grid minor,;
+xlim([1 50])
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+%xlim([1 100])
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft =fft(data,fftLength); 
+ft1 = fftshift(ft);
+ftMag = abs(ft1); 
+plot (fax_kHz,ftMag), grid minor,
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(4)               % plots resultinf fft(in dB)  from Matlab functions
+ft = fft(data,fftLength+1); 
+ftMag = abs(ft(1:fftLength+1)); 
+plot (freq3,20*log10(ftMag)), grid minor,
+title('dB Magnitude') 
+ylabel('dB'), xlabel('kHz') 
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);           % create vektor size of fftlength
+
+stage = 1;              %Do it here for stage #1 
+c = 0:fftLength-1;
+c_bin = de2bi(c);       % create binary table
+rev_bit_dec = bi2de(fliplr(circshift(c_bin',stage-1)'));    %Rotate binary table and convert to dec
+
+%  creating array
+%  create empty array to store values in reverse bit order
+stage = zeros(bits + 1,fftLength);
+
+%% New stages
+
+for st = 0 : stage_num;
+    if st == 0
+       for tmp=1:fftLength;
+            stage(st+1,tmp)  =  data(rev_bit_dec(tmp)+1);
+       end
+    else st > 0;
+        for n = 1 : fftLength/2;
+                Wn(n)  = exp(-j * (n-1) * 2 * pi/ 2^(st) );
+        end
+        for i = 1 : 2^st : fftLength;
+                for k = 0 : 2^(st-1)-1;
+                    % Even
+                        stage(st+1,i+k) = stage(st,i+k) + Wn(k+1)*stage(st,i+k+2^(st-1));
+                    % Odd
+                        stage(st+1,i+k+2^(st-1)) = stage(st,i+k) - Wn(k+1)*stage(st,i+k+2^(st-1));
+                end
+        end
+    end
+end
+
+%% Ploting out
+% slowly plot result
+figure(5)
+for i = 1 : bits + 1;
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+        plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ), grid minor,;
+    pause(1);
+end
+
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
@@ -0,0 +1,144 @@
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=512;              % windowlength 
+stage_num = log2(fftLength);
+% signal frequencies
+max = 2048 - 1 ;
+
+f1 = 430;
+a1 = 0;
+
+f2 = 4300;
+a2 = 0;
+
+f3 = 8000;
+a3 = max/2;
+
+% calculating signals 
+comp1 = a1 * sin(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * sin(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * sin(2*pi*f3*[0:1/fs:1]);
+Length = length(comp3);
+% calculatin vector values for step function
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+%data = [ d1 , d2];                  % creates vector with step function
+data = comp1 + comp2 + comp3;      % creates vector from 3 sin functions
+%data = comp3;
+
+% Grafika nobiides
+bin_vals = [0 : fftLength-1];
+N_2 = ceil(fftLength/2);
+fax_kHz = (bin_vals-N_2)*fs/fftLength/1000;
+
+freq3 = ceil(-(fftLength)/2:1:(fftLength)/2).*(fs/fftLength)/1000;
+
+figure(1)               % plots separete sin functions
+hold off,
+%plot ( comp1, '-');
+hold on;
+%plot ( comp2, '-');
+plot ( comp3, '-'), grid minor,;
+%xlim([1 50])
+title('Separete SIN functions') 
+ylabel('magnitude'), xlabel('time') 
+hold off;
+
+figure(2)               % plots signal for fft
+plot ( data), grid minor,;
+xlim([1 50])
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+%xlim([1 100])
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft =fft(data,fftLength); 
+ft1 = fftshift(ft);
+ftMag = abs(ft1); 
+plot (fax_kHz,ftMag), grid minor,
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(4)               % plots resultinf fft(in dB)  from Matlab functions
+ft = fft(data,fftLength+1); 
+ftMag = abs(ft(1:fftLength+1)); 
+plot (freq3,20*log10(ftMag)), grid minor,
+title('dB Magnitude') 
+ylabel('dB'), xlabel('kHz') 
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);           % create vektor size of fftlength
+
+stage = 1;              %Do it here for stage #1 
+c = 0:fftLength-1;
+c_bin = de2bi(c);       % create binary table
+rev_bit_dec = bi2de(fliplr(circshift(c_bin',stage-1)'));    %Rotate binary table and convert to dec
+
+%  creating array
+%  create empty array to store values in reverse bit order
+stage = zeros(bits+1,fftLength);
+real_n = zeros(bits+1,fftLength);
+imag_n = zeros(bits+1,fftLength);
+
+Wn = zeros(1,fftLength/2);   % complex
+Wr = zeros(1,fftLength/2);    % real
+Wi = zeros(1,fftLength/2);    % imag
+
+%% New stages
+
+for st = 0 : stage_num;
+    if st == 0
+       for tmp=1:fftLength;
+            stage(st+1,tmp)  =  data(rev_bit_dec(tmp)+1);
+            real_n(st+1,tmp)  =  data(rev_bit_dec(tmp)+1);
+       end
+    else st > 0;
+        for n = 1 : fftLength/2;
+                Wn(n)  = exp(-j * (n-1) * 2 * pi/ 2^(st) );
+                Wr(n) = real(Wn(n));
+                Wi(n) = imag(Wn(n));
+        end
+        for i = 1 : 2^st : fftLength;
+                for k = 0 : 2^(st-1)-1;
+                    % Even
+                        stage(st+1,i+k) = stage(st,i+k) + Wn(k+1)*stage(st,i+k+2^(st-1));
+                        real_n(st+1,i+k) = real_n(st,i+k) + Wn(k+1)*real_n(st,i+k+2^(st-1));
+                        imag_n(st+1,i+k) = imag_n(st,i+k) + Wn(k+1)*imag_n(st,i+k+2^(st-1));
+                    % Odd
+                        stage(st+1,i+k+2^(st-1)) = stage(st,i+k) - Wn(k+1)*stage(st,i+k+2^(st-1));
+                        real_n(st+1,i+k+2^(st-1)) = real_n(st,i+k) - Wn(k+1)*real_n(st,i+k+2^(st-1));
+                        imag_n(st+1,i+k+2^(st-1)) = imag_n(st,i+k) - Wn(k+1)*imag_n(st,i+k+2^(st-1));
+                end
+        end
+    end
+end
+
+%% Ploting out
+% slowly plot result
+figure(5)
+for i = 1 : bits + 1;
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    %plot( fax_kHz, abs( fftshift( real_n(i, :) + j.*imag_n(i,:) ) ) ), grid minor,;
+    plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ), grid minor,;
+    %pause(1);
+end
+
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz')
+
+figure(6)
+for i = 1 : bits + 1;
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    plot( fax_kHz, abs( fftshift( real_n(i, :) + j.*imag_n(i,:) ) ) ), grid minor,;
+    %plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ), grid minor,;
+    %pause(1);
+end
+
+title('Linear Magnitude FFT, ploted from Real + Imag') 
+ylabel('magnitude'), xlabel('kHz') 
@@ -0,0 +1,163 @@
+%% If need working only with Real and Imginary parts Comment lines started 
+% with "Stage" in "New Stages" part and on the bottom whole figure(5)
+
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=256;              % windowlength 
+stage_num = log2(fftLength);
+
+while 1                     % Checking for correct "fftLength"-Wondow length value
+if ~mod(stage_num,1)==0
+    error('"fftLength"-Wondow length value must be a numer: 2^x= : 2, 4, 8, 16, 32,...');
+    break
+else
+                            % continue working if value is correct
+% signal frequencies
+max = 2048 - 1 ;
+
+f1 = 430;
+a1 = 0;
+
+f2 = 4300;
+a2 = 0;
+
+f3 = 8000;
+a3 = max/2;
+
+% calculating signals 
+comp1 = a1 * sin(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * sin(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * sin(2*pi*f3*[0:1/fs:1]);
+Length = length(comp3);
+
+data = comp1 + comp2 + comp3;      % creates vector from 3 sin functions
+%data = comp3;
+
+% Plot shifting to center
+bin_vals = [0 : fftLength-1];
+N_2 = ceil(fftLength/2);
+fax_kHz = (bin_vals-N_2)*fs/fftLength/1000;
+
+freq3 = ceil(-(fftLength)/2:1:(fftLength)/2).*(fs/fftLength)/1000;
+
+figure(1)               % plots separete sin functions
+hold off,
+%plot ( comp1, '-');
+hold on;
+%plot ( comp2, '-');
+plot (comp3, '-')
+xlim([1 50]), grid minor,;
+title('Separete SIN functions') 
+ylabel('magnitude'), xlabel('time') 
+hold off;
+
+figure(2)               % plots signal for fft
+plot (data), grid minor,;
+xlim([1 50])
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft = fft(data,fftLength); 
+ft1 = fftshift(ft);
+ftMag = abs(ft1); 
+plot (fax_kHz,ftMag), grid minor,
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(4)               % plots resultinf fft(in dB) from Matlab functions
+ft = fft(data,fftLength); 
+ft1 = fftshift(ft);
+ftMag = abs(ft1(1:fftLength)); 
+plot (fax_kHz,20*log10(ftMag)), grid minor,
+title('dB Magnitude') 
+ylabel('dB'), xlabel('kHz') 
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);           % create vektor size of fftlength
+
+stage = 1;              %Do it here for stage #1 
+c = 0:fftLength-1;
+c_bin = de2bi(c);       % create binary table
+rev_bit_dec = bi2de(fliplr(circshift(c_bin',stage-1)'));    %Rotate binary table and convert to dec
+
+%  creating matrix arrays
+%  create empty matrix arrays to store values in reverse bit order
+stage = zeros(bits+1,fftLength);
+real_n = zeros(bits+1,fftLength);
+imag_n = zeros(bits+1,fftLength);
+
+real_n_sfi = zeros(bits+1,fftLength);
+imag_n_sfi = zeros(bits+1,fftLength);
+
+%% Starting stages
+
+for st = 0 : stage_num;
+    if st == 0
+       for tmp=1:fftLength;
+            stage(st+1,tmp)  =  data(rev_bit_dec(tmp)+1);
+            real_n(st+1,tmp)  =  data(rev_bit_dec(tmp)+1);
+       end
+    else st > 0;
+        for n = 1 : fftLength/2;
+                Wn(n)  = exp(-j * (n-1) * 2 * pi/ 2^(st) );
+                Wr(n) = real(Wn(n));
+                Wi(n) = imag(Wn(n));
+        end
+        for i = 1 : 2^st : fftLength;
+                for k = 0 : 2^(st-1)-1;
+                    % Even
+                        stage(st+1,i+k) = stage(st,i+k) + Wn(k+1)*stage(st,i+k+2^(st-1));
+                        real_n(st+1,i+k) = real_n(st,i+k) + Wr(k+1)*real_n(st,i+k+2^(st-1)) - Wi(k+1)*imag_n(st,i+k+2^(st-1));
+                        imag_n(st+1,i+k) = imag_n(st,i+k) + Wi(k+1)*real_n(st,i+k+2^(st-1)) + + Wr(k+1)*imag_n(st,i+k+2^(st-1));
+                    % Odd
+                        stage(st+1,i+k+2^(st-1)) = stage(st,i+k) - Wn(k+1)*stage(st,i+k+2^(st-1));
+                        real_n(st+1,i+k+2^(st-1)) = real_n(st,i+k) - Wr(k+1)*real_n(st,i+k+2^(st-1)) +  Wi(k+1)*imag_n(st,i+k+2^(st-1));
+                        imag_n(st+1,i+k+2^(st-1)) = imag_n(st,i+k) - Wi(k+1)*real_n(st,i+k+2^(st-1)) - Wr(k+1)*imag_n(st,i+k+2^(st-1));
+                end
+        end
+    end
+end
+
+%% Constructing signed fixed-point numeric objects
+
+ for n = 1 : fftLength/2;
+     Wr_sfi(n) = sfi(real(Wn(n)),16);
+     Wi_sfi(n) = sfi(imag(Wn(n)),16);
+ end
+
+  for n = 1 : fftLength;
+      for k = 1 : st + 1
+        real_n_sfi(k,n) = sfi(real_n(k,n),24);
+        imag_n_sfi(k,n) = sfi(imag_n(k,n),24);
+      end
+  end
+ 
+%% Plotting out
+
+% for slowly result plotting uncomment pause
+
+figure(5)
+for i = 1 : bits + 1;
+    %plot( fax_kHz, abs( fftshift( real_n(i, :) + j.*imag_n(i,:) ) ) ),
+    plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ),
+    grid minor, title('Linear Magnitude FFT'), ylabel('magnitude'), xlabel('kHz');
+    %pause(1);
+end
+
+figure(6)
+for i = 1 : bits + 1;
+    plot( fax_kHz, abs( fftshift( real_n(i, :) + j.*imag_n(i,:) ) ) ),
+    grid minor, title('Linear Magnitude FFT, ploted from Real + Imag'), ylabel('magnitude'), xlabel('kHz');
+    %plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ), grid minor,;
+    %pause(1);
+end
+
+break
+end
+end
@@ -1,16 +1,28 @@
-f = 4000; 
-fs = 22050; 
-fftLength=1024;             %windowlength 
-x =sin(2*pi*f*[0:1/fs:1]);  %makethesinewave 
-ft =fft(x,fftLength);       %doFFT,userect.window 
-ftMag=abs(ft);              %computemagnitude 
+f = 4300; 
+fs =  44100; 
+fftLength=512;             % windowlength 
+x =sin(2*pi*1000*[0:1/fs:1]) + sin(2*pi*f*[0:1/fs:1])  +  sin(2*pi*20000*[0:1/fs:1]);  % makethesinewave 
+ft =fft(x,fftLength);       % doFFT,userect.window 
+ftMag=abs(ft(1:fftLength/2));          % computemagnitude ( half )

 % plot the results both in linear and dB magnitudes 

 subplot(2, 1, 1), plot(ftMag) 
 title('Linear Magnitude') 
-ylabel('magnitude'), xlabel('bins') 
+ylabel('magnitude'), xlabel('kHz') 

+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round(xt*fstep)/1000 ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+ 
 subplot(2, 1, 2), plot(20*log10(ftMag)) 
 title('dB Magnitude') 
-ylabel('dB'), xlabel('bins')
+ylabel('dB'), xlabel('kHz')
+
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = (fs/fftLength);       % tick of f axis in f domain 
+xtnew = round(xt*fstep)/1000;   % calculate new tick in kHz
+xticklabels(xtnew)        % set new tick labels
+
+    
@@ -0,0 +1,86 @@
+module no_effect #( parameter
+    data_width = 16          // data width 
+)(
+    input                                   clk,
+    input                                   reset,
+    input   signed      [data_width-1: 0]   i_data,
+    output  signed      [data_width-1: 0]   o_data,
+    input                                   i_read_done,
+    output                                  o_read_enable,
+    output                                  o_data_valid,
+    input                                   i_data_ready
+);
+
+//-------------Internal Constants---------------------------
+localparam [1:0]        IDLE         = 'd0,
+                        OUTPUT       = 'd1,
+                        CLEAR        = 'd3;
+
+reg [1:0] r_state=IDLE, r_next=IDLE;
+
+reg   signed      [data_width-1: 0]     r_data = 'b0;
+reg                                     r_read_enable = 0;
+reg                                     r_data_valid = 0;
+
+assign  o_read_enable   = r_read_enable;
+assign  o_data_valid    = r_data_valid;
+assign  o_data          = r_data;
+
+
+//---------state register sequential always block-----------
+always @(posedge clk ) begin
+    if (~reset) begin
+        r_state <= r_next;
+    end 
+end
+
+//----next state & outputs, combinational always block------
+
+always @(posedge clk ) begin
+    if (reset) begin
+        r_next <= IDLE;
+        r_read_enable <= 0;     // redy to read data
+        r_data_valid <= 0;
+    end   
+    else begin  
+    case(r_state)
+        IDLE    :   begin
+                        if (i_data_ready == 1) begin
+                            r_next <= OUTPUT;
+                            r_data <= i_data;
+                            r_read_enable <= 0;
+                            r_data_valid <= 0;
+                        end
+                        else begin
+                            r_next <= IDLE;
+                            r_read_enable <= 1;     // redy to read data
+                            r_data_valid <= 0;
+                        end                     
+                    end
+        OUTPUT  :   begin
+                        if (i_read_done == 1) begin
+                            r_next <= CLEAR;
+                            r_data_valid <= 0;
+                            r_read_enable <= 0;
+                        end
+                        else begin
+                            r_next <= OUTPUT;
+                            r_data_valid <= 1;
+                            r_read_enable <= 0;     // read disable
+                        end
+                    end
+        CLEAR   :   begin
+                        r_next <= IDLE;
+                        r_data_valid  <= 0;
+                        r_read_enable <= 1;
+                    end
+        default:    begin
+                        r_next <= IDLE;          // on error
+                    end
+    endcase 
+    end
+end
+
+
+
+endmodule
@@ -0,0 +1,119 @@
+// Fifo code source:
+// https://vlsicoding.blogspot.com/2013/11/verilog-code-for-synchronous-fifo.html
+// 
+module sync_fifo #( parameter
+//---------------parametre declaration
+   data_width       = 4,
+   address_width    = 4,
+   ram_depth        = 16         // must be 2^n
+)(
+//--------------input output port declaration
+   output reg signed [data_width-1:0]  data_out,
+   output                        full,
+   output                        empty,
+   output  [address_width-1:0]     data_fill,
+   input signed  [data_width-1:0]  data_in,
+   input                         w_clk,      // write clock
+   input                         r_clk,      // read clock
+   input                         reset,
+   input                         wr_en,
+   input                         rd_en);
+ 
+
+//--------------internal register declaration
+reg      [address_width-1:0]     wr_pointer = 0;
+reg      [address_width-1:0]     rd_pointer = 0;
+// reg      [address_width :0]      status_count = 0;
+wire  signed   [data_width-1:0]        data_ram ;
+
+// reg addition = 0;
+// reg subtractor = 0; 
+
+// always@(posedge addition )
+// begin
+//    if (addition ^ subtractor)    // if XOR
+//    begin  
+//       if (status_count != 0) 
+//                status_count = status_count + 1;  
+//    end
+//    addition = 0;        // reset addition 
+// end
+
+// always@(posedge subtractor)
+// begin
+//    if (addition ^ subtractor)    // if XOR
+//    begin
+//       if (status_count != 0) 
+//                status_count = status_count - 1;  
+//    end 
+//    subtractor = 0;      // reset subtractor
+// end
+ 
+//--------------wr_pointer pointing to write address
+   always @ (posedge w_clk,posedge reset)
+   begin
+      if(reset)
+         wr_pointer = 0;
+      else if(wr_en)
+         wr_pointer = wr_pointer+1;
+         //addition = 1;
+   end
+//-------------rd_pointer points to read address
+   always @ (posedge r_clk,posedge reset)
+   begin
+      if(reset)
+         rd_pointer = 0;
+      else if(rd_en)
+         rd_pointer = rd_pointer + 1;
+         //subtractor = 1;
+   end
+//-------------read from FIFO
+   always @ (posedge r_clk,posedge reset)
+   begin
+      if(reset)
+         data_out=0;
+      else if(rd_en)
+         data_out=data_ram;
+   end
+
+// //--------------Status pointer for full and empty checking
+//    always @ (posedge w_clk,posedge r_clk,posedge reset)
+//    begin
+//       if(reset)
+//          status_count = 0;
+//       else if(wr_en && !rd_en && (status_count != ram_depth))
+//          status_count = status_count + 1;
+//       else if(rd_en && !wr_en && (status_count != 0))
+//          status_count = status_count - 1;
+//    end // always @ (posedge clk,posedge reset)
+
+
+// assign full = (status_count == (ram_depth));
+// assign empty = (status_count == 0);
+// assign data_fill = status_count;       // how full are FIFO
+
+assign full = (wr_pointer - rd_pointer  == ram_depth) ? 1'b1 : 1'b0 ;
+assign empty = (wr_pointer - rd_pointer == 0) ? 1'b1 : 1'b0 ;
+assign data_fill = wr_pointer - rd_pointer ;       // how full are FIFO
+ 
+rams_tdp_rf_rf #( 
+   .DEPTH(ram_depth),
+   .ADDR_WIDTH(address_width),
+   .DATA_WIDTH(data_width)
+) memory1 (
+   .addra(wr_pointer),
+   .addrb(rd_pointer),
+   .dia(data_in),
+   .dib(),
+   .doa(),
+   .dob(data_ram),
+   .wea(wr_en),
+   .web(1'b0),
+   .ena(1'b1),
+   .enb(rd_en),
+   .clka(w_clk),
+   .clkb(r_clk)
+);
+
+endmodule // sync_fifo
+
@@ -1,15 +1,19 @@
 //      TOP module 
 //       
-
-
-
+//
+//
+//
 module top #( parameter
    sclk_ws_ratio = 64,         // number of sclk periods per word select period
    mclk_sclk_ratio = 4,        // number of mclk periods per sclk period
-    d_width = 24                // data width
+    d_width = 24,               // data width for I2S
+    memory_d_width = 16         // data width for memory (and effects). lower bits are ignored
 )(
    input           clk,
    input           btnC,
+    output  [15:0]  led, 
+    // input   [1:0]   sw,         // swiches on board to control effects
+    input   [15:0]   sw,         // swiches on board to control effects
    output          da_mclk,
    output          ad_mclk,
    output          da_sclk,
@@ -21,113 +25,159 @@ module top #( parameter
    output  [7: 0]  JXADC       // output for logic analizer
    );

-//------internal wires and registers--------
-wire master_clk;            // 11.29 MHz master clock
-wire serial_clk_sender;
-wire word_select_sender;
-wire serial_clk_receicer;
-wire word_select_receicer;
-wire reset_n;
-wire [d_width-1: 0] r_data_tx;
-wire [d_width-1: 0] l_data_tx;
-wire [d_width-1: 0] r_data_rx;
-wire [d_width-1: 0] l_data_rx;
-
-wire w_sd_tx;               //internal wire
-
-//-----sub modules--------------------------
-// connecting signals to JXADC PMOD to monitor them with signal analyzer
-JXADC_controler JXADC_controler(
-    .ch0(master_clk),
-    .ch1(serial_clk_receicer),
-    .ch2(word_select_receicer),
-    .ch3(ad_sdout),     // serial data in
-    .ch4(master_clk),
-    .ch5(serial_clk_sender),
-    .ch6(word_select_sender),
-    .ch7(w_sd_tx),      // serial data out
-    .JXADC(JXADC)       // output for logic analizer   
-);
-
-
-//declare PLL to create 11.29 MHz master clock from 100 MHz system clock
-clk_wiz_0 m_clk(
-    .clk_in1(clk),
-    .clk_out1(master_clk)
-);
-
-// // instantiate I2S Transceiver component
-// i2s_transceiver  #(
-//     .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
-//     .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
-//     .d_width(d_width)                       //data width
-// ) i2s_transceiver (
-//     .reset_n(reset_n),         //asynchronous active high reset
-//     .mclk(master_clk),      //master clock
-//     .sclk(serial_clk),      //serial clock (or bit clock)
-//     .ws(word_select),       //word select (or left-right clock)
-//     .sd_rx(ad_sdout),       //serial data transmit
-//     .sd_tx(w_sd_tx),        //serial data receive
-//     .l_data_tx(l_data_tx),  //left channel data to transmit
-//     .r_data_tx(r_data_tx),  //right channel data to transmit
-//     .l_data_rx(l_data_rx),  //left channel data received
-//     .r_data_rx(r_data_rx)   //right channel data received
-// );
-
-i2s_sender  #(
-    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
-    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
-    .d_width(d_width)                       //data width
-) i2s_sender (
-    .reset_n(reset_n),      //asynchronous active high reset
-    .mclk(master_clk),      //master clock
-    .sclk(serial_clk_sender),      //serial clock (or bit clock)
-    .ws(word_select_sender),       //word select (or left-right clock)
-    .sd_tx(w_sd_tx),        //serial data transmit
-    .l_data_tx(l_data_tx),  //left channel data to transmit
-    .r_data_tx(r_data_tx)   //right channel data to transmit
-);
-
-i2s_receicer  #(
-    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
-    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
-    .d_width(d_width)                       //data width
-) i2s_receicer (
-    .reset_n(reset_n),         //asynchronous active high reset
-    .mclk(master_clk),      //master clock
-    .sclk(serial_clk_receicer),      //serial clock (or bit clock)
-    .ws(word_select_receicer),       //word select (or left-right clock)
-    .sd_rx(ad_sdout),       //serial data receive
-    .l_data_rx(l_data_rx),  //left channel data received
-    .r_data_rx(r_data_rx)   //right channel data received
-);
-
-//passing data to effect controler
-effect_controler #(
-    .d_width(d_width)                       //data width
-) effect_controler (
-//  .clk(clk),
-    .i_l_data(l_data_rx),               //left channel data received         
-    .i_r_data(r_data_rx),               //right channel data received
-    .o_l_data(l_data_tx),               //left channel data to transmit
-    .o_r_data(r_data_tx)                //right channel data to transmit
-);
-
-//debounce reset button
-debounce_switch debounce_switch_reset(
-    .clk(master_clk),
-    .i_switch(btnC),
-    .o_switch(reset_n)
-);
+//assign output from effect controler to leds
+assign led = l_data_tx[d_width-1: d_width-16];

 assign da_mclk = master_clk;    //output master clock to ADC
 assign ad_mclk = master_clk;    //output master clock to DAC
-assign da_sclk = serial_clk_sender;    //output serial clock (from I2S Transceiver) to ADC
-assign ad_sclk = serial_clk_receicer;    //output serial clock (from I2S Transceiver) to DAC
-assign da_lrck = word_select_sender;   //output word select (from I2S Transceiver) to ADC
-assign ad_lrck = word_select_receicer;   //output word select (from I2S Transceiver) to DAC
+// assign da_sdin = w_sd_tx;      //assign received data to transmit (to playback out received data)

-assign da_sdin = w_sd_tx;      //assign right channel received data to transmit (to playback out received data)
+
+//------internal wires and registers--------
+wire master_clk;            // 11.29 MHz master clock
+
+wire clk_50MHz;             // 
+
+wire                w_reset, w_reset1, w_reset2;
+wire                w_internal_reset;
+
+wire signed [d_width-1: 0] r_data_tx;
+wire signed [d_width-1: 0] l_data_tx;
+wire signed [d_width-1: 0] r_data_rx;
+wire signed [d_width-1: 0] l_data_rx;
+
+
+wire [d_width-1: 0] w_data_to_eff;
+wire                w_dv_to_eff;  
+
+wire                w_dv_from_eff; 
+wire                w_rd_en_from_eff;
+
+wire                w_read_done_eff;        // read done from effects module to mixer 
+wire                w_read_ready_eff;       // ready to read from effects module   
+
+// Data wires from effects module to effect controler
+wire [d_width-1: 0] w_data_from_eff_sw0;
+wire [d_width-1: 0] w_data_from_eff_sw1;
+
+
+
+//-----sub modules--------------------------
+
+// declare PLL to create 11.29 MHz master clock from 100 MHz system clock for I2S
+//
+// Common clocking errors with 7-Series FPGAs
+// http://www.markharvey.info/art/7clk_19.10.2015/7clk_19.10.2015.html
+clk_wiz_0 m_clk(
+    .clk_in1(clk),
+    .clk_out1(master_clk),  // 11.29 MHz master clock for I2S
+    .clk_out2(clk_50MHz),   // 25MHz main clock
+    .locked(w_internal_reset),
+    .reset(btnC)
+);
+
+// Flip-flops for reset
+d_flipflop_sync_rst D_flipflop1 (
+    .D(1'b0),
+    .Q(w_reset1),
+    .clk(master_clk),
+    .reset(~w_internal_reset));
+
+d_flipflop_sync_rst D_flipflop2 (
+    .D(w_reset1),
+    .Q(w_reset2),
+    .clk(master_clk),
+    .reset(~w_internal_reset));
+
+d_flipflop_sync_rst D_flipflop3 (
+    .D(w_reset2),
+    .Q(w_reset),
+    .clk(master_clk),
+    .reset(~w_internal_reset));
+
+
+
+io_module  #(
+    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
+    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
+    .d_width(d_width)                       //data width
+) io_module (
+    //.reset_n(reset_n),                  //asynchronous active high reset
+    .mclk(master_clk),                  //master clock
+    .da_sclk(da_sclk),                  //serial clock (or bit clock)
+    .da_ws(da_lrck),                    //word select (or left-right clock)
+    .ad_sclk(ad_sclk),                  //serial clock (or bit clock)
+    .ad_ws(ad_lrck),                    //word select (or left-right clock)
+    .sd_tx(da_sdin),                    //serial data transmit
+    .sd_rx(ad_sdout),                   //serial data receive
+    .l_data_tx(l_data_tx),              //left channel data to transmit
+    .r_data_tx(r_data_tx),              //right channel data to transmit
+
+    .reset(w_reset),           //reset 
+
+    .l_data_rx(l_data_rx),              //left channel data received
+    .r_data_rx(r_data_rx),              //right channel data received
+
+
+    // // inputs to logic analyzer
+    // .ch0(),
+    // .ch1(),
+    // .ch2(),
+    // .ch3(),
+    // .ch4(),
+    // .ch5(),
+    // .ch6(),
+    // .ch7(),
+
+    .JXADC(JXADC)                       // output for logic analizer
+);
+
+
+//Effect controler controls effects and perfoms multiplexing and data marging
+effect_controler #(
+    .d_width(d_width),                  // data width
+    .memory_d_width(memory_d_width)
+) effect_controler (
+    .reset(w_reset),                    // asynchronous active high reset
+    .mclk(master_clk),
+    .sw(sw[1:0]),
+    .clk(clk_50MHz),
+    .i_l_data(l_data_rx),               // left channel data received         
+    .i_r_data(r_data_rx),               // right channel data received
+    // .i_l_data({sw[15:2], 10'b0 }),               // left channel data received         
+    // .i_r_data({sw[15:2], 10'b0 }),               // right channel data received
+    .o_l_data(l_data_tx),               // left channel data to transmit
+    .o_r_data(r_data_tx),               // right channel data to transmit
+    .o_read_done(w_read_done_eff),      // read done from effects controler
+    .o_read_ready(w_read_ready_eff),    // ready read from reefects module
+
+    .o_data_to_eff(w_data_to_eff),      // Data output to effects module
+    .o_data_valid(w_dv_to_eff),         // data valid to read (FIFO not empty). data valid signal to effect module
+    
+    .i_read_enable(w_rd_en_from_eff),   // read enable from Effect module
+    .i_dv_from_eff(w_dv_from_eff),      // data valid write (FIFO not full). data valid signal from effect module
+    .i_data_from_eff_sw0(w_data_from_eff_sw0),   // Data input from effects module
+    .i_data_from_eff_sw1(w_data_from_eff_sw1)    // Data input from effects module
+);
+
+
+//Effect module contains all individual effects  
+effect_module #(
+    .d_width(memory_d_width)                    // data width
+) effect_module (
+    .clk(clk_50MHz),
+    .reset(w_reset),
+    .sw(sw[1:0]),                               // effect control swiches
+    .i_treshhold(sw[15:2]),
+    .i_data_ready(w_dv_to_eff),                 // data ready to read
+    .i_read_done(w_read_done_eff),              // read done from effects controler
+    .i_data(w_data_to_eff),                     // data input form effect controler
+    .o_read_enable(w_rd_en_from_eff),           // enable data reading
+    .o_data_valid(w_dv_from_eff),
+    .o_data_sw0(w_data_from_eff_sw0),
+    .o_data_sw1(w_data_from_eff_sw1)
+
+);


 endmodule
@@ -1,4 +1,4 @@
-// This file is Test Bench for top_vga_mem module
+// This file is Test Bench for top module
 //  
 //
Author	SHA1	Message	Date
Imants PulkstenisandGitHub	b132a68ca2	Update README.md	2020-02-10 21:28:51 +02:00
Imants PulkstenisandGitHub	2b997daa7e	Merge pull request #1 from Clockfix/add-license-1 Create LICENSE	2020-02-10 21:19:15 +02:00
Imants PulkstenisandGitHub	ac81b247d7	Create LICENSE	2020-02-10 21:19:05 +02:00
Imants PulkstenisandGitHub	575e4fee34	Update README.md	2020-02-10 21:06:18 +02:00
Imants Pulkstenis	c9e3a92ccb	Trying to fix audio issues	2020-01-21 21:26:29 +02:00
Imants Pulkstenis	e8095a4e68	add test beches	2020-01-21 21:23:47 +02:00
Imants Pulkstenis	bb79fe8730	Updated myfft3 file. Add calculations using fixed point integers and seperatly calculated real and imaginary numbers	2019-12-27 17:19:28 +02:00
Imants Pulkstenis	1a2289d877	minor changes	2019-12-27 13:17:42 +02:00
Aleksejs Mirnijs	6a422ee888	updatet figure plot Added xlim to figure(1)	2019-12-27 06:39:48 +02:00
Aleksejs Mirnijs	cf30046dbf	Added check for fftLength and some code minor updates	2019-12-25 15:50:56 +02:00
Aleksejs Mirnijs	e04020511a	Corrected separately complex number counting.	2019-12-25 11:08:18 +02:00
Aleksejs Mirnijs	790c73cab6	Updated comments	2019-12-23 15:06:02 +02:00
Aleksejs Mirnijs	f876a6a77a	Works separately with Real & Imag parts	2019-12-23 14:58:47 +02:00
Aleksejs Mirnijs	f1946c3b19	Corrected fft matlab code FFT Butterfly 4-1024 point code	2019-12-23 13:40:27 +02:00
Imants PulkstenisandGitHub	2ca0dd08ee	upload photo	2019-12-15 21:50:54 +02:00
Imants Pulkstenis	ae6b8e4ef9	add matlab files	2019-12-15 14:24:12 +02:00
Imants Pulkstenis	6519459430	treshold change	2019-12-03 22:48:43 +02:00
Imants Pulkstenis	9701ead6d3	Main clk speed changed from 25MHz to 50MHz add LEDs (outputs data from effects controler) add switches to control cliping treshold	2019-12-03 22:41:14 +02:00
Imants Pulkstenis	c86c2a267b	Merge branch 'master' of https://github.com/Clockfix/audio_effects_FPGA	2019-11-25 21:11:18 +02:00
Imants Pulkstenis	888bc47cd5	effect mixer update	2019-11-25 21:10:31 +02:00
Imants PulkstenisandGitHub	31c2b30c5a	Update README.md	2019-11-24 22:22:11 +02:00
Imants PulkstenisandGitHub	97649d2265	Update README.md	2019-11-24 22:13:20 +02:00
Imants PulkstenisandGitHub	85553b8660	Update README.md	2019-11-24 22:12:53 +02:00
Imants PulkstenisandGitHub	ce694c9844	Update README.md	2019-11-24 22:09:00 +02:00
Imants Pulkstenis	11c36aec2d	add effect mixer module and posibility to switch effects	2019-11-24 21:59:44 +02:00
Imants Pulkstenis	518bbe43cb	add flipflop module	2019-11-24 19:27:46 +02:00
Imants PulkstenisandGitHub	5e318949b6	Update README.md	2019-11-24 01:49:00 +02:00
Imants Pulkstenis	2d9f369ae9	readme commit	2019-11-24 01:44:24 +02:00
Imants Pulkstenis	60b57ed374	Merge branch 'master' of https://github.com/Clockfix/audio_effects_FPGA	2019-11-24 01:43:50 +02:00
Imants Pulkstenis	edf1ece511	Clipping effect now working	2019-11-24 01:43:20 +02:00
Imants PulkstenisandGitHub	cea943ba27	Update README.md	2019-11-23 23:05:41 +02:00
Imants PulkstenisandGitHub	af24d9fb43	Update README.md	2019-11-23 23:05:27 +02:00
Imants PulkstenisandGitHub	499869df4f	Update README.md	2019-11-23 23:03:15 +02:00
Imants PulkstenisandGitHub	12afd25ebf	Update README.md	2019-11-23 23:01:37 +02:00
Imants Pulkstenis	45caf399a1	readme file commit	2019-11-23 23:00:09 +02:00
Imants Pulkstenis	65b1690a47	Effect module added	2019-11-23 22:47:53 +02:00
Imants PulkstenisandGitHub	ee7edb0638	Update README.md	2019-11-22 01:02:10 +02:00
Imants PulkstenisandGitHub	131dee3643	Update README.md	2019-11-22 01:00:33 +02:00
Imants PulkstenisandGitHub	43d37fb9ad	Update README.md	2019-11-22 01:00:13 +02:00
Imants Pulkstenis	15dbd68ee2	Add fifo memory size variable.	2019-11-22 00:49:32 +02:00
Imants Pulkstenis	07cfe9893d	fifo module now working in loopback mode	2019-11-21 23:01:00 +02:00
Imants Pulkstenis	b8bfb00389	add fifo memory block	2019-11-21 22:21:35 +02:00
Imants Pulkstenis	4fc31319df	delete fifo files	2019-11-21 21:04:09 +02:00
Imants Pulkstenis	acef4ab3f2	update fifo files	2019-11-21 21:02:10 +02:00
Imants Pulkstenis	681d20fbf4	add FIFO files	2019-11-20 21:09:14 +02:00