add FIFO files

fifo.v

@@ -0,0 +1,65 @@
+// Sample code from https://www.fpga4student.com/2017/01/verilog-code-for-fifo-memory.html
+// with some modifications
+module fifo_mem(
+    output  [7:0]   data_out,
+    output          fifo_full, 
+    output          fifo_empty, 
+    output          fifo_threshold, 
+    output          fifo_overflow, 
+    output          fifo_underflow,
+    input           clk, 
+    input           rst_n, 
+    input           wr, 
+    input           rd, 
+    input   [7:0]   data_in
+);  
+    wire    [4:0]   wptr,
+                    rptr;  
+    wire            fifo_we,
+                    fifo_rd;   
+
+// sub modules
+    write_pointer write_pointer(
+        .wptr(wptr),
+        .fifo_we(fifo_we),
+        .wr(wr),
+        .fifo_full(fifo_full),
+        .clk(clk),
+        .rst_n(rst_n)
+    );  
+
+    read_pointer read_pointer(
+        .rptr(rptr),
+        .fifo_rd(fifo_rd),
+        .rd(rd),
+        .fifo_empty(fifo_empty),
+        .clk(clk),
+        .rst_n(rst_n)
+    );  
+
+    memory_array memory_array(
+        .data_out(data_out), 
+        .data_in(data_in), 
+        .clk(clk),
+        .fifo_we(fifo_we), 
+        .wptr(wptr),
+        .rptr(rptr)
+    );  
+
+
+    status_signal status_signal(
+        .fifo_full(fifo_full), 
+        .fifo_empty(fifo_empty), 
+        .fifo_threshold(), 
+        .fifo_overflow(fifo_overflow), 
+        .fifo_underflow(fifo_underflow), 
+        .wr(wr), 
+        .rd(rd), 
+        .fifo_we(fifo_we), 
+        .fifo_rd(fifo_rd), 
+        .wptr(wptr),
+        .rptr(rptr),
+        .clk(clk),
+        .rst_n(rst_n)
+    );  
+endmodule 

i2s_receiver.v

@@ -1,4 +1,4 @@
-// This I2S Playback design uses the common 44.1 kHz 
+// This I2S design uses the common 44.1 kHz 
 // sampling frequency.  
 // From Figure 2 in Section 4.1.1 of the CS5343 
 // Datasheet, it is appropriate to use an SCLK/LRCK 

memory_array.v

@@ -0,0 +1,20 @@
+module memory_array(
+    output  [7:0]   data_out, 
+    input   [7:0]   data_in, 
+    input           clk,
+    input           fifo_we, 
+    input   [4:0]   wptr,
+    input   [4:0]   rptr
+);  
+     
+    reg     [7:0]   data_out2   [15:0];  
+    wire    [7:0]   data_out;
+
+    always @(posedge clk)  
+    begin  
+        if(fifo_we)   
+            data_out2[wptr[3:0]] <=data_in ;  
+    end  
+
+    assign data_out = data_out2[rptr[3:0]];  
+endmodule  

read_pointer.v

@@ -0,0 +1,21 @@
+module read_pointer(
+    output  [4:0]   rptr,
+    output          fifo_rd,
+    input           rd,
+    input           fifo_empty,
+    input           clk,
+    input           rst_n);  
+   
+    reg     [4:0]   rptr;  
+    
+    assign fifo_rd = (~fifo_empty)& rd;  
+
+    always @(posedge clk or negedge rst_n)  
+    begin  
+        if(~rst_n) rptr <= 'b0;  
+        else if(fifo_rd)  
+            rptr <= rptr + 'b1;  
+        else  
+            rptr <= rptr;  
+    end  
+endmodule 

status_signal.v

@@ -0,0 +1,61 @@
+module status_signal(
+    output          fifo_full, 
+    output          fifo_empty, 
+    output          fifo_threshold, 
+    output          fifo_overflow, 
+    output          fifo_underflow, 
+    input           wr, 
+    input           rd, 
+    input           fifo_we, 
+    input           fifo_rd, 
+    input   [4:0]   wptr,
+    input   [4:0]   rptr,
+    input           clk,
+    input           rst_n);  
+ 
+    wire    fbit_comp, 
+            overflow_set, 
+            underflow_set;  
+    wire    pointer_equal;  
+    wire    [4:0]   pointer_result;  
+    reg     fifo_full, 
+            fifo_empty, 
+            fifo_threshold, 
+            fifo_overflow, 
+            fifo_underflow;  
+
+    assign fbit_comp = wptr[4] ^ rptr[4];  
+    assign pointer_equal = (wptr[3:0] - rptr[3:0]) ? 0:1;  
+    assign pointer_result = wptr[4:0] - rptr[4:0];  
+    assign overflow_set = fifo_full & wr;  
+    assign underflow_set = fifo_empty&rd; 
+
+    always @(*)  
+    begin  
+        fifo_full =fbit_comp & pointer_equal;  
+        fifo_empty = (~fbit_comp) & pointer_equal;  
+        fifo_threshold = (pointer_result[4]||pointer_result[3]) ? 1:0;  
+    end  
+
+    always @(posedge clk or negedge rst_n)  
+    begin  
+        if(~rst_n) fifo_overflow <=0;  
+        else if((overflow_set==1)&&(fifo_rd==0))  
+            fifo_overflow <=1;  
+        else if(fifo_rd)  
+            fifo_overflow <=0;  
+        else  
+            fifo_overflow <= fifo_overflow;  
+    end 
+
+    always @(posedge clk or negedge rst_n)  
+    begin  
+        if(~rst_n) fifo_underflow <=0;  
+        else if((underflow_set==1)&&(fifo_we==0))  
+            fifo_underflow <=1;  
+        else if(fifo_we)  
+            fifo_underflow <=0;  
+        else  
+            fifo_underflow <= fifo_underflow;  
+    end  
+endmodule  

write_pointer.v

@@ -0,0 +1,19 @@
+module write_pointer(
+    output  [4:0]   wptr,
+    output          fifo_we,
+    input           wr,
+    input           fifo_full,
+    input           clk,
+    input           rst_n);  
+
+    assign fifo_we = (~fifo_full)   &  wr;  
+
+    always @(posedge clk or negedge rst_n)  
+    begin  
+        if(~rst_n) wptr <= 'b0;  
+        else if(fifo_we)  
+            wptr <= wptr + 'b1;  
+        else  
+            wptr <= wptr;  
+    end  
+endmodule