imants/audio_effects_FPGA
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Imants Pulkstenis c9e3a92ccb Trying to fix audio issues
2020-01-21 21:26:29 +02:00
matlab
Updated myfft3 file. Add calculations using fixed point integers and seperatly calculated real and imaginary numbers
2019-12-27 17:19:28 +02:00
.gitignore
Added check for fftLength
2019-12-25 15:50:56 +02:00
Basys3_Master.xdc
Main clk speed changed from 25MHz to 50MHz
2019-12-03 22:41:14 +02:00
blockram.v
Add fifo memory size variable.
2019-11-22 00:49:32 +02:00
clipping_tb.v
add test beches
2020-01-21 21:23:47 +02:00
clipping.v
Trying to fix audio issues
2020-01-21 21:26:29 +02:00
clock_divider_param_tb.v
Initial commit
2019-10-04 23:40:15 +03:00
clock_divider_param.v
Effect module added
2019-11-23 22:47:53 +02:00
clock_enable_param.v
Initial commit
2019-10-04 23:40:15 +03:00
clock_enable_tb.v
Initial commit
2019-10-04 23:40:15 +03:00
d_flip-flop.v
add flipflop module
2019-11-24 19:27:46 +02:00
debounce_switch_tb.v
i2s_transceiver update and testbench
2019-10-13 17:00:57 +03:00
debounce_switch.v
works, but with high noises
2019-10-13 23:22:48 +03:00
effect_controler.v
Trying to fix audio issues
2020-01-21 21:26:29 +02:00
effect_mixer.v
Trying to fix audio issues
2020-01-21 21:26:29 +02:00
effect_module.v
treshold change
2019-12-03 22:48:43 +02:00
effects_tb.v
add test beches
2020-01-21 21:23:47 +02:00
i2s_receiver.v
add FIFO files
2019-11-20 21:09:14 +02:00
i2s_sender.v
repaired i2s (loopback audio working)
2019-10-20 19:27:16 +03:00
io_module.v
add flipflop module
2019-11-24 19:27:46 +02:00
JXADC_controler.v
Spliting i2s transceiver in to two modules
2019-10-20 18:38:10 +03:00
no_effect.v
Trying to fix audio issues
2020-01-21 21:26:29 +02:00
README.md
Update README.md
2019-11-24 22:22:11 +02:00
sync_fifo.v
Effect module added
2019-11-23 22:47:53 +02:00
top_tb.v
Trying to fix audio issues
2020-01-21 21:26:29 +02:00
top.v
Trying to fix audio issues
2020-01-21 21:26:29 +02:00

README.md

Audio effects on FPGA

Audio effect synthesizer on FPGA

Audio hardware

PMOD_I2S2 PMOD_I2S2_package

i2s timing diagram from PulseView i2s timing diagram

Top module Top module_sh

Edited effect control module - now it has input and output FIFO memory efect_controler

IO module io_module

Effects module with one clipping effect io_module

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Description
Audio effect synthesizer on FPGA
Readme MIT
980 KiB
Languages
Verilog 37.6%
MATLAB 31.8%
HTML 21.1%
Tcl 9.5%