Effect module added
This commit is contained in:
Imants Pulkstenis
+16
@@ -0,0 +1,16 @@
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module eclipping_effect #( parameter
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data_width = 16 // data width
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)(
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input clk,
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input reset,
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input signed [data_width-1: 0] i_data,
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output signed [data_width-1: 0] o_data,
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input [data_width-1: 0] i_treshhold
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);
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endmodule
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@@ -7,13 +7,13 @@ module clock_divider #(
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parameter DIVIDER =2,
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parameter WIDTH =2
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) (
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input clk,
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input clk_in,
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output clk_out);
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reg state=1'b0, next_state=1'b1;
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reg [WIDTH-1:0] counter = DIVIDER-1 ;
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always@(posedge clk)begin
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always@(posedge clk_in)begin
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state <= next_state;
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if ( counter == 0) begin
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next_state <= ~next_state;
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+48
-41
@@ -4,65 +4,72 @@ module effect_controler #( parameter
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ram_depth = 16, //
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memory_d_width = 16 //
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)(
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input clk,
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input mclk, // io_module clock
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input clk, // main clock
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input reset,
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input signed [d_width-1: 0] i_l_data,
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input signed [d_width-1: 0] i_r_data, // not used
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output signed [d_width-1: 0] o_l_data,
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output signed [d_width-1: 0] o_r_data
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output signed [d_width-1: 0] o_r_data,
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output signed [memory_d_width-1: 0] o_data_to_eff, // Data output to effects module
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output o_data_valid, // data valid to read (FIFO not empty). data valid signal to effect module
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input i_read_enable,
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input signed [memory_d_width-1: 0] i_data_from_eff, // Data output to effects module
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input i_dv_from_eff // data valid to read (FIFO not empty). data valid signal to effect module
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);
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wire signed [memory_d_width: 0] w_o_data;
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wire signed [memory_d_width-1: 0] w_o_data; //output data to io_module
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wire w_empty, w_full;
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wire [address_width:0] w_data_fill;
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//wire signed [memory_d_width-1: 0] w_o_data_eff; //output data to effects module
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wire w_empty_in, w_full_in;
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wire w_empty_out, w_full_out;
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wire [address_width-1:0] w_data_fill_input; // shows how full are in FIFO memmory for intput
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wire [address_width-1:0] w_data_fill_output; // shows how full are in FIFO memmory for output
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assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler
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assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left
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assign o_data_valid = ~w_empty_in;
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// Input FIFO
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sync_fifo #(
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.ram_depth(ram_depth), // ram memory depth
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.address_width(address_width), // ram memory address width
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//.data_width(d_width) // data width
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.data_width(memory_d_width) // memory data width
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) fifo_l (
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.data_out(w_o_data),
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.full(w_full),
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.empty(w_empty),
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.data_fill(w_data_fill),
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.data_in(i_l_data[ d_width-1 : d_width-memory_d_width ]),
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.clk(clk),
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.rst_a(reset),
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.wr_en( w_full ? 1'b0 : 1'b1 ),
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.rd_en((w_empty & (w_data_fill > 1 )) ? 1'b0 : 1'b1)
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) fifo_input (
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.data_out(o_data_to_eff),
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.full(w_full_in),
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.empty(w_empty_in),
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.data_fill(w_data_fill_input),
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.data_in(i_l_data[ d_width-1 : d_width - memory_d_width ]),
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.w_clk(mclk),
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.r_clk(clk),
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.reset(reset),
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.wr_en( w_full_in ? 1'b0 : 1'b1 ), // checking is FIFO full
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.rd_en( w_empty_in ? 1'b0 : i_read_enable ) // checking is FIFO empty
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);
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// sync_fifo #(
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// .ram_depth(ram_depth), // ram memory depth
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// .address_width(address_width), // ram memory address width
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// .data_width(d_width) // data width
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// ) fifo_r (
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// .data_out(o_r_data),
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// .full(),
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// .empty(),
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// .data_in(i_r_data),
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// .clk(clk),
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// .rst_a(reset),
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// .wr_en(1'b1),
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// .rd_en(1'b1)
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// );
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// Output FIFO
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sync_fifo #(
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.ram_depth(ram_depth), // ram memory depth
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.address_width(address_width), // ram memory address width
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.data_width(memory_d_width) // memory data width
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) fifo_output (
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.data_out(w_o_data),
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.full(w_full_out),
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.empty(w_empty_out),
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.data_fill(w_data_fill),
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.data_in(i_data_from_eff),
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.w_clk(clk),
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.r_clk(mclk),
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.reset(reset),
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.wr_en( w_full_out ? 1'b0 : i_dv_from_eff ), // checking is FIFO full
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.rd_en( w_empty_out ? 1'b0 : 1'b1 ) // checking is FIFO empty
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);
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// always@* begin
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// o_l_data <= i_l_data;
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// o_r_data <= i_r_data;
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// end
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//assign o_l_data = i_l_data;
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//assign o_r_data = i_r_data;
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//assign o_l_data = 24'h000000;
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//assign o_r_data = 24'h400008;
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endmodule
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@@ -0,0 +1,30 @@
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module effect_module #( parameter
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d_width = 16 // data width
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)(
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input clk,
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input reset,
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input i_data_ready, // data ready to read
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input signed [d_width-1: 0] i_data, // data input form effect controler
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output read_enable, // enable data reading
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output signed [d_width-1: 0] o_data, // data output form effect controler
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output data_valid
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);
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assign o_data = i_data_ready ? i_data : 'b0 ;
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assign read_enable = i_data_ready ? 1 : 0 ;
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assign data_valid = i_data_ready ? 1 : 0 ;
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// // cliping effect
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// eclipping_effect #(
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// .data_width(d_width) // data width
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// ) eclipping_effect (
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// .clk(clk),
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// .reset(reset),
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// .i_data(i_data),
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// .o_data(o_data)
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// );
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endmodule
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+90
@@ -0,0 +1,90 @@
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module io_module #( parameter
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sclk_ws_ratio = 64, // number of sclk periods per word select period
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mclk_sclk_ratio = 4, // number of mclk periods per sclk period
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d_width = 24 // data width
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)(
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output reset_n, //asynchronous active low reset
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input mclk, //master clock
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output ad_sclk, //serial clock (or bit clock)
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output ad_ws, //word select (or left-right clock)
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output da_sclk, //serial clock (or bit clock)
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output da_ws, //word select (or left-right clock)
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output sd_tx, //serial data transmit
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input sd_rx, //serial data receive
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input signed [d_width-1: 0] l_data_tx, //left channel data to transmit
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input signed [d_width-1: 0] r_data_tx, //right channel data to transmit
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output signed [d_width-1: 0] l_data_rx, //left channel data received
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output signed [d_width-1: 0] r_data_rx, //right channel data received
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input btnC,
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// // inputs to logic analyzer
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// input ch0,
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// input ch1,
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// input ch2,
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// input ch3,
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// input ch4,
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// input ch5,
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// input ch6,
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// input ch7,
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output [7: 0] JXADC // output for logic analizer
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);
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i2s_sender #(
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.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
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.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
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.d_width(d_width) //data width
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) i2s_sender (
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.reset_n(reset_n), //asynchronous active high reset
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.mclk(mclk), //master clock
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.sclk(da_sclk), //serial clock (or bit clock)
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.ws(da_ws), //word select (or left-right clock)
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.sd_tx(sd_tx), //serial data transmit
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.l_data_tx(l_data_tx), //left channel data to transmit
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.r_data_tx(r_data_tx) //right channel data to transmit
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);
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i2s_receicer #(
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.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
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.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
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.d_width(d_width) //data width
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) i2s_receicer (
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.reset_n(reset_n), //asynchronous active high reset
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.mclk(mclk), //master clock
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.sclk(ad_sclk), //serial clock (or bit clock)
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.ws(ad_ws), //word select (or left-right clock)
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.sd_rx(sd_rx), //serial data receive
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.l_data_rx(l_data_rx), //left channel data received
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.r_data_rx(r_data_rx) //right channel data received
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);
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// connecting signals to JXADC PMOD to monitor them with signal analyzer
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JXADC_controler JXADC_controler(
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.ch0(mclk),
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.ch1(ad_sclk),
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.ch2(ad_ws),
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.ch3(sd_rx), // serial data in
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.ch4(mclk),
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.ch5(da_sclk),
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.ch6(da_ws),
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.ch7(sd_tx), // serial data out
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.JXADC(JXADC) // output for logic analizer
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);
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// debounce reset button
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debounce_switch debounce_switch_reset(
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.clk(mclk),
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.i_switch(btnC),
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.o_switch(reset_n)
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);
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endmodule
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+56
-28
@@ -5,16 +5,17 @@ module sync_fifo #( parameter
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//---------------parametre declaration
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data_width = 4,
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address_width = 4,
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ram_depth = 16
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ram_depth = 16 // must be 2^n
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)(
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//--------------input output port declaration
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output reg signed [data_width-1:0] data_out,
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output full,
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output empty,
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output [address_width:0] data_fill,
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input signed [data_width-1:0] data_in,
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input clk,
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input rst_a,
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output [address_width-1:0] data_fill,
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input signed [data_width-1:0] data_in,
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input w_clk, // write clock
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input r_clk, // read clock
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input reset,
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input wr_en,
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input rd_en);
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@@ -22,51 +23,78 @@ module sync_fifo #( parameter
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//--------------internal register declaration
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reg [address_width-1:0] wr_pointer = 0;
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reg [address_width-1:0] rd_pointer = 0;
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reg [address_width :0] status_count = 0;
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// reg [address_width :0] status_count = 0;
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wire signed [data_width-1:0] data_ram ;
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// reg addition = 0;
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// reg subtractor = 0;
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// always@(posedge addition )
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// begin
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// if (addition ^ subtractor) // if XOR
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// begin
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// if (status_count != 0)
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// status_count = status_count + 1;
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// end
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// addition = 0; // reset addition
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// end
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// always@(posedge subtractor)
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// begin
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// if (addition ^ subtractor) // if XOR
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// begin
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// if (status_count != 0)
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// status_count = status_count - 1;
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// end
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// subtractor = 0; // reset subtractor
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// end
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//--------------wr_pointer pointing to write address
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always @ (posedge clk,posedge rst_a)
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always @ (posedge w_clk,posedge reset)
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begin
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if(rst_a)
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if(reset)
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wr_pointer = 0;
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else if(wr_en)
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wr_pointer = wr_pointer+1;
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//addition = 1;
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end
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//-------------rd_pointer points to read address
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always @ (posedge clk,posedge rst_a)
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always @ (posedge r_clk,posedge reset)
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begin
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if(rst_a)
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if(reset)
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rd_pointer = 0;
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else if(rd_en)
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rd_pointer = rd_pointer+1;
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rd_pointer = rd_pointer + 1;
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//subtractor = 1;
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end
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//-------------read from FIFO
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always @ (posedge clk,posedge rst_a)
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always @ (posedge r_clk,posedge reset)
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begin
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if(rst_a)
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if(reset)
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data_out=0;
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else if(rd_en)
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data_out=data_ram;
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end
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//--------------Status pointer for full and empty checking
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always @ (posedge clk,posedge rst_a)
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begin
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if(rst_a)
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status_count = 0;
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else if(wr_en && !rd_en && (status_count != ram_depth))
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status_count = status_count + 1;
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else if(rd_en && !wr_en && (status_count != 0))
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status_count = status_count - 1;
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end // always @ (posedge clk,posedge rst_a)
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// //--------------Status pointer for full and empty checking
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// always @ (posedge w_clk,posedge r_clk,posedge reset)
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// begin
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// if(reset)
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// status_count = 0;
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// else if(wr_en && !rd_en && (status_count != ram_depth))
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// status_count = status_count + 1;
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// else if(rd_en && !wr_en && (status_count != 0))
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// status_count = status_count - 1;
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// end // always @ (posedge clk,posedge reset)
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assign full = (status_count == (ram_depth));
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assign empty = (status_count == 0);
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assign data_fill = status_count; // how full are FIFO
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// assign full = (status_count == (ram_depth));
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// assign empty = (status_count == 0);
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// assign data_fill = status_count; // how full are FIFO
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assign full = (wr_pointer - rd_pointer == ram_depth) ? 1'b1 : 1'b0 ;
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assign empty = (wr_pointer - rd_pointer == 0) ? 1'b1 : 1'b0 ;
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assign data_fill = wr_pointer - rd_pointer ; // how full are FIFO
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rams_tdp_rf_rf #(
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.DEPTH(ram_depth),
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@@ -83,8 +111,8 @@ rams_tdp_rf_rf #(
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.web(1'b0),
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.ena(1'b1),
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.enb(rd_en),
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.clka(clk),
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.clkb(clk)
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.clka(w_clk),
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.clkb(r_clk)
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);
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endmodule // sync_fifo
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@@ -1,8 +1,8 @@
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// TOP module
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//
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//
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//
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//
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module top #( parameter
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sclk_ws_ratio = 64, // number of sclk periods per word select period
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mclk_sclk_ratio = 4, // number of mclk periods per sclk period
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@@ -22,115 +22,111 @@ module top #( parameter
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output [7: 0] JXADC // output for logic analizer
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);
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assign da_mclk = master_clk; //output master clock to ADC
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assign ad_mclk = master_clk; //output master clock to DAC
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// assign da_sdin = w_sd_tx; //assign received data to transmit (to playback out received data)
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//------internal wires and registers--------
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wire master_clk; // 11.29 MHz master clock
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wire serial_clk_sender;
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wire word_select_sender;
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wire serial_clk_receicer;
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wire word_select_receicer;
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wire clk_25MHz; //
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wire reset_n;
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wire [d_width-1: 0] r_data_tx;
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wire [d_width-1: 0] l_data_tx;
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wire [d_width-1: 0] r_data_rx;
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wire [d_width-1: 0] l_data_rx;
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wire w_sd_tx; //internal wire
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wire [d_width-1: 0] w_data_to_eff;
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wire w_dv_to_eff;
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wire [d_width-1: 0] w_data_from_eff;
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wire w_dv_from_eff;
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wire w_rd_en_from_eff;
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//-----sub modules--------------------------
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// connecting signals to JXADC PMOD to monitor them with signal analyzer
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JXADC_controler JXADC_controler(
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.ch0(master_clk),
|
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.ch1(serial_clk_receicer),
|
||||
.ch2(word_select_receicer),
|
||||
.ch3(ad_sdout), // serial data in
|
||||
.ch4(master_clk),
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.ch5(serial_clk_sender),
|
||||
.ch6(word_select_sender),
|
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.ch7(w_sd_tx), // serial data out
|
||||
.JXADC(JXADC) // output for logic analizer
|
||||
);
|
||||
|
||||
|
||||
//declare PLL to create 11.29 MHz master clock from 100 MHz system clock
|
||||
//declare PLL to create 11.29 MHz master clock from 100 MHz system clock for I2S
|
||||
clk_wiz_0 m_clk(
|
||||
.clk_in1(clk),
|
||||
.clk_out1(master_clk)
|
||||
.clk_out1(master_clk), // 11.29 MHz master clock for I2S
|
||||
.clk_out2(clk_25MHz) // 25MHz main clock
|
||||
);
|
||||
|
||||
// // instantiate I2S Transceiver component
|
||||
// i2s_transceiver #(
|
||||
// .mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
|
||||
// .sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
|
||||
// .d_width(d_width) //data width
|
||||
// ) i2s_transceiver (
|
||||
// .reset_n(reset_n), //asynchronous active high reset
|
||||
// .mclk(master_clk), //master clock
|
||||
// .sclk(serial_clk), //serial clock (or bit clock)
|
||||
// .ws(word_select), //word select (or left-right clock)
|
||||
// .sd_rx(ad_sdout), //serial data transmit
|
||||
// .sd_tx(w_sd_tx), //serial data receive
|
||||
// .l_data_tx(l_data_tx), //left channel data to transmit
|
||||
// .r_data_tx(r_data_tx), //right channel data to transmit
|
||||
// .l_data_rx(l_data_rx), //left channel data received
|
||||
// .r_data_rx(r_data_rx) //right channel data received
|
||||
// );
|
||||
|
||||
i2s_sender #(
|
||||
io_module #(
|
||||
.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
|
||||
.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
|
||||
.d_width(d_width) //data width
|
||||
) i2s_sender (
|
||||
.reset_n(reset_n), //asynchronous active high reset
|
||||
.mclk(master_clk), //master clock
|
||||
.sclk(serial_clk_sender), //serial clock (or bit clock)
|
||||
.ws(word_select_sender), //word select (or left-right clock)
|
||||
.sd_tx(w_sd_tx), //serial data transmit
|
||||
.l_data_tx(l_data_tx), //left channel data to transmit
|
||||
.r_data_tx(r_data_tx) //right channel data to transmit
|
||||
) io_module (
|
||||
.reset_n(reset_n), //asynchronous active high reset
|
||||
.mclk(master_clk), //master clock
|
||||
.da_sclk(da_sclk), //serial clock (or bit clock)
|
||||
.da_ws(da_lrck), //word select (or left-right clock)
|
||||
.ad_sclk(ad_sclk), //serial clock (or bit clock)
|
||||
.ad_ws(ad_lrck), //word select (or left-right clock)
|
||||
.sd_tx(da_sdin), //serial data transmit
|
||||
.sd_rx(ad_sdout), //serial data receive
|
||||
.l_data_tx(l_data_tx), //left channel data to transmit
|
||||
.r_data_tx(r_data_tx), //right channel data to transmit
|
||||
|
||||
.btnC(btnC), //reset button input
|
||||
|
||||
.l_data_rx(l_data_rx), //left channel data received
|
||||
.r_data_rx(r_data_rx), //right channel data received
|
||||
|
||||
|
||||
// // inputs to logic analyzer
|
||||
// .ch0(),
|
||||
// .ch1(),
|
||||
// .ch2(),
|
||||
// .ch3(),
|
||||
// .ch4(),
|
||||
// .ch5(),
|
||||
// .ch6(),
|
||||
// .ch7(),
|
||||
|
||||
.JXADC(JXADC) // output for logic analizer
|
||||
);
|
||||
|
||||
i2s_receicer #(
|
||||
.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
|
||||
.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
|
||||
.d_width(d_width) //data width
|
||||
) i2s_receicer (
|
||||
.reset_n(reset_n), //asynchronous active high reset
|
||||
.mclk(master_clk), //master clock
|
||||
.sclk(serial_clk_receicer), //serial clock (or bit clock)
|
||||
.ws(word_select_receicer), //word select (or left-right clock)
|
||||
.sd_rx(ad_sdout), //serial data receive
|
||||
.l_data_rx(l_data_rx), //left channel data received
|
||||
.r_data_rx(r_data_rx) //right channel data received
|
||||
);
|
||||
|
||||
//passing data to effect controler
|
||||
//Effect controler controls effects and perfoms multiplexing and data marging
|
||||
effect_controler #(
|
||||
.d_width(d_width), //data width
|
||||
.memory_d_width(memory_d_width)
|
||||
) effect_controler (
|
||||
.reset(reset_n), //asynchronous active high reset
|
||||
.clk(master_clk),
|
||||
.mclk(master_clk),
|
||||
.clk(clk_25MHz),
|
||||
.i_l_data(l_data_rx), //left channel data received
|
||||
.i_r_data(r_data_rx), //right channel data received
|
||||
.o_l_data(l_data_tx), //left channel data to transmit
|
||||
.o_r_data(r_data_tx) //right channel data to transmit
|
||||
.o_r_data(r_data_tx), //right channel data to transmit
|
||||
|
||||
.o_data_to_eff(w_data_to_eff), // Data output to effects module
|
||||
.o_data_valid(w_dv_to_eff), // data valid to read (FIFO not empty). data valid signal to effect module
|
||||
|
||||
.i_read_enable(w_rd_en_from_eff), //read enable from Effect module
|
||||
.i_data_from_eff(w_data_from_eff), // Data input from effects module
|
||||
.i_dv_from_eff(w_dv_from_eff) // data valid write (FIFO not full). data valid signal from effect module
|
||||
);
|
||||
|
||||
//debounce reset button
|
||||
debounce_switch debounce_switch_reset(
|
||||
.clk(master_clk),
|
||||
.i_switch(btnC),
|
||||
.o_switch(reset_n)
|
||||
|
||||
//Effect module contains all individual effects
|
||||
effect_module #(
|
||||
.d_width(memory_d_width) //data width
|
||||
) effect_module (
|
||||
.clk(clk_25MHz),
|
||||
.reset(reset_n),
|
||||
.i_data_ready(w_dv_to_eff), // data ready to read
|
||||
.i_data(w_data_to_eff), // data input form effect controler
|
||||
.read_enable(w_rd_en_from_eff), // enable data reading
|
||||
.o_data(w_data_from_eff),
|
||||
.data_valid(w_dv_from_eff)
|
||||
|
||||
);
|
||||
|
||||
assign da_mclk = master_clk; //output master clock to ADC
|
||||
assign ad_mclk = master_clk; //output master clock to DAC
|
||||
assign da_sclk = serial_clk_sender; //output serial clock (from I2S Transceiver) to ADC
|
||||
assign ad_sclk = serial_clk_receicer; //output serial clock (from I2S Transceiver) to DAC
|
||||
assign da_lrck = word_select_sender; //output word select (from I2S Transceiver) to ADC
|
||||
assign ad_lrck = word_select_receicer; //output word select (from I2S Transceiver) to DAC
|
||||
|
||||
assign da_sdin = w_sd_tx; //assign right channel received data to transmit (to playback out received data)
|
||||
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user