Add fifo memory size variable.
This commit is contained in:
Imants Pulkstenis
+3
-3
@@ -7,15 +7,15 @@
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// Dual-Port Block RAM with Two Write Ports
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// File: blobkram.v
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module blockram #( parameter
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module rams_tdp_rf_rf #( parameter
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DEPTH = 16,
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ADDR_WIDTH = 4,
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DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
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input clka,clkb,ena,enb,wea,web;
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input [ADDR_WIDTH-1:0] addra,addrb;
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input signed [DATA_WIDTH-1:0] dia,dib;
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output signed [DATA_WIDTH-1:0] doa,dob;
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input [DATA_WIDTH-1:0] dia,dib;
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output [DATA_WIDTH-1:0] doa,dob;
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reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0];
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reg [DATA_WIDTH-1:0] doa,dob;
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+32
-23
@@ -1,47 +1,56 @@
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module effect_controler #( parameter
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d_width = 24, // data width
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address_width = 4, //
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ram_depth = 16 //
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ram_depth = 16, //
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memory_d_width = 16 //
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)(
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input clk,
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input reset,
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input signed [d_width-1: 0] i_l_data,
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input signed [d_width-1: 0] i_r_data,
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input signed [d_width-1: 0] i_r_data, // not used
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output signed [d_width-1: 0] o_l_data,
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output signed [d_width-1: 0] o_r_data
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);
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wire signed [memory_d_width: 0] w_o_data;
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wire w_empty, w_full;
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wire [address_width:0] w_data_fill;
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assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler
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assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left
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sync_fifo #(
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.ram_depth(ram_depth), // ram memory depth
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.address_width(address_width), // ram memory address width
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.data_width(d_width) // data width
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//.data_width(d_width) // data width
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.data_width(memory_d_width) // memory data width
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) fifo_l (
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.data_out(o_l_data),
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.full(),
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.empty(),
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.data_in(i_l_data),
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.data_out(w_o_data),
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.full(w_full),
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.empty(w_empty),
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.data_fill(w_data_fill),
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.data_in(i_l_data[ d_width-1 : d_width-memory_d_width ]),
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.clk(clk),
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.rst_a(reset),
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.wr_en(1'b1),
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.rd_en(1'b1)
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.wr_en( w_full ? 1'b0 : 1'b1 ),
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.rd_en((w_empty & (w_data_fill > 1 )) ? 1'b0 : 1'b1)
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);
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sync_fifo #(
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.ram_depth(ram_depth), // ram memory depth
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.address_width(address_width), // ram memory address width
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.data_width(d_width) // data width
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) fifo_r (
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.data_out(o_r_data),
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.full(),
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.empty(),
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.data_in(i_r_data),
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.clk(clk),
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.rst_a(reset),
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.wr_en(1'b1),
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.rd_en(1'b1)
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);
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// sync_fifo #(
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// .ram_depth(ram_depth), // ram memory depth
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// .address_width(address_width), // ram memory address width
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// .data_width(d_width) // data width
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// ) fifo_r (
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// .data_out(o_r_data),
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// .full(),
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// .empty(),
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// .data_in(i_r_data),
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// .clk(clk),
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// .rst_a(reset),
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// .wr_en(1'b1),
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// .rd_en(1'b1)
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// );
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// always@* begin
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+6
-5
@@ -11,6 +11,7 @@ module sync_fifo #( parameter
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output reg signed [data_width-1:0] data_out,
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output full,
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output empty,
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output [address_width:0] data_fill,
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input signed [data_width-1:0] data_in,
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input clk,
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input rst_a,
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@@ -19,10 +20,9 @@ module sync_fifo #( parameter
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//--------------internal register declaration
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reg [address_width-1:0] wr_pointer;
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reg [address_width-1:0] rd_pointer;
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reg [address_width :0] status_count;
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reg signed [data_width-1:0] data_out ;
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reg [address_width-1:0] wr_pointer = 0;
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reg [address_width-1:0] rd_pointer = 0;
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reg [address_width :0] status_count = 0;
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wire signed [data_width-1:0] data_ram ;
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@@ -66,8 +66,9 @@ wire signed [data_width-1:0] data_ram ;
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assign full = (status_count == (ram_depth));
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assign empty = (status_count == 0);
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assign data_fill = status_count; // how full are FIFO
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blockram #(
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rams_tdp_rf_rf #(
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.DEPTH(ram_depth),
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.ADDR_WIDTH(address_width),
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.DATA_WIDTH(data_width)
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@@ -6,7 +6,8 @@
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module top #( parameter
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sclk_ws_ratio = 64, // number of sclk periods per word select period
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mclk_sclk_ratio = 4, // number of mclk periods per sclk period
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d_width = 24 // data width
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d_width = 24, // data width for I2S
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memory_d_width = 16 // data width for memory (and effects). lower bits are ignored
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)(
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input clk,
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input btnC,
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@@ -104,7 +105,8 @@ i2s_receicer #(
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//passing data to effect controler
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effect_controler #(
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.d_width(d_width) //data width
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.d_width(d_width), //data width
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.memory_d_width(memory_d_width)
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) effect_controler (
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.reset(reset_n), //asynchronous active high reset
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.clk(master_clk),
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