add effect mixer module and posibility to switch effects
This commit is contained in:
Imants Pulkstenis
+2
-2
@@ -13,11 +13,11 @@ module clipping_effect #( parameter
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);
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//-------------Internal Constants---------------------------
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localparam [3:0] IDLE = 'd0,
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localparam [2:0] IDLE = 'd0,
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CLIP = 'd1,
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OUTPUT = 'd2;
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reg [3:0] r_state=IDLE, r_next=IDLE;
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reg [2:0] r_state=IDLE, r_next=IDLE;
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reg signed [data_width-1: 0] r_data = 'b0;
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reg signed [data_width-1: 0] r_treshhold_p = 'b0;
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+37
-4
@@ -12,10 +12,18 @@ module effect_controler #( parameter
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output signed [d_width-1: 0] o_l_data,
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output signed [d_width-1: 0] o_r_data,
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output o_read_done, // read done from effects module
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output o_read_ready, // ready read from reefects module
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input [1:0] sw, // effect control swiches
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output signed [memory_d_width-1: 0] o_data_to_eff, // Data output to effects module
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output o_data_valid, // data valid to read (FIFO not empty). data valid signal to effect module
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input i_read_enable,
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input signed [memory_d_width-1: 0] i_data_from_eff, // Data output to effects module
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input i_read_enable, // enable read from input fifo
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input signed [memory_d_width-1: 0] i_data_from_eff_sw0, // Data output to effects module
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input signed [memory_d_width-1: 0] i_data_from_eff_sw1, // Data output to effects module
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input i_dv_from_eff // data valid to read (FIFO not empty). data valid signal to effect module
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);
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@@ -26,9 +34,14 @@ wire signed [memory_d_width-1: 0] w_o_data; //output data to io_module
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wire w_empty_in, w_full_in;
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wire w_empty_out, w_full_out;
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wire [memory_d_width-1:0] w_data_to_fifo; // wire connets mixer to output fifo
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wire [address_width-1:0] w_data_fill_input; // shows how full are in FIFO memmory for intput
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wire [address_width-1:0] w_data_fill_output; // shows how full are in FIFO memmory for output
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wire w_data_valid_to_fifo; // data valid to write output FIFO from mixer
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assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler
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assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left
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@@ -62,14 +75,34 @@ sync_fifo #(
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.full(w_full_out),
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.empty(w_empty_out),
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.data_fill(w_data_fill),
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.data_in(i_data_from_eff),
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.data_in(w_data_to_fifo),
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.w_clk(clk),
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.r_clk(mclk),
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.reset(reset),
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.wr_en( w_full_out ? 1'b0 : i_dv_from_eff ), // checking is FIFO full
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.wr_en( w_data_valid_to_fifo ), // checking of FIFO full are performing mixer module
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.rd_en( w_empty_out ? 1'b0 : 1'b1 ) // checking is FIFO empty
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);
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// Effect mixer, performs audio data merging
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effect_mixer #(
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.data_width(memory_d_width) // memory data width
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) effect_mixer (
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.sw(sw),
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.clk(clk),
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.reset(reset),
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.i_fifo_full(w_full_out),
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.o_read_done(o_read_done), // read from effect module done
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.o_read_ready(o_read_ready), // ready to read from effect module
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.o_data(w_data_to_fifo), // data to output FIFO memory
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.o_data_valid(w_data_valid_to_fifo),
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.i_dv_from_eff(i_dv_from_eff),
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.i_data_from_eff_sw0(i_data_from_eff_sw0), // Data output to effects module
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.i_data_from_eff_sw1(i_data_from_eff_sw1)
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);
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endmodule
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+129
@@ -0,0 +1,129 @@
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module effect_mixer #( parameter
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data_width = 16 // data width
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)(
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input clk,
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input [1:0] sw,
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input reset,
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input i_fifo_full,
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output signed [data_width-1: 0] o_data,
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output o_read_done, // read from effect module done
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output o_read_ready, // ready to read from effect module
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output o_data_valid, // data valit to write in FIFO memory
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input i_dv_from_eff,
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input signed [data_width-1: 0] i_data_from_eff_sw0, // Data output to effects module
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input signed [data_width-1: 0] i_data_from_eff_sw1
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);
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//-------------Internal Constants---------------------------
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localparam [2:0] IDLE = 'd0,
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ADD = 'd1,
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NORM = 'd2,
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OUTPUT = 'd3;
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reg [2:0] r_state=IDLE, r_next=IDLE;
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reg signed [data_width-1: 0] r_data_sw0 = 'b0;
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reg signed [data_width-1: 0] r_data_sw1 = 'b0;
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reg signed [data_width: 0] r_data_add = 'b0;
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reg signed [data_width-1: 0] r_data_norm = 'b0;
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reg r_read_done = 0;
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reg r_read_ready = 0;
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reg r_data_valid = 0;
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assign o_read_done = r_read_done;
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assign o_data_valid = r_data_valid;
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assign o_data = r_data_norm;
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//---------state register sequential always block-----------
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always @(posedge clk ) begin
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if (reset == 1) begin
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// clear state
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r_state <= IDLE;
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r_next <= IDLE;
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end
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else begin
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r_state <= r_next;
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end
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end
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//----next state & outputs, combinational always block------
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always @(posedge clk ) begin
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case(r_state)
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IDLE : begin
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if (i_dv_from_eff == 1) begin
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r_next <= ADD;
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r_data_sw0 <= i_data_from_eff_sw0;
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r_data_sw1 <= i_data_from_eff_sw1;
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r_read_done <= 1;
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r_read_ready <= 0;
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r_data_valid <= 0;
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end
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else begin
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r_next <= IDLE;
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r_read_ready <= 1; // redy to read data
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r_data_valid <= 0;
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end
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end
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ADD : begin
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case ( sw )
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0 : begin // off all sound
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r_data_add <= 0;
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end
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1 : begin // no effect only
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r_data_add <= r_data_sw0;
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end
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2 : begin // clipping effect only
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r_data_add <= r_data_sw1;
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end
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3 : begin // no effect and clipping effect
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r_data_add <= r_data_sw0 + r_data_sw1;
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end
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endcase
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r_next <= NORM;
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r_read_done <= 0;
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end
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NORM : begin
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case ( sw )
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0 : begin // off all sound
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r_data_norm <= 0;
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end
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1 : begin // no effect only
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r_data_norm <= r_data_add[data_width-1: 0];
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end
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2 : begin // clipping effect only
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r_data_norm <= r_data_add[data_width-1: 0];
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end
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3 : begin // no effect and clipping effect
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r_data_norm <= r_data_add[data_width-1: 0] >>> 1; // Shift Right, Arithmetic (keep sign)
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end
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endcase
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r_next <= OUTPUT;
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end
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OUTPUT : begin
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if ((i_fifo_full == 1) & (i_dv_from_eff == 1)) begin // wait for FIFO memory and data valid in effect module
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r_next <= OUTPUT;
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r_read_done <= 0;
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r_read_ready <= 0;
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r_data_valid <= 0;
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end
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else begin
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r_next <= IDLE;
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r_read_ready <= 0; // redy to read data
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r_data_valid <= 1; // data valid to write in FIFO
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end
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end
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default: r_next <= IDLE; // on error
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endcase
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end
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endmodule
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+50
-21
@@ -6,37 +6,66 @@ module effect_module #( parameter
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input [1:0] sw, // effect control swiches
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input i_data_ready, // data ready to read
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input signed [d_width-1: 0] i_data, // data input form effect controler
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output o_read_enable, // enable data reading
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input i_read_done, // read done from effects controler
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output signed [d_width-1: 0] o_data, // data output form effect controler
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output o_data_valid
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output o_data_valid,
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output o_read_enable,
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// SW0 no effect
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output signed [d_width-1: 0] o_data_sw0, // data output form effect controler
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// SW1 clipping effect
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output signed [d_width-1: 0] o_data_sw1 // data output form effect controler
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);
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// Wires for cliping effect
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wire signed [d_width-1: 0] w_data_ce;
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wire w_read_enable_ce;
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wire w_data_valid_ce;
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wire signed [d_width-1: 0] w_data_sw0;
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wire w_read_enable_sw0;
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wire w_data_valid_sw0;
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wire signed [d_width-1: 0] w_data_sw1;
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wire w_read_enable_sw1;
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wire w_data_valid_sw1;
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// asynchronous logic ---------------------------------------
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assign o_data_sw0 = w_data_sw0;
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assign o_data_sw1 = w_data_sw1;
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assign o_read_enable = w_read_enable_sw0 & w_read_enable_sw1;
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assign o_data_valid = w_data_valid_sw0 & w_data_valid_sw1;
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// Individual effect modules -----------------------------
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// no effect SW0
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no_effect #(
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.data_width(d_width) // data width
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) no_effect (
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.clk(clk),
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.reset(reset),
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.i_data(i_data),
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.i_read_done(i_read_done), // read done from effects controler
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.i_data_ready(i_data_ready),
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.o_data(w_data_sw0),
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.o_read_enable(w_read_enable_sw0),
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.o_data_valid(w_data_valid_sw0)
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);
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assign o_data = w_data_ce;// ? w_data_ce : 'b0 ;
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assign o_read_enable = w_read_enable_ce;//(i_data_ready & w_data_valid_ce ) ? w_read_enable_ce : 0 ;
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assign o_data_valid = w_data_valid_ce;//(i_data_ready & w_data_valid_ce ) ? w_data_valid_ce : 0 ;
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// clipping effect
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// clipping effect SW1
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clipping_effect #(
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.data_width(d_width) // data width
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.data_width(d_width) // data width
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) clipping_effect (
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.clk(clk),
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.reset(reset),
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.i_treshhold(16'h00f0),
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.i_data(i_data),
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.i_read_done(i_data_ready),
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.o_data(w_data_ce),
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.o_read_enable(w_read_enable_ce),
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.o_data_valid(w_data_valid_ce),
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.i_data_ready(i_data_ready)
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.clk(clk),
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.reset(reset),
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.i_treshhold(16'h00f0),
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.i_data(i_data),
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.i_read_done(i_read_done), // read done from effects controler
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.i_data_ready(i_data_ready),
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.o_data(w_data_sw1),
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.o_read_enable(w_read_enable_sw1),
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.o_data_valid(w_data_valid_sw1)
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);
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+77
@@ -0,0 +1,77 @@
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module no_effect #( parameter
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data_width = 16 // data width
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)(
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input clk,
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input reset,
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input signed [data_width-1: 0] i_data,
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output signed [data_width-1: 0] o_data,
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input i_read_done,
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output o_read_enable,
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output o_data_valid,
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input i_data_ready
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);
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//-------------Internal Constants---------------------------
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localparam [3:0] IDLE = 'd0,
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OUTPUT = 'd1;
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reg [3:0] r_state=IDLE, r_next=IDLE;
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reg signed [data_width-1: 0] r_data = 'b0;
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reg r_read_enable = 0;
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reg r_data_valid = 0;
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assign o_read_enable = r_read_enable;
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assign o_data_valid = r_data_valid;
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assign o_data = r_data;
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//---------state register sequential always block-----------
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always @(posedge clk ) begin
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if (reset == 1) begin
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// clear state
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r_state <= IDLE;
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r_next <= IDLE;
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end
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else begin
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r_state <= r_next;
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end
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end
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//----next state & outputs, combinational always block------
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always @(posedge clk ) begin
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case(r_state)
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IDLE : begin
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if (i_data_ready == 1) begin
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r_next <= OUTPUT;
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r_data <= i_data;
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r_read_enable <= 0;
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r_data_valid <= 0;
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end
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else begin
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r_next <= IDLE;
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r_read_enable <= 1; // redy to read data
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r_data_valid <= 0;
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end
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end
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OUTPUT : begin
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if (i_read_done == 1) begin
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r_next <= IDLE;
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r_data_valid <= 0;
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r_read_enable <= 1;
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end
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else begin
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r_next <= OUTPUT;
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r_data_valid <= 1;
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r_read_enable <= 0; // read disable
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end
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end
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default: r_next <= IDLE; // on error
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endcase
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end
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endmodule
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@@ -35,21 +35,28 @@ wire clk_25MHz; //
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wire w_reset, w_reset1, w_reset2, w_reset3,
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w_reset4, w_reset5;
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wire w_internal_reset;
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wire [d_width-1: 0] r_data_tx;
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wire [d_width-1: 0] l_data_tx;
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wire [d_width-1: 0] r_data_rx;
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wire [d_width-1: 0] l_data_rx;
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wire [d_width-1: 0] w_data_to_eff;
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wire w_dv_to_eff;
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wire [d_width-1: 0] w_data_from_eff;
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wire w_dv_from_eff;
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wire w_rd_en_from_eff;
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wire w_internal_reset;
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wire w_read_done_eff; // read done from effects module to mixer
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wire w_read_ready_eff; // ready to read from effects module
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// Data wires from effects module to effect controler
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wire [d_width-1: 0] w_data_from_eff_sw0;
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wire [d_width-1: 0] w_data_from_eff_sw1;
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//-----sub modules--------------------------
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@@ -129,18 +136,22 @@ effect_controler #(
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) effect_controler (
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.reset(w_reset), // asynchronous active high reset
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.mclk(master_clk),
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.sw(sw),
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.clk(clk_25MHz),
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.i_l_data(l_data_rx), // left channel data received
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.i_r_data(r_data_rx), // right channel data received
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.o_l_data(l_data_tx), // left channel data to transmit
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.o_r_data(r_data_tx), // right channel data to transmit
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.o_read_done(w_read_done_eff), // read done from effects controler
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.o_read_ready(w_read_ready_eff), // ready read from reefects module
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.o_data_to_eff(w_data_to_eff), // Data output to effects module
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.o_data_valid(w_dv_to_eff), // data valid to read (FIFO not empty). data valid signal to effect module
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.i_read_enable(w_rd_en_from_eff), // read enable from Effect module
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.i_data_from_eff(w_data_from_eff), // Data input from effects module
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.i_dv_from_eff(w_dv_from_eff) // data valid write (FIFO not full). data valid signal from effect module
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.i_dv_from_eff(w_dv_from_eff), // data valid write (FIFO not full). data valid signal from effect module
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.i_data_from_eff_sw0(w_data_from_eff_sw0), // Data input from effects module
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.i_data_from_eff_sw1(w_data_from_eff_sw1) // Data input from effects module
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);
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@@ -152,10 +163,12 @@ effect_module #(
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.reset(w_reset),
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.sw(sw), // effect control swiches
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.i_data_ready(w_dv_to_eff), // data ready to read
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.i_read_done(w_read_done_eff), // read done from effects controler
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.i_data(w_data_to_eff), // data input form effect controler
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.o_read_enable(w_rd_en_from_eff), // enable data reading
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.o_data(w_data_from_eff),
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.o_data_valid(w_dv_from_eff)
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.o_data_valid(w_dv_from_eff),
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.o_data_sw0(w_data_from_eff_sw0),
|
||||
.o_data_sw1(w_data_from_eff_sw1)
|
||||
|
||||
);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user