Changes to Matlab model

Add VGA module
Initial commit for new branch
2020-04-04 16:06:23 +03:00 · 2020-04-04 01:40:11 +03:00 · 2020-04-04 00:16:44 +03:00 · 2020-02-10 21:28:51 +02:00 · 2020-02-10 21:19:15 +02:00 · 2020-02-10 21:19:05 +02:00
42 changed files with 2235 additions and 730 deletions
@@ -14,102 +14,102 @@ set_property PACKAGE_PIN W5 [get_ports clk]


 ## Switches
-#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
-#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
-#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
-#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
-#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
-#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
-#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
-#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
-#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
-#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
-#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
-#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
-#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
-#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
-#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
-#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+set_property PACKAGE_PIN W17 [get_ports {sw[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
+set_property PACKAGE_PIN W15 [get_ports {sw[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
+set_property PACKAGE_PIN V15 [get_ports {sw[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
+set_property PACKAGE_PIN W14 [get_ports {sw[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
+set_property PACKAGE_PIN W13 [get_ports {sw[7]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
+set_property PACKAGE_PIN V2 [get_ports {sw[8]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
+set_property PACKAGE_PIN T3 [get_ports {sw[9]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
+set_property PACKAGE_PIN T2 [get_ports {sw[10]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
+set_property PACKAGE_PIN R3 [get_ports {sw[11]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
+set_property PACKAGE_PIN W2 [get_ports {sw[12]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
+set_property PACKAGE_PIN U1 [get_ports {sw[13]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
+set_property PACKAGE_PIN T1 [get_ports {sw[14]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
+set_property PACKAGE_PIN R2 [get_ports {sw[15]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
 

-## LEDs
-#set_property PACKAGE_PIN U16 [get_ports {led[0]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
-#set_property PACKAGE_PIN E19 [get_ports {led[1]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
-#set_property PACKAGE_PIN U19 [get_ports {led[2]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
-#set_property PACKAGE_PIN V19 [get_ports {led[3]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
-#set_property PACKAGE_PIN W18 [get_ports {led[4]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
-#set_property PACKAGE_PIN U15 [get_ports {led[5]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
-#set_property PACKAGE_PIN U14 [get_ports {led[6]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
-#set_property PACKAGE_PIN V14 [get_ports {led[7]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
-#set_property PACKAGE_PIN V13 [get_ports {led[8]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
-#set_property PACKAGE_PIN V3 [get_ports {led[9]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
-#set_property PACKAGE_PIN W3 [get_ports {led[10]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
-#set_property PACKAGE_PIN U3 [get_ports {led[11]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
-#set_property PACKAGE_PIN P3 [get_ports {led[12]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
-#set_property PACKAGE_PIN N3 [get_ports {led[13]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
-#set_property PACKAGE_PIN P1 [get_ports {led[14]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
-#set_property PACKAGE_PIN L1 [get_ports {led[15]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
+# LEDs
+set_property PACKAGE_PIN U16 [get_ports {led[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property PACKAGE_PIN E19 [get_ports {led[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property PACKAGE_PIN U19 [get_ports {led[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property PACKAGE_PIN V19 [get_ports {led[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+set_property PACKAGE_PIN W18 [get_ports {led[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
+set_property PACKAGE_PIN U15 [get_ports {led[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
+set_property PACKAGE_PIN U14 [get_ports {led[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
+set_property PACKAGE_PIN V14 [get_ports {led[7]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
+set_property PACKAGE_PIN V13 [get_ports {led[8]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
+set_property PACKAGE_PIN V3 [get_ports {led[9]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
+set_property PACKAGE_PIN W3 [get_ports {led[10]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
+set_property PACKAGE_PIN U3 [get_ports {led[11]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
+set_property PACKAGE_PIN P3 [get_ports {led[12]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
+set_property PACKAGE_PIN N3 [get_ports {led[13]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
+set_property PACKAGE_PIN P1 [get_ports {led[14]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
+set_property PACKAGE_PIN L1 [get_ports {led[15]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
 	
 	
-##7 segment display
-#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
-#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
-#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
-#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
-#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
-#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
-#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
+#7 segment display
+set_property PACKAGE_PIN W7 [get_ports {seg[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
+set_property PACKAGE_PIN W6 [get_ports {seg[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
+set_property PACKAGE_PIN U8 [get_ports {seg[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
+set_property PACKAGE_PIN V8 [get_ports {seg[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
+set_property PACKAGE_PIN U5 [get_ports {seg[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
+set_property PACKAGE_PIN V5 [get_ports {seg[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
+set_property PACKAGE_PIN U7 [get_ports {seg[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

-#set_property PACKAGE_PIN V7 [get_ports dp]							
-	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
+set_property PACKAGE_PIN V7 [get_ports dp]							
+	set_property IOSTANDARD LVCMOS33 [get_ports dp]

-#set_property PACKAGE_PIN U2 [get_ports {an[0]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
-#set_property PACKAGE_PIN U4 [get_ports {an[1]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
-#set_property PACKAGE_PIN V4 [get_ports {an[2]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
-#set_property PACKAGE_PIN W4 [get_ports {an[3]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
+set_property PACKAGE_PIN U2 [get_ports {an[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
+set_property PACKAGE_PIN U4 [get_ports {an[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
+set_property PACKAGE_PIN V4 [get_ports {an[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
+set_property PACKAGE_PIN W4 [get_ports {an[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]


 ##Buttons
@@ -237,35 +237,35 @@ set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]



-##VGA Connector
-#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
-#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
-#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
-#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
-#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
-#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
-#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
-#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
-#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
-#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
-#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
-#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
-#set_property PACKAGE_PIN P19 [get_ports Hsync]						
-	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
-#set_property PACKAGE_PIN R19 [get_ports Vsync]						
-	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
+#VGA Connector
+set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
+set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
+set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
+set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
+set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
+set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
+set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
+set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
+set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
+set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
+set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
+set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
+set_property PACKAGE_PIN P19 [get_ports Hsync]						
+	set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
+set_property PACKAGE_PIN R19 [get_ports Vsync]						
+	set_property IOSTANDARD LVCMOS33 [get_ports Vsync]


 ##USB-RS232 Interface
@@ -1,5 +1,21 @@
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - JXADC PMOD connector output
+//
+// Detailed module description:
 // This module outputs signals to JXADC PMOD
 // where logic analyzer are conected.
+// Port is connected to logic analizer
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////
+

 module JXADC_controler (
    input           ch0,
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2020 Imants Pulkstenis
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
@@ -1,14 +1,11 @@
-# Audio effects on FPGA
+[![MIT license](https://img.shields.io/badge/License-MIT-blue.svg?style=plastic)](https://lbesson.mit-license.org/)
+![GitHub commit activity](https://img.shields.io/github/commit-activity/m/clockfix/audio_effects_FPGA?style=plastic)
+![GitHub last commit](https://img.shields.io/github/last-commit/clockfix/audio_effects_FPGA?style=plastic)
+![GitHub contributors](https://img.shields.io/github/contributors/clockfix/audio_effects_FPGA?style=plastic)
+# Audio FFT on FPGA

-Audio effect synthesizer on FPGA
+Audio FFT on FPGA

 Audio hardware

 ![PMOD_I2S2](https://euborw.bl.files.1drv.com/y4mwscr7u3Q0WJKuOjfrLSFswmMhJFcQz_qvUDQmWPsWANUPPx3s-RrdHahplWN4MPxWtFJAZCzZokzS9oG3hJRHTa8-hztUF-5ix6DoEZ3FbW79HuWuWykaC6-vPQCz_jN-qtZzENmEM_CL7x6Fu-V3fVBwSbUUZ1B4FpyTJbHc2y09jmmIoznP9JKdHkloQC22fRvzkGEwn-uEL7m5GIYtg/pmod_i2s2.jpg) ![PMOD_I2S2_package](https://jhuenw.bl.files.1drv.com/y4mh-JRwzfInJGsB7npvB02QFP4E8O0fYseJrh7mCKZPhDtrRKAkyIU4vrSgIPZ57SPrRugP-CoS5pu-_W9fq1E2gV9SOYeyPc2In_a5uqQzCtwXbUYRvOQnHEt-zomphOLXn2Uw7RpaKbKLNvgQfF-pJNqbiX5LAaW5zODYNF66IESQ3uHqDSOCEtjt620oITZFzO71EyDkpSPB3bvZ61J6Q/pmod_i2s2_package.png)
-
-
-Top module
-![Top module_sh](https://sqtelw.bl.files.1drv.com/y4m3crragNjKRiiBnam_JQ72R1capMF7J4KFYmU9IC8ejan87w2KHOPl_SzV9Hyi6joKVl75qHteBc-DM81evlTdlBqJ8cgvCm6ISM2YxCEOrbJ7jEZR11jLt_6sS8Alucgz6lbZa-jescBHfFhU9g2CnuQqXTLzn9F3EoO2W4vQHQX8-6efsKfu73ZbmjWOWr9vgFpp42JJJO0DL6gPKsWxA/top-audio-effects.png?psid=1)
-
-i2s timing diagram
-![i2s timing diagram](https://jxuqnw.ch.files.1drv.com/y4m-dZeGZ7098LnxNfhcXYLc_boX5bUNKolrZoOikvJ15bhmx83OEfjXsL0DOx4bJQwo9Nj8JhPdbH3-p2_NsPtkQLQMjqqvHQD1aoTLU4iCGlzmuDkeRaJ4hOWEjlSxfPTpLuJmFxd3Co8m7PUNAHw-lSomMgNqrO4Sw_8E4K-vfiS2ijUOfIdlW4VUDLv0Dku1zcMel3jQGcMSIH0GiQyRA/i2s-loopback.png?psid=1)
@@ -0,0 +1,51 @@
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - Dual-Port Block RAM
+//
+// Detailed module description:
+// Code from: Vivado Design Suite User Guide Synthesis
+// UG901 (v2018.3) December 19, 2018
+//
+// Dual-Port Block RAM with Two Write Ports
+// File: blobkram.v 
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////
+
+module rams_tdp_rf_rf #( parameter
+    DEPTH =  16,
+    ADDR_WIDTH = 4, 
+    DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
+
+input                       clka,clkb,ena,enb,wea,web;
+input   [ADDR_WIDTH-1:0]    addra,addrb;
+input   [DATA_WIDTH-1:0]    dia,dib;
+output  [DATA_WIDTH-1:0]    doa,dob;
+reg     [DATA_WIDTH-1:0]    ram     [ DEPTH - 1 :0];
+reg     [DATA_WIDTH-1:0]    doa,dob;
+
+always @(posedge clka)
+begin
+    if (ena)
+    begin
+        if (wea)
+            ram[addra] <= dia;
+            doa <= ram[addra];
+        end
+    end
+always @(posedge clkb)
+begin
+    if (enb)
+    begin
+        if (web)
+            ram[addrb] <= dib;
+            dob <= ram[addrb];
+    end
+end
+endmodule
@@ -1,19 +1,32 @@
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - clock divider
+//
+// Detailed module description:
 // This module devide FPGA input clock 
 // by DIVIDER. Result is 50% duty cicle 
 // pulses.
 //
+// Revision:
+// A - initial design
+// B - 
+// C - 
 //
+///////////////////////////////////////////////////////////////////
+
 module clock_divider #(
-    parameter DIVIDER =2,
-    parameter WIDTH =2
+    parameter WIDTH =2,
+    parameter DIVIDER =(2**WIDTH)
 ) (
-    input clk,
+    input clk_in,
    output clk_out);

 reg state=1'b0, next_state=1'b1;
 reg [WIDTH-1:0] counter = DIVIDER-1 ; 

-always@(posedge clk)begin
+always@(posedge clk_in)begin
    state <= next_state;
    if ( counter == 0) begin
        next_state <= ~next_state;
@@ -1,40 +0,0 @@
-// `timescale [time unit] / [time precision]
-`timescale 10 ps / 1 ps
-
-`include "clock_divider_param.v"
-
-module clock_divider_param_tb ();
-
-reg clk = 1'b0;
-wire enable;
-
-always #1 clk <= ~clk; 
-
-  initial
-  begin
-    #100;
-    $finish();
-  end
-    
-  initial 
-  begin 
-    $display(" ");
-    $display("----------------------------------------------");
-    $display("          Starting Testbench...");
-    $dumpfile("wave.vcd");
-    $dumpvars(0);
-    $display("----------------------------------------------");
-    $display(" ");
-  end
-
-clock_divider #(
-    .DIVIDER(2),
-    .WIDTH(2)
-  ) test_unit1 (
-    .clk(clk),
-    .enable(enable)
-);
-
-
-
-endmodule
@@ -1,31 +0,0 @@
-// This module devide FPGA input clock 
-// by DIVIDER. 
-//
-//
-module clock_enable_param #(
-    parameter WAIT =1,
-    parameter WIDTH =1
-) (
-    input clk,
-    output enable);
-
-reg state=1'b0;
-reg [WIDTH-1:0] counter = 1'b0 ; 
-
-always@(posedge clk)begin  
-    if(counter == 0)begin
-      if (state == 1) begin
-        state <= 0;
-        counter <= WAIT - 1;
-      end
-      else begin
-        state <= 1;
-        counter <= 0;
-      end
-    end
-    else counter <= counter -1;
-end
-
-assign enable = state;
-
-endmodule
@@ -1,61 +0,0 @@
-`include "clock_enable_param.v"
-
-module clock_enable_tb();
-
-reg clk = 1'b0;
-wire enable0;
-wire enable1;
-wire enable2;
-wire enable3;
-
-always #1 clk <= ~clk; 
-
-  initial
-  begin
-    #100;
-    $finish();
-  end
-    
-  initial 
-  begin 
-    $display(" ");
-    $display("----------------------------------------------");
-    $display("          Starting Testbench...");
-    $dumpfile("wave.vcd");
-    $dumpvars(0);
-    $display("----------------------------------------------");
-    $display(" ");
-  end
-
-clock_enable_param test_unit0(
-    .clk(clk),
-    .enable(enable0)
-);
-
-clock_enable_param #(
-    .WAIT(2),
-    .WIDTH(4)
-   ) test_unit1(
-    .clk(clk),
-    .enable(enable1)
-);
-
-clock_enable_param #(
-    .WAIT(3),
-    .WIDTH(8)
-   )test_unit2(
-    .clk(clk),
-    .enable(enable2)
-);
-
-clock_enable_param #(
-    .WAIT(9),
-    .WIDTH(8)
-   )test_unit3(
-    .clk(clk),
-    .enable(enable3)
-);
-
-
-
-endmodule
@@ -0,0 +1,29 @@
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - Flip-Flop
+//
+// Detailed module description:
+// Simple Flip-Flop
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////
+module d_flipflop_sync_rst(
+    input       D,
+    output  reg Q,
+    input       clk,
+    input       reset);
+
+always@(posedge clk, posedge reset)
+begin
+    if(reset)
+        Q <= 1'd0;
+    else
+        Q <= D;     
+end
+endmodule
@@ -1,4 +1,20 @@
-module debounce_switch(
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - Debounce switch
+//
+// Detailed module description:
+// This is Debounce switch module.
+// It toggles output only when input is in 
+// HIGH or LOW state atleast for 10ms 
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////module debounce_switch(
    input clk,
    input i_switch,
    output o_switch);
@@ -1,6 +1,19 @@
-// This file is Test Bench for top_vga_mem module
-//  
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - Test Bench for debounce switch
+//
+// Detailed module description:
+// This file is Test Bench for debounce switch module
 // 
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////

 // 100MHz clock on Basys3 -> 10ns period
 // 50% duty cycle 5ns HIGH and 5ns LOW
@@ -1,23 +0,0 @@
-module effect_controler #( parameter
-    d_width = 24                // data width
-)(
-//    input clk,
-    input signed [d_width-1: 0] i_l_data,
-    input signed  [d_width-1: 0] i_r_data,
-    output reg signed [d_width-1: 0] o_l_data,
-    output  reg signed [d_width-1: 0] o_r_data
-);
-
-always@* begin
-    o_l_data <= i_l_data;
-    o_r_data <= i_r_data;
-end
-
-//assign o_l_data = i_l_data;
-//assign o_r_data = i_r_data;
-
-
-//assign o_l_data = 24'h000000;
-//assign o_r_data = 24'h400008;
-
-endmodule
@@ -0,0 +1,89 @@
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - horizontal counter
+//
+// Detailed module description:
+//
+// 
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////
+module horizontal_counter #( 
+    parameter
+        HSYNC_CLKS = 800,
+        HSYNC_DISPLAY = 640,
+        HSYNC_PULSE = 96,
+        HSYNC_FRONT_PORCH = 16,
+        HSYNC_BACK_PORCH = 48
+    )(
+        input clk,
+        output o_Hsync,
+        output o_h_display,
+        output [9:0] o_h_pixel
+        );
+//----------Internal registers, constants and wariables-----
+reg hsync_reg = 1'b1;
+reg [9:0] counter_reg = 'h0;
+reg [9:0] counter_pixel_reg = 'h0;
+reg [2:0] r_state=HS_FRONT_PORCH, r_next=HS_FRONT_PORCH;
+localparam [2:0]        HS_FRONT_PORCH  = 'h0,
+                        HS_PULSE        = 'h1,
+                        HS_BACK_PORCH   = 'h2,
+                        HS_DISPLAY      = 'h3;
+
+//---------state register sequential always block-----------
+always @(posedge clk ) begin
+        r_state <= r_next; 
+end
+//----next state & outputs, combinational always block------
+
+
+always@(posedge clk) begin
+  counter_reg <= counter_reg + 1;
+
+    case (r_state)
+      HS_FRONT_PORCH: begin
+        hsync_reg <= 1'b1;
+        if(counter_reg ==   HSYNC_FRONT_PORCH - 2)
+            r_next <= HS_PULSE;
+      end
+      HS_PULSE:begin
+        hsync_reg <= 1'b0;
+        if(counter_reg ==   HSYNC_FRONT_PORCH +
+                            HSYNC_PULSE - 2)
+            r_next <= HS_BACK_PORCH;
+      end
+      HS_BACK_PORCH:begin
+        hsync_reg <= 1'b1;
+        if(counter_reg ==   HSYNC_FRONT_PORCH +
+                            HSYNC_PULSE +
+                            HSYNC_BACK_PORCH - 2) begin
+            r_next <= HS_DISPLAY;
+            counter_pixel_reg <= 'h0;
+            end
+      end
+      HS_DISPLAY:begin
+        hsync_reg <= 1'b1;
+        counter_pixel_reg <= counter_pixel_reg + 1;
+        if(counter_reg ==   HSYNC_FRONT_PORCH +
+                            HSYNC_PULSE +
+                            HSYNC_BACK_PORCH +
+                            HSYNC_DISPLAY - 1) begin
+            r_next <= HS_FRONT_PORCH;
+            counter_reg <= 'h0;
+        end
+      end
+    endcase
+end
+
+assign o_Hsync = hsync_reg;
+assign o_h_display = (counter_pixel_reg >= 1 && counter_pixel_reg <= HSYNC_DISPLAY) ? 1'b1 : 1'b0 ;
+assign o_h_pixel = counter_pixel_reg - 1 ;
+
+endmodule
@@ -1,4 +1,11 @@
-// This I2S Playback design uses the common 44.1 kHz 
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - i2s receiver
+//
+// Detailed module description:
+// This I2S design uses the common 44.1 kHz 
 // sampling frequency.  
 // From Figure 2 in Section 4.1.1 of the CS5343 
 // Datasheet, it is appropriate to use an SCLK/LRCK 
@@ -19,8 +26,14 @@
 //
 //  Module is created from sample provided by 
 //  Digilent
+// 
 //
-
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////

 module i2s_receicer #( parameter
    sclk_ws_ratio = 64,         // number of sclk periods per word select period
@@ -1,4 +1,11 @@
-// This I2S Playback design uses the common 44.1 kHz 
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - i2s sender
+//
+// Detailed module description:
+// This I2S design uses the common 44.1 kHz 
 // sampling frequency.  
 // From Figure 2 in Section 4.1.1 of the CS5343 
 // Datasheet, it is appropriate to use an SCLK/LRCK 
@@ -19,7 +26,14 @@
 //
 //  Module is created from sample provided by 
 //  Digilent
+// 
 //
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////


 module i2s_sender #( parameter
@@ -0,0 +1,83 @@
+module io_module #( parameter
+    sclk_ws_ratio = 64,         // number of sclk periods per word select period
+    mclk_sclk_ratio = 4,        // number of mclk periods per sclk period
+    d_width = 24                // data width
+)(
+    //output reset,                             //asynchronous active low reset
+    input  mclk,                                //master clock
+    output ad_sclk,                             //serial clock (or bit clock)
+    output ad_ws,                               //word select (or left-right clock)
+    output da_sclk,                             //serial clock (or bit clock)
+    output da_ws,                               //word select (or left-right clock)
+    output sd_tx,                               //serial data transmit
+    input  sd_rx,                               //serial data receive
+
+    input signed [d_width-1: 0] l_data_tx,      //left channel data to transmit
+    input signed [d_width-1: 0] r_data_tx,      //right channel data to transmit
+
+    output signed [d_width-1: 0] l_data_rx,            //left channel data received
+    output signed [d_width-1: 0] r_data_rx,             //right channel data received   
+
+    input reset,
+    
+    // inputs to logic analyzer
+    input           ch0,
+    input           ch1,
+    input           ch2,
+    input           ch3,
+    input           ch4,
+    input           ch5,
+    input           ch6,
+    input           ch7,
+
+    output  [7: 0]  JXADC      // output for logic analizer
+
+    );
+
+
+
+i2s_sender  #(
+    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
+    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
+    .d_width(d_width)                       //data width
+) i2s_sender (
+    .reset_n(reset),        //asynchronous active high reset
+    .mclk(mclk),            //master clock
+    .sclk(da_sclk),         //serial clock (or bit clock)
+    .ws(da_ws),             //word select (or left-right clock)
+    .sd_tx(sd_tx),          //serial data transmit
+    .l_data_tx(l_data_tx),  //left channel data to transmit
+    .r_data_tx(r_data_tx)   //right channel data to transmit
+);
+
+
+
+i2s_receicer  #(
+    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
+    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
+    .d_width(d_width)                       //data width
+) i2s_receicer (
+    .reset_n(reset),            //asynchronous active high reset
+    .mclk(mclk),                //master clock
+    .sclk(ad_sclk),             //serial clock (or bit clock)
+    .ws(ad_ws),                 //word select (or left-right clock)
+    .sd_rx(sd_rx),              //serial data receive
+    .l_data_rx(l_data_rx),      //left channel data received
+    .r_data_rx(r_data_rx)       //right channel data received
+);
+
+
+// connecting signals to JXADC PMOD to monitor them with signal analyzer
+JXADC_controler JXADC_controler(
+    .ch0(ch0),
+    .ch1(ch1),
+    .ch2(ch2),
+    .ch3(ch3),        // serial data in
+    .ch4(ch4),
+    .ch5(ch5),
+    .ch6(ch6),
+    .ch7(ch7),        // serial data out
+    .JXADC(JXADC)       // output for logic analizer   
+);
+
+endmodule
@@ -1,23 +0,0 @@
-dt  =   0.01;  
-T  =   1; 
-t  =   [0:dt:T]' ;  
-omega0  =   2 *   pi  /T; 
-N  =    length  (t); 
-N2  =    round  (N/2); 
-x  =   ones(N, 1); 
-x (N2 + 1:N)  =  -1 * ones(N  - N2, 1);
-a(1)  =   1/T *  ( sum  (x) *  dt); 
-xfs  =   a(1) *  ones( size(x)); 
-for   k  =   1:10                
-    ck  =    cos  (k *  omega0 *  t); %  cosine component                   
-    a(k  +   1)  =   2/T *  ( sum  (x.*  ck) *  dt); 
-    sk  =    sin  (k *  omega0 *  t);   %  sine component                   
-    b(k  +   1)  =   2/T *  ( sum  (x.*  sk) *  dt); 
-    
-    %  Fourier series approximation
-    xfs  =   xfs +  a(k +  1) * cos  (k * omega0 *  t) + b(k +  1) * sin  (k *  omega0 *  t); 
-    plot  (t, x,  '-' , t, xfs,  ':' );                 
-    legend  ( ' desired ' ,  ' approximated ' ); 
-    drawnow  ;  
-    pause  (1);   
-end    
@@ -0,0 +1,659 @@
+
+<!DOCTYPE html
+  PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head>
+      <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+   <!--
+This HTML was auto-generated from MATLAB code.
+To make changes, update the MATLAB code and republish this document.
+      --><title>myfft3</title><meta name="generator" content="MATLAB 9.3"><link rel="schema.DC" href="http://purl.org/dc/elements/1.1/"><meta name="DC.date" content="2019-12-27"><meta name="DC.source" content="myfft3.m"><style type="text/css">
+html,body,div,span,applet,object,iframe,h1,h2,h3,h4,h5,h6,p,blockquote,pre,a,abbr,acronym,address,big,cite,code,del,dfn,em,font,img,ins,kbd,q,s,samp,small,strike,strong,sub,sup,tt,var,b,u,i,center,dl,dt,dd,ol,ul,li,fieldset,form,label,legend,table,caption,tbody,tfoot,thead,tr,th,td{margin:0;padding:0;border:0;outline:0;font-size:100%;vertical-align:baseline;background:transparent}body{line-height:1}ol,ul{list-style:none}blockquote,q{quotes:none}blockquote:before,blockquote:after,q:before,q:after{content:'';content:none}:focus{outine:0}ins{text-decoration:none}del{text-decoration:line-through}table{border-collapse:collapse;border-spacing:0}
+
+html { min-height:100%; margin-bottom:1px; }
+html body { height:100%; margin:0px; font-family:Arial, Helvetica, sans-serif; font-size:10px; color:#000; line-height:140%; background:#fff none; overflow-y:scroll; }
+html body td { vertical-align:top; text-align:left; }
+
+h1 { padding:0px; margin:0px 0px 25px; font-family:Arial, Helvetica, sans-serif; font-size:1.5em; color:#d55000; line-height:100%; font-weight:normal; }
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+h3 { padding:0px; margin:0px 0px 5px; font-family:Arial, Helvetica, sans-serif; font-size:1.1em; color:#000; font-weight:bold; line-height:140%; }
+
+a { color:#005fce; text-decoration:none; }
+a:hover { color:#005fce; text-decoration:underline; }
+a:visited { color:#004aa0; text-decoration:none; }
+
+p { padding:0px; margin:0px 0px 20px; }
+img { padding:0px; margin:0px 0px 20px; border:none; }
+p img, pre img, tt img, li img, h1 img, h2 img { margin-bottom:0px; } 
+
+ul { padding:0px; margin:0px 0px 20px 23px; list-style:square; }
+ul li { padding:0px; margin:0px 0px 7px 0px; }
+ul li ul { padding:5px 0px 0px; margin:0px 0px 7px 23px; }
+ul li ol li { list-style:decimal; }
+ol { padding:0px; margin:0px 0px 20px 0px; list-style:decimal; }
+ol li { padding:0px; margin:0px 0px 7px 23px; list-style-type:decimal; }
+ol li ol { padding:5px 0px 0px; margin:0px 0px 7px 0px; }
+ol li ol li { list-style-type:lower-alpha; }
+ol li ul { padding-top:7px; }
+ol li ul li { list-style:square; }
+
+.content { font-size:1.2em; line-height:140%; padding: 20px; }
+
+pre, code { font-size:12px; }
+tt { font-size: 1.2em; }
+pre { margin:0px 0px 20px; }
+pre.codeinput { padding:10px; border:1px solid #d3d3d3; background:#f7f7f7; }
+pre.codeoutput { padding:10px 11px; margin:0px 0px 20px; color:#4c4c4c; }
+pre.error { color:red; }
+
+@media print { pre.codeinput, pre.codeoutput { word-wrap:break-word; width:100%; } }
+
+span.keyword { color:#0000FF }
+span.comment { color:#228B22 }
+span.string { color:#A020F0 }
+span.untermstring { color:#B20000 }
+span.syscmd { color:#B28C00 }
+
+.footer { width:auto; padding:10px 0px; margin:25px 0px 0px; border-top:1px dotted #878787; font-size:0.8em; line-height:140%; font-style:italic; color:#878787; text-align:left; float:none; }
+.footer p { margin:0px; }
+.footer a { color:#878787; }
+.footer a:hover { color:#878787; text-decoration:underline; }
+.footer a:visited { color:#878787; }
+
+table th { padding:7px 5px; text-align:left; vertical-align:middle; border: 1px solid #d6d4d4; font-weight:bold; }
+table td { padding:7px 5px; text-align:left; vertical-align:top; border:1px solid #d6d4d4; }
+
+
+
+
+
+  </style></head><body><div class="content"><h2>Contents</h2><div><ul><li><a href="#1">FFT algoritm</a></li><li><a href="#2">Data preparation for FFT</a></li><li><a href="#3">First stage</a></li><li><a href="#4">Second stage</a></li><li><a href="#5">Therd stage</a></li><li><a href="#6">4th stage</a></li><li><a href="#7">5th stage</a></li><li><a href="#8">Ploting out</a></li></ul></div><h2 id="1">FFT algoritm</h2><pre class="codeinput">clear;                      <span class="comment">% clears all previus values from memory</span>
+clc;                        <span class="comment">% clear command window</span>
+fs =  44100;                <span class="comment">% samplinf freq.</span>
+fftLength=32;               <span class="comment">% windowlength</span>
+
+<span class="comment">% signal frequencies</span>
+data_length = 8;           <span class="comment">% data length in FPGA calculations</span>
+max = 2^(data_length-1) - 1 ;            <span class="comment">% max aplitude 2^n  /2</span>
+
+f1 = 1000;
+a1 = max/2;
+
+f2 = 0;
+a2 = max/4;
+
+f3 = 8000;
+a3 = max/2;
+
+<span class="comment">% calculating signals</span>
+comp1 = a1 * cos(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * cos(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * cos(2*pi*f3*[0:1/fs:1]);
+
+<span class="comment">% calculatin vector values for step function</span>
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+<span class="comment">%data = [ d1 , d2];                  % creates vector with step function</span>
+data = comp1 + comp2 + comp3;      <span class="comment">% creates vector from 3 sin functions</span>
+
+figure(1)               <span class="comment">% plots separete sin functions</span>
+plot ( comp1, <span class="string">'-'</span>);
+hold <span class="string">on</span>;
+plot ( comp2, <span class="string">'-'</span>);
+plot ( comp3, <span class="string">'-'</span>);
+xlim([1 50])
+title(<span class="string">'Separete SIN functions'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'time'</span>)
+hold <span class="string">off</span>;
+
+figure(2)               <span class="comment">% plots signal for fft</span>
+plot ( data);
+title(<span class="string">'Signal for FFT analysis FFT'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'time'</span>)
+xlim([1 100])
+
+figure(3)               <span class="comment">% plots resultinf fft from Matlab functions</span>
+ft =fft(data,fftLength);
+ftMag=abs(ft(1:fftLength/2));
+stem (ftMag)
+title(<span class="string">'Linear Magnitude FFT'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'kHz'</span>)
+
+xt = xticks;        <span class="comment">% returns the current x-axis tick values as a vector</span>
+fstep = fs/fftLength;       <span class="comment">% tick of f axis in f domain</span>
+xtnew = round((xt-1)*fstep/1000, 1) ;   <span class="comment">% calculate new tick in kHz</span>
+xticklabels(xtnew)      <span class="comment">% set new tick labels</span>
+
+<span class="comment">% figure(4)               % plots resultinf fft(in dB)  from Matlab functions</span>
+<span class="comment">% ft =fft(data,fftLength);</span>
+<span class="comment">% ftMag=abs(ft(1:fftLength/2));</span>
+<span class="comment">% plot (20*log10(ftMag))</span>
+<span class="comment">% title('dB Magnitude')</span>
+<span class="comment">% ylabel('dB'), xlabel('kHz')</span>
+<span class="comment">%</span>
+<span class="comment">% xt = xticks;        % returns the current x-axis tick values as a vector</span>
+<span class="comment">% fstep = fs/fftLength;       % tick of f axis in f domain</span>
+<span class="comment">% xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz</span>
+<span class="comment">% xticklabels(xtnew)      % set new tick labels</span>
+</pre><img vspace="5" hspace="5" src="myfft3_01.png" alt=""> <img vspace="5" hspace="5" src="myfft3_02.png" alt=""> <img vspace="5" hspace="5" src="myfft3_03.png" alt=""> <h2 id="2">Data preparation for FFT</h2><pre class="codeinput"><span class="comment">% reverse bit calulation</span>
+bits = length(dec2bin( fftLength - 1 ));    <span class="comment">% how many bits in binary number</span>
+rev_bit_dec = zeros(1,fftLength);           <span class="comment">% create vektor size of fftlength</span>
+
+<span class="keyword">for</span> n=1:fftLength
+    bin_num = dec2bin(n-1 , bits);          <span class="comment">% converting to binary number</span>
+    rev_bit = [];                           <span class="comment">% create empty vector</span>
+    <span class="keyword">for</span> k=bits:-1:1
+       rev_bit = [rev_bit , bin_num(k)];
+    <span class="keyword">end</span>
+    rev_bit_dec(n) = bin2dec(rev_bit) ;     <span class="comment">% add 1 to match Matlab numbering</span>
+<span class="keyword">end</span>
+
+<span class="comment">%  creating array</span>
+<span class="comment">%  create empty array to store values in reverse bit order</span>
+stage = zeros(bits + 1,fftLength);
+
+<span class="keyword">for</span> n=1:fftLength
+     stage(1,n)  =  data(rev_bit_dec(n)+1);
+<span class="keyword">end</span>
+
+<span class="comment">% Calculating W twiddling factor for all stages</span>
+<span class="keyword">for</span> n = 1 : fftLength/2
+    W(n)  = exp(-1i * (n-1) * 2 * pi/ fftLength );
+<span class="keyword">end</span>
+
+<span class="comment">% convert to fixed point mumber -&gt; sfi(v,w,f) returns a signed fixed-point object with value v, word length w, and fraction length f.</span>
+Wr = sfi(real(W),data_length,data_length-2);
+Wi = sfi(imag(W),data_length,data_length-2);
+
+st_real = sfi(real(stage) , data_length + 3 , 0);
+st_imag = sfi(imag(stage) , data_length + 3 , 0);
+<span class="comment">% temp values for multiplaying with W twiddling factor</span>
+st_real_tmp = sfi(real(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+st_imag_tmp = sfi(imag(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+</pre><h2 id="3">First stage</h2><pre class="codeinput"><span class="keyword">for</span> n = 1 : 2^1 : fftLength
+    <span class="comment">% Even</span>
+    stage(2,n)    = stage(1,n) + stage(1,n+1);
+    <span class="comment">% Odd</span>
+    stage(2,n+1)  = stage(1,n) - stage(1,n+1);
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^1 : fftLength
+    <span class="comment">% Even</span>
+    st_real(2,n)    = st_real(1,n) + st_real(1,n+1);
+    <span class="comment">% imag is 0</span>
+    <span class="comment">% Odd</span>
+    st_real(2,n+1)  = st_real(1,n) - st_real(1,n+1);
+    <span class="comment">% imag is 0</span>
+<span class="keyword">end</span>
+</pre><h2 id="4">Second stage</h2><pre class="codeinput"><span class="comment">% Calculating W twiddling factor</span>
+<span class="keyword">for</span> n = 1 : 2
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 4 );
+<span class="keyword">end</span>
+
+<span class="comment">% calculate next stage values</span>
+<span class="keyword">for</span> n = 1 : 2^2 : fftLength
+    <span class="comment">% Even pair</span>
+        stage(3,n+0)   = stage(2,n+0) + Wn(1)*stage(2,n+2);
+        stage(3,n+1)   = stage(2,n+1) + Wn(2)*stage(2,n+3);
+    <span class="comment">% Odd par</span>
+        stage(3,n+2)   = stage(2,n+0) - Wn(1)*stage(2,n+2);
+        stage(3,n+3)   = stage(2,n+1) - Wn(2)*stage(2,n+3);
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^2 : fftLength
+    <span class="comment">% Even pair</span>
+        st_real(3,n+0)   = st_real(2,n+0) + st_real(2,n+2);
+        <span class="comment">% imag is 0</span>
+        st_real(3,n+1)   = st_real(2,n+1) ;         <span class="comment">% real is 0</span>
+        st_imag(3,n+1)   = -1 * st_real(2,n+3);     <span class="comment">% mult -j</span>
+    <span class="comment">% Odd par</span>
+        st_real(3,n+2)   = st_real(2,n+0) - st_real(2,n+2);
+        <span class="comment">% imag is 0</span>
+        st_real(3,n+3)   = st_real(2,n+1) ;         <span class="comment">% real is 0</span>
+        st_imag(3,n+3)   = st_real(2,n+3);          <span class="comment">% mult -j</span>
+<span class="keyword">end</span>
+</pre><h2 id="5">Therd stage</h2><pre class="codeinput"><span class="comment">% Calculating W twiddling factor</span>
+<span class="keyword">for</span> n = 1 : 4
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 8 );
+<span class="keyword">end</span>
+
+<span class="comment">% calculate next stage values</span>
+<span class="keyword">for</span> n = 1 : 2^3 : fftLength
+    <span class="keyword">for</span> k = 0 : 3
+        <span class="comment">% Even pair</span>
+        stage(4,n+k)   = stage(3,n+k) + Wn(k+1)*stage(3,n+k+4);
+        <span class="comment">% Odd par</span>
+        stage(4,n+k+4) = stage(3,n+k) - Wn(k+1)*stage(3,n+k+4);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^3 : fftLength
+    <span class="keyword">for</span> k = 0 : 3
+        st_real_tmp(3,n+k+4) = ( Wr(k*4+1) * st_real(3,n+k+4) ) - (  Wi(k*4+1) * st_imag(3,n+k+4) );
+        st_imag_tmp(3,n+k+4) = ( Wi(k*4+1) * st_real(3,n+k+4) ) + (  Wr(k*4+1) * st_imag(3,n+k+4) );
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+<span class="keyword">for</span> n = 1 : 2^3 : fftLength
+    <span class="keyword">for</span> k = 0 : 3
+        <span class="comment">% Even pair</span>
+        st_real(4,n+k)   = st_real(3,n+k) + st_real_tmp(3,n+k+4);
+        st_imag(4,n+k)   = st_imag(3,n+k) + st_imag_tmp(3,n+k+4);
+        <span class="comment">% Odd par</span>
+        st_real(4,n+k+4) = st_real(3,n+k) - st_real_tmp(3,n+k+4);
+        st_imag(4,n+k+4) = st_imag(3,n+k) - st_imag_tmp(3,n+k+4);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+</pre><h2 id="6">4th stage</h2><pre class="codeinput"><span class="comment">% Calculating W twiddling factor</span>
+<span class="keyword">for</span> n = 1 : 8
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 16 );
+<span class="keyword">end</span>
+
+<span class="comment">% calculate next stage values</span>
+<span class="keyword">for</span> n = 1 : 2^4 : fftLength
+    <span class="keyword">for</span> k = 0 : 7
+        <span class="comment">% Even pair</span>
+        stage(5,n+k)    = stage(4,n+k) + Wn(k+1)*stage(4,n+k+8);
+        <span class="comment">% Odd par</span>
+        stage(5,n+k+8)  = stage(4,n+k) - Wn(k+1)*stage(4,n+k+8);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^4 : fftLength
+    <span class="keyword">for</span> k = 0 : 7
+         st_real_tmp(4,n+k+8) = ( Wr(k*2+1) * st_real(4,n+k+8) ) - (  Wi(k*2+1) * st_imag(4,n+k+8) );
+         st_imag_tmp(4,n+k+8) = ( Wi(k*2+1) * st_real(4,n+k+8) ) + (  Wr(k*2+1) * st_imag(4,n+k+8) );
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+<span class="keyword">for</span> n = 1 : 2^4 : fftLength
+    <span class="keyword">for</span> k = 0 : 7
+        <span class="comment">% Even pair</span>
+        st_real(5,n+k)    = st_real(4,n+k) + st_real_tmp(4,n+k+8);
+        st_imag(5,n+k)    = st_imag(4,n+k) + st_imag_tmp(4,n+k+8);
+        <span class="comment">% Odd par</span>
+        st_real(5,n+k+8)  = st_real(4,n+k) - st_real_tmp(4,n+k+8);
+        st_imag(5,n+k+8)  = st_imag(4,n+k) - st_imag_tmp(4,n+k+8);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+</pre><h2 id="7">5th stage</h2><pre class="codeinput"><span class="comment">% Calculating W twiddling factor</span>
+<span class="keyword">for</span> n = 1 : 16
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 32 );
+<span class="keyword">end</span>
+
+<span class="comment">% calculate next stage values</span>
+<span class="keyword">for</span> n = 1 : 2^5 : fftLength
+    <span class="keyword">for</span> k = 0 : 15
+        <span class="comment">% Even pair</span>
+        stage(6,n+k)    = stage(5,n+k) + Wn(k+1)*stage(5,n+k+16);
+        <span class="comment">% Odd par</span>
+        stage(6,n+k+16)  = stage(5,n+k) - Wn(k+1)*stage(5,n+k+16);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+
+<span class="comment">% calculations using separate real and imaginary numbers</span>
+<span class="keyword">for</span> n = 1 : 2^5 : fftLength
+    <span class="keyword">for</span> k = 0 : 15
+         st_real_tmp(5,n+k+16) = ( Wr(k*1+1) * st_real(5,n+k+16) ) - (  Wi(k*1+1) * st_imag(5,n+k+16) );
+         st_imag_tmp(5,n+k+16) = ( Wi(k*1+1) * st_real(5,n+k+16) ) + (  Wr(k*1+1) * st_imag(5,n+k+16) );
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+<span class="keyword">for</span> n = 1 : 2^5 : fftLength
+    <span class="keyword">for</span> k = 0 : 15
+        <span class="comment">% Even pair</span>
+        st_real(6,n+k)    = st_real(5,n+k) + st_real_tmp(5,n+k+16);
+        st_imag(6,n+k)    = st_imag(5,n+k) + st_imag_tmp(5,n+k+16);
+        <span class="comment">% Odd par</span>
+        st_real(6,n+k+16)  = st_real(5,n+k) - st_real_tmp(5,n+k+16);
+        st_imag(6,n+k+16)  = st_imag(5,n+k) - st_imag_tmp(5,n+k+16);
+    <span class="keyword">end</span>
+<span class="keyword">end</span>
+</pre><h2 id="8">Ploting out</h2><p>slowly plot result</p><pre class="codeinput">figure(5)
+<span class="keyword">for</span> n = 1 : bits +1
+    <span class="comment">%plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );</span>
+    stem( abs( stage(n,1:fftLength/2) ) );
+<span class="comment">%     pause(1);</span>
+<span class="keyword">end</span>
+xt = xticks;        <span class="comment">% returns the current x-axis tick values as a vector</span>
+fstep = fs/fftLength;       <span class="comment">% tick of f axis in f domain</span>
+xtnew = round((xt-1)*fstep/1000, 1) ;   <span class="comment">% calculate new tick in kHz</span>
+xticklabels(xtnew)      <span class="comment">% set new tick labels</span>
+title(<span class="string">'FFT using custom function'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'kHz'</span>)
+
+figure(6)
+<span class="keyword">for</span> n = 1 : bits +1
+    <span class="comment">%plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );</span>
+    temp = st_real + 1i * st_imag;
+    stem( abs( temp(n,1:fftLength/2) ) );
+<span class="comment">%      pause(1);</span>
+<span class="keyword">end</span>
+xt = xticks;        <span class="comment">% returns the current x-axis tick values as a vector</span>
+fstep = fs/fftLength;       <span class="comment">% tick of f axis in f domain</span>
+xtnew = round((xt-1)*fstep/1000, 1) ;   <span class="comment">% calculate new tick in kHz</span>
+xticklabels(xtnew)      <span class="comment">% set new tick labels</span>
+title(<span class="string">'FFT using custom function real/imag separate'</span>)
+ylabel(<span class="string">'magnitude'</span>), xlabel(<span class="string">'kHz'</span>)
+
+figure(7)
+dif2 = 100* abs(temp(bits +1,1:fftLength/2) - ft(1:fftLength/2))./abs(ft(1:fftLength/2)) ;
+plot(dif2, <span class="string">'blue'</span>)
+title(<span class="string">'Difference in calculations'</span>)
+xt = xticks;        <span class="comment">% returns the current x-axis tick values as a vector</span>
+fstep = fs/fftLength;       <span class="comment">% tick of f axis in f domain</span>
+xtnew = round((xt-1)*fstep/1000, 1) ;   <span class="comment">% calculate new tick in kHz</span>
+xticklabels(xtnew)      <span class="comment">% set new tick labels</span>
+ylabel(<span class="string">'percents, %'</span>), xlabel(<span class="string">'kHz'</span>)
+</pre><img vspace="5" hspace="5" src="myfft3_04.png" alt=""> <img vspace="5" hspace="5" src="myfft3_05.png" alt=""> <img vspace="5" hspace="5" src="myfft3_06.png" alt=""> <p class="footer"><br><a href="http://www.mathworks.com/products/matlab/">Published with MATLAB&reg; R2017b</a><br></p></div><!--
+##### SOURCE BEGIN #####
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=32;               % windowlength 
+
+% signal frequencies
+data_length = 8;           % data length in FPGA calculations 
+max = 2^(data_length-1) - 1 ;            % max aplitude 2^n  /2 
+
+f1 = 1000;
+a1 = max/2;
+
+f2 = 0;
+a2 = max/4;
+
+f3 = 8000;
+a3 = max/2;
+
+% calculating signals 
+comp1 = a1 * cos(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * cos(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * cos(2*pi*f3*[0:1/fs:1]);
+
+% calculatin vector values for step function
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+%data = [ d1 , d2];                  % creates vector with step function
+data = comp1 + comp2 + comp3;      % creates vector from 3 sin functions
+
+figure(1)               % plots separete sin functions
+plot ( comp1, '-');
+hold on;
+plot ( comp2, '-');
+plot ( comp3, '-');
+xlim([1 50])
+title('Separete SIN functions') 
+ylabel('magnitude'), xlabel('time') 
+hold off;
+
+figure(2)               % plots signal for fft
+plot ( data);
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+xlim([1 100])
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft =fft(data,fftLength); 
+ftMag=abs(ft(1:fftLength/2)); 
+stem (ftMag)
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
+
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+
+% figure(4)               % plots resultinf fft(in dB)  from Matlab functions
+% ft =fft(data,fftLength); 
+% ftMag=abs(ft(1:fftLength/2)); 
+% plot (20*log10(ftMag))
+% title('dB Magnitude') 
+% ylabel('dB'), xlabel('kHz') 
+% 
+% xt = xticks;        % returns the current x-axis tick values as a vector
+% fstep = fs/fftLength;       % tick of f axis in f domain 
+% xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+% xticklabels(xtnew)      % set new tick labels
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);           % create vektor size of fftlength
+
+for n=1:fftLength
+    bin_num = dec2bin(n-1 , bits);          % converting to binary number
+    rev_bit = [];                           % create empty vector
+    for k=bits:-1:1
+       rev_bit = [rev_bit , bin_num(k)];
+    end
+    rev_bit_dec(n) = bin2dec(rev_bit) ;     % add 1 to match Matlab numbering   
+end
+
+%  creating array
+%  create empty array to store values in reverse bit order
+stage = zeros(bits + 1,fftLength);
+
+for n=1:fftLength
+     stage(1,n)  =  data(rev_bit_dec(n)+1);
+end
+
+% Calculating W twiddling factor for all stages 
+for n = 1 : fftLength/2 
+    W(n)  = exp(-1i * (n-1) * 2 * pi/ fftLength );
+end
+
+% convert to fixed point mumber -> sfi(v,w,f) returns a signed fixed-point object with value v, word length w, and fraction length f.
+Wr = sfi(real(W),data_length,data_length-2);       
+Wi = sfi(imag(W),data_length,data_length-2);
+
+st_real = sfi(real(stage) , data_length + 3 , 0);
+st_imag = sfi(imag(stage) , data_length + 3 , 0);
+% temp values for multiplaying with W twiddling factor
+st_real_tmp = sfi(real(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+st_imag_tmp = sfi(imag(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+
+%% First stage
+
+for n = 1 : 2^1 : fftLength 
+    % Even
+    stage(2,n)    = stage(1,n) + stage(1,n+1);
+    % Odd
+    stage(2,n+1)  = stage(1,n) - stage(1,n+1);
+end
+
+% calculations using separate real and imaginary numbers 
+for n = 1 : 2^1 : fftLength 
+    % Even
+    st_real(2,n)    = st_real(1,n) + st_real(1,n+1);
+    % imag is 0
+    % Odd
+    st_real(2,n+1)  = st_real(1,n) - st_real(1,n+1);
+    % imag is 0
+end
+
+%% Second stage
+
+% Calculating W twiddling factor 
+for n = 1 : 2 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 4 );
+end
+
+% calculate next stage values
+for n = 1 : 2^2 : fftLength 
+    % Even pair
+        stage(3,n+0)   = stage(2,n+0) + Wn(1)*stage(2,n+2); 
+        stage(3,n+1)   = stage(2,n+1) + Wn(2)*stage(2,n+3); 
+    % Odd par
+        stage(3,n+2)   = stage(2,n+0) - Wn(1)*stage(2,n+2); 
+        stage(3,n+3)   = stage(2,n+1) - Wn(2)*stage(2,n+3); 
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^2 : fftLength 
+    % Even pair
+        st_real(3,n+0)   = st_real(2,n+0) + st_real(2,n+2); 
+        % imag is 0
+        st_real(3,n+1)   = st_real(2,n+1) ;         % real is 0
+        st_imag(3,n+1)   = -1 * st_real(2,n+3);     % mult -j
+    % Odd par
+        st_real(3,n+2)   = st_real(2,n+0) - st_real(2,n+2); 
+        % imag is 0
+        st_real(3,n+3)   = st_real(2,n+1) ;         % real is 0
+        st_imag(3,n+3)   = st_real(2,n+3);          % mult -j
+end
+
+
+%% Therd stage
+
+% Calculating W twiddling factor 
+for n = 1 : 4 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 8 );
+end
+
+% calculate next stage values
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        % Even pair
+        stage(4,n+k)   = stage(3,n+k) + Wn(k+1)*stage(3,n+k+4);   
+        % Odd par
+        stage(4,n+k+4) = stage(3,n+k) - Wn(k+1)*stage(3,n+k+4); 
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        st_real_tmp(3,n+k+4) = ( Wr(k*4+1) * st_real(3,n+k+4) ) - (  Wi(k*4+1) * st_imag(3,n+k+4) );   
+        st_imag_tmp(3,n+k+4) = ( Wi(k*4+1) * st_real(3,n+k+4) ) + (  Wr(k*4+1) * st_imag(3,n+k+4) ); 
+    end
+end
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        % Even pair
+        st_real(4,n+k)   = st_real(3,n+k) + st_real_tmp(3,n+k+4);  
+        st_imag(4,n+k)   = st_imag(3,n+k) + st_imag_tmp(3,n+k+4);
+        % Odd par
+        st_real(4,n+k+4) = st_real(3,n+k) - st_real_tmp(3,n+k+4); 
+        st_imag(4,n+k+4) = st_imag(3,n+k) - st_imag_tmp(3,n+k+4); 
+    end
+end
+
+
+%% 4th stage  
+
+% Calculating W twiddling factor 
+for n = 1 : 8 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 16 );
+end
+
+% calculate next stage values
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+        % Even pair
+        stage(5,n+k)    = stage(4,n+k) + Wn(k+1)*stage(4,n+k+8);     
+        % Odd par
+        stage(5,n+k+8)  = stage(4,n+k) - Wn(k+1)*stage(4,n+k+8);  
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+         st_real_tmp(4,n+k+8) = ( Wr(k*2+1) * st_real(4,n+k+8) ) - (  Wi(k*2+1) * st_imag(4,n+k+8) );   
+         st_imag_tmp(4,n+k+8) = ( Wi(k*2+1) * st_real(4,n+k+8) ) + (  Wr(k*2+1) * st_imag(4,n+k+8) ); 
+    end
+end
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+        % Even pair
+        st_real(5,n+k)    = st_real(4,n+k) + st_real_tmp(4,n+k+8); 
+        st_imag(5,n+k)    = st_imag(4,n+k) + st_imag_tmp(4,n+k+8);
+        % Odd par
+        st_real(5,n+k+8)  = st_real(4,n+k) - st_real_tmp(4,n+k+8);
+        st_imag(5,n+k+8)  = st_imag(4,n+k) - st_imag_tmp(4,n+k+8);
+    end
+end
+
+%% 5th stage  
+
+% Calculating W twiddling factor 
+for n = 1 : 16 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 32 );
+end
+
+% calculate next stage values
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+        % Even pair
+        stage(6,n+k)    = stage(5,n+k) + Wn(k+1)*stage(5,n+k+16);     
+        % Odd par
+        stage(6,n+k+16)  = stage(5,n+k) - Wn(k+1)*stage(5,n+k+16);  
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+         st_real_tmp(5,n+k+16) = ( Wr(k*1+1) * st_real(5,n+k+16) ) - (  Wi(k*1+1) * st_imag(5,n+k+16) );   
+         st_imag_tmp(5,n+k+16) = ( Wi(k*1+1) * st_real(5,n+k+16) ) + (  Wr(k*1+1) * st_imag(5,n+k+16) );
+    end
+end
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+        % Even pair
+        st_real(6,n+k)    = st_real(5,n+k) + st_real_tmp(5,n+k+16); 
+        st_imag(6,n+k)    = st_imag(5,n+k) + st_imag_tmp(5,n+k+16); 
+        % Odd par
+        st_real(6,n+k+16)  = st_real(5,n+k) - st_real_tmp(5,n+k+16); 
+        st_imag(6,n+k+16)  = st_imag(5,n+k) - st_imag_tmp(5,n+k+16);
+    end
+end
+
+
+
+%% Ploting out
+% slowly plot result
+figure(5)
+for n = 1 : bits +1
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    stem( abs( stage(n,1:fftLength/2) ) );
+%     pause(1);
+end
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+title('FFT using custom function') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(6)
+for n = 1 : bits +1
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    temp = st_real + 1i * st_imag;
+    stem( abs( temp(n,1:fftLength/2) ) );
+%      pause(1);
+end
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+title('FFT using custom function real/imag separate') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(7)
+dif2 = 100* abs(temp(bits +1,1:fftLength/2) - ft(1:fftLength/2))./abs(ft(1:fftLength/2)) ;
+plot(dif2, 'blue')
+title('Difference in calculations') 
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+ylabel('percents, %'), xlabel('kHz') 
+
+##### SOURCE END #####
+--></body></html>
@@ -1,295 +0,0 @@
-%% FFT algoritm
-clear;  % clear all data from memmory
-start_time = 0;
-number_of_samples = 8;
-end_time = number_of_samples - 1;
-n = linspace(start_time, end_time , number_of_samples ); 
-
-f1 = 1;
-a1 = 0.2;
-
-f2 = 2;
-a2 = 00;
-
-f3 = 1;
-a3 = 00;
-comp1 = a1 * cos( f1 *2*pi*n/number_of_samples);
-comp2 = a2 * sin( f2 *2*pi*n/number_of_samples);
-comp3 = a3 * sin( f3 *2*pi*n/number_of_samples);
-
-data = comp1 + comp2 + comp3;
-
-
-figure(1)
-plot (n, comp1, '-');
-hold on;
-plot (n, comp2, '-');
-plot (n, comp3, '-');
-hold off;
-
-figure(2)
-plot (n, data);
-
-figure(3)
-X_matlab = fft(data, number_of_samples);
-stem (n,abs(X_matlab))
-
-%% My FFT
-
-%  W_N vector calculation
-% W  = zeros(1,number_of_samples);    % complex
-% Wr = zeros(1,number_of_samples);    % real
-% Wi = zeros(1,number_of_samples);    % imag
-% for i = 1 : number_of_samples 
-%     W(i)  = exp(-j * (i-1) * 2 * pi/ number_of_samples );
-%     Wr(i) = real(W(i));
-%     Wi(i) = imag(W(i));
-% end
-
-% reverse bit calulation
-
-bits = length(dec2bin( number_of_samples - 1 ));
-rev_bit_dec = zeros(1,number_of_samples); 
-
-for i=1:number_of_samples
-    bin_num = dec2bin(i-1 , bits);
-    rev_bit = [];
-    for k=bits:-1:1
-       rev_bit = [rev_bit , bin_num(k)];
-    end
-    rev_bit_dec(i) = bin2dec(rev_bit) + 1; % add 1 to match Matlab numbering   
-end
-
-% First stage of FFT
-
-stage = zeros(bits,number_of_samples);
-
-for i=1:number_of_samples
-     stage(1,i) =  data((i)); 
-    
-end
-
-
-stage(2,1) = stage(1,1) +  stage(1,2);
-stage(2,2) = stage(1,1) -  stage(1,2) ;
-
-stage(2,3) = (stage(1,3) +  stage(1,4)) * exp(-j * 0 * 2 * pi/ 4 );
-stage(2,4) = (stage(1,3) -  stage(1,4)) * exp(-j * 1 * 2 * pi/ 4 );
-
-stage(2,5) = stage(1,5) +  stage(1,6);
-stage(2,6) = stage(1,5) -  stage(1,6);
-
-stage(2,7) = (stage(1,7) +  stage(1,8)) * exp(-j * 0 * 2 * pi/ 4 );
-stage(2,8) = (stage(1,7) -  stage(1,8)) * exp(-j * 1 * 2 * pi/ 4 );
-
-% stage(2,9) = stage(1,9) + stage(1,10);
-% stage(2,10) = stage(1,9) -  stage(1,10);
-% 
-% stage(2,11) = (stage(1,11) +  stage(1,12)) * exp(-j * 0 * 2 * pi/ 4 );
-% stage(2,12) = (stage(1,11) -  stage(1,12)) * exp(-j * 1 * 2 * pi/ 4 );
-% 
-% stage(2,13) = stage(1,13) +  stage(1,14);
-% stage(2,14) = stage(1,13) -  stage(1,14);
-% 
-% stage(2,15) = (stage(1,15) +  stage(1,16)) * exp(-j * 0 * 2 * pi/ 4 );
-% stage(2,16) = (stage(1,15) -  stage(1,16)) * exp(-j * 1 * 2 * pi/ 4 );
-
-% stage(2,17) = stage(1,17) +  stage(1,18);
-% stage(2,18) = stage(1,17) -  stage(1,18)) * exp(-j * 1 * 2 * pi/ 4 );
-% 
-% stage(2,19) = stage(1,19) +  stage(1,20);
-% stage(2,20) = stage(1,19) -  stage(1,20)) * exp(-j * 1 * 2 * pi/ 4 );
-% 
-% stage(2,21) = stage(1,21) +  stage(1,22);
-% stage(2,22) = stage(1,21) -  stage(1,22);
-% 
-% stage(2,23) = stage(1,23) +  stage(1,24);
-% stage(2,24) = stage(1,23) -  stage(1,24);
-% 
-% stage(2,25) = stage(1,25) +  stage(1,26);
-% stage(2,26) = stage(1,25) -  stage(1,26);
-% 
-% stage(2,27) = stage(1,27) +  stage(1,28);
-% stage(2,28) = stage(1,27) -  stage(1,28);
-% 
-% stage(2,29) = stage(1,29) +  stage(1,30);
-% stage(2,30) = stage(1,29) -  stage(1,30);
-% 
-% stage(2,31) = stage(1,31) +  stage(1,32);
-% stage(2,32) = stage(1,31) -  stage(1,32);
-
-
-% stage,
-
-% Second stage 
-
-
-stage(2,1) = stage(1,1) +  stage(1,3);
-stage(2,2) = stage(1,2) +  stage(1,4);
-stage(2,3) = stage(1,1) -  stage(1,3);
-stage(2,4) = stage(1,2) -  stage(1,4);
-
-stage(2,5) = (stage(1,5) +  stage(1,7)) * exp(-j * 0 * 2 * pi/ 8 );
-stage(2,6) = (stage(1,6) +  stage(1,8)) * exp(-j * 1 * 2 * pi/ 8 );
-stage(2,7) = (stage(1,5) -  stage(1,7)) * exp(-j * 2 * 2 * pi/ 8 );
-stage(2,8) = (stage(1,6) -  stage(1,8)) * exp(-j * 3 * 2 * pi/ 8 );
-
-% stage(2,9) = stage(1,9) +   stage(1,11);
-% stage(2,10) = stage(1,10) + stage(1,12);
-% stage(2,11) = stage(1,9) - stage(1,11);
-% stage(2,12) = stage(1,10) - stage(1,12);
-% 
-% stage(2,13) = (stage(1,13) + stage(1,15)) * exp(-j * 0 * 2 * pi/ 8 );
-% stage(2,14) = (stage(1,14) + stage(1,16)) * exp(-j * 1 * 2 * pi/ 8 );
-% stage(2,15) = (stage(1,13) - stage(1,15)) * exp(-j * 2 * 2 * pi/ 8 );
-% stage(2,16) = (stage(1,14) - stage(1,16)) * exp(-j * 3 * 2 * pi/ 8 );
-
-% stage(2,17) = stage(1,17) + 1 * stage(1,19);
-% stage(2,18) = stage(1,18) + 1 * stage(1,20);
-% stage(2,19) = stage(1,19) - W1(1) * stage(1,17);
-% stage(2,20) = stage(1,20) - W1(2) * stage(1,18);
-% 
-% stage(2,21) = stage(1,21) + 1 * stage(1,23);
-% stage(2,22) = stage(1,22) + 1 * stage(1,24);
-% stage(2,23) = stage(1,23) - W1(1) * stage(1,21);
-% stage(2,24) = stage(1,24) - W1(2) * stage(1,22);
-% 
-% stage(2,25) = stage(1,25) + 1 * stage(1,27);
-% stage(2,26) = stage(1,26) + 1 * stage(1,28);
-% stage(2,27) = stage(1,27) - W1(1) * stage(1,25);
-% stage(2,28) = stage(1,28) - W1(2) * stage(1,26);
-% 
-% stage(2,29) = stage(1,29) + 1 * stage(1,31);
-% stage(2,30) = stage(1,30) + 1 * stage(1,32);
-% stage(2,31) = stage(1,31) - W1(1) * stage(1,29);
-% stage(2,32) = stage(1,32) - W1(2) * stage(1,30);
-
-% theard stage 
-
-
-stage(3,1) = stage(2,1) +  stage(2,5);
-stage(3,2) = stage(2,2) +  stage(2,6);
-stage(3,3) = stage(2,3) +  stage(2,7);
-stage(3,4) = stage(2,4) +  stage(2,8);
-stage(3,5) = stage(2,1) -  stage(2,5);
-stage(3,6) = stage(2,2) -  stage(2,6);
-stage(3,7) = stage(2,3) -  stage(2,7);
-stage(3,8) = stage(2,4) -  stage(2,8);
-
-% stage(3,9) =  (stage(2,9)  +  stage(2,13)) * exp(-j * 0 * 2 * pi/ 16 );
-% stage(3,10) = (stage(2,10) +  stage(2,14)) * exp(-j * 1 * 2 * pi/ 16 );
-% stage(3,11) = (stage(2,11) +  stage(2,15)) * exp(-j * 2 * 2 * pi/ 16 );
-% stage(3,12) = (stage(2,12) +  stage(2,16)) * exp(-j * 3 * 2 * pi/ 16 );
-% stage(3,13) = (stage(2,9)  -  stage(2,13)) * exp(-j * 4 * 2 * pi/ 16 );
-% stage(3,14) = (stage(2,10) -  stage(2,14)) * exp(-j * 5 * 2 * pi/ 16 );
-% stage(3,15) = (stage(2,11) -  stage(2,15)) * exp(-j * 6 * 2 * pi/ 16 );
-% stage(3,16) = (stage(2,12) -  stage(2,16)) * exp(-j * 7 * 2 * pi/ 16 );
-
-
-
-% stage(3,17) = stage(2,17) + W2(1) * stage(2,21);
-% stage(3,18) = stage(2,18) + W2(2) * stage(2,22);
-% stage(3,19) = stage(2,19) + W2(3) * stage(2,23);
-% stage(3,20) = stage(2,20) + W2(4) * stage(2,24);
-% stage(3,21) = stage(2,21) - W2(1) * stage(2,17);
-% stage(3,22) = stage(2,22) - W2(2) * stage(2,18);
-% stage(3,23) = stage(2,23) - W2(3) * stage(2,19);
-% stage(3,24) = stage(2,24) - W2(4) * stage(2,20);
-% 
-% stage(3,25) = stage(2,25) + W2(1) * stage(2,29);
-% stage(3,26) = stage(2,26) + W2(2) * stage(2,30);
-% stage(3,27) = stage(2,27) + W2(3) * stage(2,31);
-% stage(3,28) = stage(2,28) + W2(4) * stage(2,32);
-% stage(3,29) = stage(2,29) - W2(1) * stage(2,25);
-% stage(3,30) = stage(2,30) - W2(2) * stage(2,26);
-% stage(3,31) = stage(2,31) - W2(3) * stage(2,27);
-% stage(3,32) = stage(2,32) - W2(4) * stage(2,28);
-
-
-% Fourt stage
-
-% 
-% stage(4,1) = stage(3,1) +  stage(3,9);
-% stage(4,2) = stage(3,2) +  stage(3,10);
-% stage(4,3) = stage(3,3) +  stage(3,11);
-% stage(4,4) = stage(3,4) +  stage(3,12);
-% stage(4,5) = stage(3,5) +  stage(3,13);
-% stage(4,6) = stage(3,6) +  stage(3,14);
-% stage(4,7) = stage(3,7) +  stage(3,15);
-% stage(4,8) = stage(3,8) +  stage(3,16);
-% stage(4,9)  = stage(3,1) - stage(3,9);
-% stage(4,10) = stage(3,2) -  stage(3,10);
-% stage(4,11) = stage(3,3) -  stage(3,11);
-% stage(4,12) = stage(3,4) -  stage(3,12);
-% stage(4,13) = stage(3,5) -  stage(3,13);
-% stage(4,14) = stage(3,6) -  stage(3,14);
-% stage(4,15) = stage(3,7) -  stage(3,15);
-% stage(4,16) = stage(3,8) -  stage(3,16);
-
-% stage(4,17) = stage(3,17) + W3(1) * stage(3,25);
-% stage(4,18) = stage(3,18) + W3(2) * stage(3,26);
-% stage(4,19) = stage(3,19) + W3(3) * stage(3,27);
-% stage(4,20) = stage(3,20) + W3(4) * stage(3,28);
-% stage(4,21) = stage(3,21) + W3(5) * stage(3,29);
-% stage(4,22) = stage(3,22) + W3(6) * stage(3,30);
-% stage(4,23) = stage(3,23) + W3(7) * stage(3,31);
-% stage(4,24) = stage(3,24) + W3(8) * stage(3,32);
-% stage(4,25) = stage(3,25) - W3(1) * stage(3,17);
-% stage(4,26) = stage(3,26) - W3(2) * stage(3,18);
-% stage(4,27) = stage(3,27) - W3(3) * stage(3,19);
-% stage(4,28) = stage(3,28) - W3(4) * stage(3,20);
-% stage(4,29) = stage(3,29) - W3(5) * stage(3,21);
-% stage(4,30) = stage(3,30) - W3(6) * stage(3,22);
-% stage(4,31) = stage(3,31) - W3(7) * stage(3,23);
-% stage(4,32) = stage(3,32) - W3(8) * stage(3,24);
-
-% Fifth stage
-
-% W4  = zeros(1,32);    % complex
-% for i = 1 : 32 
-%     W4(i)  = exp(-j * (i-1) * 2 * pi/ 32 );
-% end
-% 
-% stage(5,1) = stage(4,1) + W4(1) * stage(4,17);
-% stage(5,2) = stage(4,2) + W4(2) * stage(4,18);
-% stage(5,3) = stage(4,3) + W4(3) * stage(4,19);
-% stage(5,4) = stage(4,4) + W4(4) * stage(4,20);
-% stage(5,5) = stage(4,5) + W4(5) * stage(4,21);
-% stage(5,6) = stage(4,6) + W4(6) * stage(4,22);
-% stage(5,7) = stage(4,7) + W4(7) * stage(4,23);
-% stage(5,8) = stage(4,8) + W4(8) * stage(4,24);
-% stage(5,9)  = stage(4,9)  + W4(9) * stage(4,25);
-% stage(5,10) = stage(4,10) + W4(10) * stage(4,26);
-% stage(5,11) = stage(4,11) + W4(11) * stage(4,27);
-% stage(5,12) = stage(4,12) + W4(12) * stage(4,28);
-% stage(5,13) = stage(4,13) + W4(13) * stage(4,29);
-% stage(5,14) = stage(4,14) + W4(14) * stage(4,30);
-% stage(5,15) = stage(4,15) + W4(15) * stage(4,31);
-% stage(5,16) = stage(4,16) + W4(16) * stage(4,32);
-% stage(5,17) = stage(4,17) - W4(1) * stage(4,1);
-% stage(5,18) = stage(4,18) - W4(2) * stage(4,2);
-% stage(5,19) = stage(4,19) - W4(3) * stage(4,3);
-% stage(5,20) = stage(4,20) - W4(4) * stage(4,4);
-% stage(5,21) = stage(4,21) - W4(5) * stage(4,5);
-% stage(5,22) = stage(4,22) - W4(6) * stage(4,6);
-% stage(5,23) = stage(4,23) - W4(7) * stage(4,7);
-% stage(5,24) = stage(4,24) - W4(8) * stage(4,8);
-% stage(5,25) = stage(4,25) - W4(9) * stage(4,9);
-% stage(5,26) = stage(4,26) - W4(10) * stage(4,10);
-% stage(5,27) = stage(4,27) - W4(11) * stage(4,11);
-% stage(5,28) = stage(4,28) - W4(12) * stage(4,12);
-% stage(5,29) = stage(4,29) - W4(13) * stage(4,13);
-% stage(5,30) = stage(4,30) - W4(14) * stage(4,14);
-% stage(5,31) = stage(4,31) - W4(15) * stage(4,15);
-% stage(5,32) = stage(4,32) - W4(16) * stage(4,16);
-
-
-
-
-figure(4)
-stem(n, abs( stage(bits,:) ) )
-
-
-
-
-
@@ -0,0 +1,306 @@
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=32;               % windowlength 
+
+% signal frequencies
+data_length = 8;           % data length in FPGA calculations 
+max = 2^(data_length-1) - 1 ;            % max aplitude 2^n  /2 
+
+f1 = 1000;
+a1 = max/2;
+
+f2 = 0;
+a2 = max/4;
+
+f3 = 8000;
+a3 = max/2;
+
+% calculating signals 
+comp1 = a1 * cos(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * cos(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * cos(2*pi*f3*[0:1/fs:1]);
+
+% calculatin vector values for step function
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+%data = [ d1 , d2];                  % creates vector with step function
+data = comp1 + comp2 + comp3;      % creates vector from 3 sin functions
+
+figure(1)               % plots separete sin functions
+plot ( comp1, '-');
+hold on;
+plot ( comp2, '-');
+plot ( comp3, '-');
+xlim([1 50])
+title('Separete SIN functions') 
+ylabel('magnitude'), xlabel('time') 
+hold off;
+
+figure(2)               % plots signal for fft
+plot ( data);
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+xlim([1 100])
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft =fft(data,fftLength); 
+ftMag=abs(ft(1:fftLength/2)); 
+stem (ftMag)
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
+
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+
+% figure(4)               % plots resultinf fft(in dB)  from Matlab functions
+% ft =fft(data,fftLength); 
+% ftMag=abs(ft(1:fftLength/2)); 
+% plot (20*log10(ftMag))
+% title('dB Magnitude') 
+% ylabel('dB'), xlabel('kHz') 
+% 
+% xt = xticks;        % returns the current x-axis tick values as a vector
+% fstep = fs/fftLength;       % tick of f axis in f domain 
+% xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+% xticklabels(xtnew)      % set new tick labels
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);           % create vektor size of fftlength
+
+for n=1:fftLength
+    bin_num = dec2bin(n-1 , bits);          % converting to binary number
+    rev_bit = [];                           % create empty vector
+    for k=bits:-1:1
+       rev_bit = [rev_bit , bin_num(k)];
+    end
+    rev_bit_dec(n) = bin2dec(rev_bit) ;     % add 1 to match Matlab numbering   
+end
+
+%  creating array
+%  create empty array to store values in reverse bit order
+stage = zeros(bits + 1,fftLength);
+
+for n=1:fftLength
+     stage(1,n)  =  data(rev_bit_dec(n)+1);
+end
+
+% Calculating W twiddling factor for all stages 
+for n = 1 : fftLength/2 
+    W(n)  = exp(-1i * (n-1) * 2 * pi/ fftLength );
+end
+
+% convert to fixed point mumber -> sfi(v,w,f) returns a signed fixed-point object with value v, word length w, and fraction length f.
+Wr = sfi(real(W),data_length,data_length-2);       
+Wi = sfi(imag(W),data_length,data_length-2);
+
+st_real = sfi(real(stage) , data_length + 3 , 0);
+st_imag = sfi(imag(stage) , data_length + 3 , 0);
+% temp values for multiplaying with W twiddling factor
+st_real_tmp = sfi(real(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+st_imag_tmp = sfi(imag(zeros(bits + 1,fftLength)) , data_length + 3 , 0);
+
+%% First stage
+
+for n = 1 : 2^1 : fftLength 
+    % Even
+    stage(2,n)    = stage(1,n) + stage(1,n+1);
+    % Odd
+    stage(2,n+1)  = stage(1,n) - stage(1,n+1);
+end
+
+% calculations using separate real and imaginary numbers 
+for n = 1 : 2^1 : fftLength 
+    % Even
+    st_real(2,n)    = st_real(1,n) + st_real(1,n+1);
+    % imag is 0
+    % Odd
+    st_real(2,n+1)  = st_real(1,n) - st_real(1,n+1);
+    % imag is 0
+end
+
+%% Second stage
+
+% Calculating W twiddling factor 
+for n = 1 : 2 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 4 );
+end
+
+% calculate next stage values
+for n = 1 : 2^2 : fftLength 
+    % Even pair
+        stage(3,n+0)   = stage(2,n+0) + Wn(1)*stage(2,n+2); 
+        stage(3,n+1)   = stage(2,n+1) + Wn(2)*stage(2,n+3); 
+    % Odd par
+        stage(3,n+2)   = stage(2,n+0) - Wn(1)*stage(2,n+2); 
+        stage(3,n+3)   = stage(2,n+1) - Wn(2)*stage(2,n+3); 
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^2 : fftLength 
+    % Even pair
+        st_real(3,n+0)   = st_real(2,n+0) + st_real(2,n+2); 
+        % imag is 0
+        st_real(3,n+1)   = st_real(2,n+1) ;         % real is 0
+        st_imag(3,n+1)   = -1 * st_real(2,n+3);     % mult -j
+    % Odd par
+        st_real(3,n+2)   = st_real(2,n+0) - st_real(2,n+2); 
+        % imag is 0
+        st_real(3,n+3)   = st_real(2,n+1) ;         % real is 0
+        st_imag(3,n+3)   = st_real(2,n+3);          % mult -j
+end
+
+
+%% Therd stage
+
+% Calculating W twiddling factor 
+for n = 1 : 4 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 8 );
+end
+
+% calculate next stage values
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        % Even pair
+        stage(4,n+k)   = stage(3,n+k) + Wn(k+1)*stage(3,n+k+4);   
+        % Odd par
+        stage(4,n+k+4) = stage(3,n+k) - Wn(k+1)*stage(3,n+k+4); 
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        st_real_tmp(3,n+k+4) = ( Wr(k*4+1) * st_real(3,n+k+4) ) - (  Wi(k*4+1) * st_imag(3,n+k+4) );   
+        st_imag_tmp(3,n+k+4) = ( Wi(k*4+1) * st_real(3,n+k+4) ) + (  Wr(k*4+1) * st_imag(3,n+k+4) ); 
+    end
+end
+for n = 1 : 2^3 : fftLength 
+    for k = 0 : 3
+        % Even pair
+        st_real(4,n+k)   = st_real(3,n+k) + st_real_tmp(3,n+k+4);  
+        st_imag(4,n+k)   = st_imag(3,n+k) + st_imag_tmp(3,n+k+4);
+        % Odd par
+        st_real(4,n+k+4) = st_real(3,n+k) - st_real_tmp(3,n+k+4); 
+        st_imag(4,n+k+4) = st_imag(3,n+k) - st_imag_tmp(3,n+k+4); 
+    end
+end
+
+
+%% 4th stage  
+
+% Calculating W twiddling factor 
+for n = 1 : 8 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 16 );
+end
+
+% calculate next stage values
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+        % Even pair
+        stage(5,n+k)    = stage(4,n+k) + Wn(k+1)*stage(4,n+k+8);     
+        % Odd par
+        stage(5,n+k+8)  = stage(4,n+k) - Wn(k+1)*stage(4,n+k+8);  
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+         st_real_tmp(4,n+k+8) = ( Wr(k*2+1) * st_real(4,n+k+8) ) - (  Wi(k*2+1) * st_imag(4,n+k+8) );   
+         st_imag_tmp(4,n+k+8) = ( Wi(k*2+1) * st_real(4,n+k+8) ) + (  Wr(k*2+1) * st_imag(4,n+k+8) ); 
+    end
+end
+for n = 1 : 2^4 : fftLength 
+    for k = 0 : 7
+        % Even pair
+        st_real(5,n+k)    = st_real(4,n+k) + st_real_tmp(4,n+k+8); 
+        st_imag(5,n+k)    = st_imag(4,n+k) + st_imag_tmp(4,n+k+8);
+        % Odd par
+        st_real(5,n+k+8)  = st_real(4,n+k) - st_real_tmp(4,n+k+8);
+        st_imag(5,n+k+8)  = st_imag(4,n+k) - st_imag_tmp(4,n+k+8);
+    end
+end
+
+%% 5th stage  
+
+% Calculating W twiddling factor 
+for n = 1 : 16 
+    Wn(n)  = exp(-1i * (n-1) * 2 * pi/ 32 );
+end
+
+% calculate next stage values
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+        % Even pair
+        stage(6,n+k)    = stage(5,n+k) + Wn(k+1)*stage(5,n+k+16);     
+        % Odd par
+        stage(6,n+k+16)  = stage(5,n+k) - Wn(k+1)*stage(5,n+k+16);  
+    end
+end
+
+% calculations using separate real and imaginary numbers  
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+         st_real_tmp(5,n+k+16) = ( Wr(k*1+1) * st_real(5,n+k+16) ) - (  Wi(k*1+1) * st_imag(5,n+k+16) );   
+         st_imag_tmp(5,n+k+16) = ( Wi(k*1+1) * st_real(5,n+k+16) ) + (  Wr(k*1+1) * st_imag(5,n+k+16) );
+    end
+end
+for n = 1 : 2^5 : fftLength 
+    for k = 0 : 15
+        % Even pair
+        st_real(6,n+k)    = st_real(5,n+k) + st_real_tmp(5,n+k+16); 
+        st_imag(6,n+k)    = st_imag(5,n+k) + st_imag_tmp(5,n+k+16); 
+        % Odd par
+        st_real(6,n+k+16)  = st_real(5,n+k) - st_real_tmp(5,n+k+16); 
+        st_imag(6,n+k+16)  = st_imag(5,n+k) - st_imag_tmp(5,n+k+16);
+    end
+end
+
+
+
+%% Ploting out
+% slowly plot result
+figure(5)
+for n = 1 : bits +1
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    stem( abs( stage(n,1:fftLength/2) ) );
+%     pause(1);
+end
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+title('FFT using custom function') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(6)
+for n = 1 : bits +1
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+    temp = st_real + 1i * st_imag;
+    stem( abs( temp(n,1:fftLength/2) ) );
+%      pause(1);
+end
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+title('FFT using custom function real/imag separate') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(7)
+dif2 = 100* abs(temp(bits +1,1:fftLength/2) - ft(1:fftLength/2))./abs(ft(1:fftLength/2)) ;
+plot(dif2, 'blue')
+title('Difference in calculations') 
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round((xt-1)*fstep/1000, 1) ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+ylabel('percents, %'), xlabel('kHz') 
@@ -0,0 +1,119 @@
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=512;              % windowlength 
+stage_num = log2(fftLength);
+% signal frequencies
+max = 2048 - 1 ;
+
+f1 = 430;
+a1 = 0;
+
+f2 = 4300;
+a2 = 0;
+
+f3 = 8000;
+a3 = max/2;
+
+% calculating signals 
+comp1 = a1 * sin(2*pi*f1*[0:1/fs:1]);
+comp2 = a2 * sin(2*pi*f2*[0:1/fs:1]);
+comp3 = a3 * sin(2*pi*f3*[0:1/fs:1]);
+Length = length(comp3);
+% calculatin vector values for step function
+d1 = ones(1, 24);
+d2 = 0.*ones(1, 1000 );
+
+%data = [ d1 , d2];                  % creates vector with step function
+data = comp1 + comp2 + comp3;      % creates vector from 3 sin functions
+%data = comp3;
+
+% Grafika nobiides
+bin_vals = [0 : fftLength-1];
+N_2 = ceil(fftLength/2);
+fax_kHz = (bin_vals-N_2)*fs/fftLength/1000;
+
+freq3 = ceil(-(fftLength)/2:1:(fftLength)/2).*(fs/fftLength)/1000;
+
+figure(1)               % plots separete sin functions
+hold off,
+%plot ( comp1, '-');
+hold on;
+%plot ( comp2, '-');
+plot ( comp3, '-'), grid minor,;
+%xlim([1 50])
+title('Separete SIN functions') 
+ylabel('magnitude'), xlabel('time') 
+hold off;
+
+figure(2)               % plots signal for fft
+plot ( data), grid minor,;
+xlim([1 50])
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+%xlim([1 100])
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft =fft(data,fftLength); 
+ft1 = fftshift(ft);
+ftMag = abs(ft1); 
+plot (fax_kHz,ftMag), grid minor,
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
+
+figure(4)               % plots resultinf fft(in dB)  from Matlab functions
+ft = fft(data,fftLength+1); 
+ftMag = abs(ft(1:fftLength+1)); 
+plot (freq3,20*log10(ftMag)), grid minor,
+title('dB Magnitude') 
+ylabel('dB'), xlabel('kHz') 
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);           % create vektor size of fftlength
+
+stage = 1;              %Do it here for stage #1 
+c = 0:fftLength-1;
+c_bin = de2bi(c);       % create binary table
+rev_bit_dec = bi2de(fliplr(circshift(c_bin',stage-1)'));    %Rotate binary table and convert to dec
+
+%  creating array
+%  create empty array to store values in reverse bit order
+stage = zeros(bits + 1,fftLength);
+
+%% New stages
+
+for st = 0 : stage_num;
+    if st == 0
+       for tmp=1:fftLength;
+            stage(st+1,tmp)  =  data(rev_bit_dec(tmp)+1);
+       end
+    else st > 0;
+        for n = 1 : fftLength/2;
+                Wn(n)  = exp(-j * (n-1) * 2 * pi/ 2^(st) );
+        end
+        for i = 1 : 2^st : fftLength;
+                for k = 0 : 2^(st-1)-1;
+                    % Even
+                        stage(st+1,i+k) = stage(st,i+k) + Wn(k+1)*stage(st,i+k+2^(st-1));
+                    % Odd
+                        stage(st+1,i+k+2^(st-1)) = stage(st,i+k) - Wn(k+1)*stage(st,i+k+2^(st-1));
+                end
+        end
+    end
+end
+
+%% Ploting out
+% slowly plot result
+figure(5)
+for i = 1 : bits + 1;
+    %plot( abs( real_n(i, :) + j.*imag_n(i,  :) ) );
+        plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ), grid minor,;
+    pause(1);
+end
+
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel('kHz') 
@@ -0,0 +1,136 @@
+%% If need working only with Real and Imginary parts Comment lines started 
+% with "Stage" in "New Stages" part and on the bottom whole figure(5)
+
+%% FFT algoritm
+clear;                      % clears all previus values from memory 
+clc;                        % clear command window
+fs =  44100;                % samplinf freq.
+fftLength=2^9;              % windowlength 
+stage_num = log2(fftLength);
+Wn_word = 12;                % signed fixed point lenght for Wn (fraction is word-2)
+samp_word = 8;               % word lenght of samped signal (fraction is word-2)
+w_bits = 10;                 % signed fixed point integer bit lenght
+f_bits = 10;                 % signed fixed point integer bit lenght for calculations
+
+                           
+% reading input audio file
+% audio samples are from matlab examples
+% load handel.mat
+% filename = 'handel.wav';
+% load gong.mat;
+filename = 'gong.wav';
+% audiowrite(filename,y,Fs);
+[y,fs] = audioread(filename);
+data = sfi(y, samp_word, samp_word-2); 
+m = 7;                          % alow select section of signal for FFT
+data_cut = data(fftLength*m+1:fftLength*m+fftLength);
+%sound(data.double,fs);
+
+figure(2)               % plots signal for fft
+plot (data_cut), grid minor,
+% xlim([fftLength*m+1 fftLength*m+fftLength])
+title('Signal for FFT analysis FFT') 
+ylabel('magnitude'), xlabel('time') 
+
+
+bin_vals = [0 : fftLength-1];
+
+figure(3)               % plots resultinf fft from Matlab functions
+ft = fft(data_cut.double,fftLength); 
+ft1 = fftshift(ft);
+ftMag = abs(ft1); 
+plot (bin_vals,ftMag), grid minor,
+title('Linear Magnitude FFT') 
+ylabel('magnitude'), xlabel(' ') 
+
+% figure(4)               % plots resultinf fft(in dB) from Matlab functions
+% ft = fft(data.double,fftLength); 
+% ft1 = fftshift(ft);
+% ftMag = abs(ft1(1:fftLength)); 
+% plot (bin_vals,20*log10(ftMag)), grid minor,
+% title('dB Magnitude') 
+% ylabel('dB'), xlabel(' ') 
+
+%% Data preparation for FFT
+
+% reverse bit calulation
+bits = length(dec2bin( fftLength - 1 ));    % how many bits in binary number
+rev_bit_dec = zeros(1,fftLength);           % create vektor size of fftlength
+
+stage = 1;              %Do it here for stage #1 
+c = 0:fftLength-1;
+c_bin = de2bi(c);       % create binary table
+rev_bit_dec = bi2de(fliplr(circshift(c_bin',stage-1)'));    %Rotate binary table and convert to dec
+
+%  creating matrix arrays
+%  create empty matrix arrays to store values in reverse bit order
+stage = zeros(bits+1,fftLength);
+real_n = zeros(bits+1,fftLength);
+imag_n = zeros(bits+1,fftLength);
+
+real_n_sfi = zeros(bits+1,fftLength);
+imag_n_sfi = zeros(bits+1,fftLength);
+
+%% Starting stages
+
+for st = 0 : stage_num
+    if st == 0
+       for tmp=1:fftLength
+            stage(st+1,tmp)  =  data_cut(rev_bit_dec(tmp)+1);
+            real_n(st+1,tmp)  =  data_cut(rev_bit_dec(tmp)+1);
+            real_n_sfi(st+1,tmp) = sfi(real_n(st+1,tmp),f_bits  +  w_bits ,f_bits);
+       end
+    else st > 0;
+        for n = 1 : fftLength/2
+                Wn(n)  = exp(-j * (n-1) * 2 * pi/ 2^(st) );
+%                 Wr(n) = real(Wn(n));
+%                 Wi(n) = imag(Wn(n));
+                Wr(n) = sfi(real(Wn(n)),Wn_word,Wn_word-2);
+                Wi(n) = sfi(imag(Wn(n)),Wn_word,Wn_word-2);
+        end
+        for i = 1 : 2^st : fftLength
+                for k = 0 : 2^(st-1)-1
+                    % Even
+                        stage(st+1,i+k) = stage(st,i+k) + Wn(k+1)*stage(st,i+k+2^(st-1));
+                        real_n(st+1,i+k) = real_n_sfi(st,i+k) + Wr(k+1)*real_n_sfi(st,i+k+2^(st-1)) - Wi(k+1)*imag_n_sfi(st,i+k+2^(st-1));
+                        imag_n(st+1,i+k) = imag_n_sfi(st,i+k) + Wi(k+1)*real_n_sfi(st,i+k+2^(st-1)) + Wr(k+1)*imag_n_sfi(st,i+k+2^(st-1));
+                        real_n_sfi(st+1,i+k) = sfi(real_n(st+1,i+k),f_bits  + w_bits,f_bits);
+                        imag_n_sfi(st+1,i+k) = sfi(imag_n(st+1,i+k),f_bits  + w_bits,f_bits);
+                    % Odd
+                        stage(st+1,i+k+2^(st-1)) = stage(st,i+k) - Wn(k+1)*stage(st,i+k+2^(st-1));
+                        real_n(st+1,i+k+2^(st-1)) = real_n_sfi(st,i+k) - Wr(k+1)*real_n_sfi(st,i+k+2^(st-1)) +  Wi(k+1)*imag_n_sfi(st,i+k+2^(st-1));
+                        imag_n(st+1,i+k+2^(st-1)) = imag_n_sfi(st,i+k) - Wi(k+1)*real_n_sfi(st,i+k+2^(st-1)) - Wr(k+1)*imag_n_sfi(st,i+k+2^(st-1));
+                        real_n_sfi(st+1,i+k+2^(st-1)) = sfi(real_n(st+1,i+k+2^(st-1)),f_bits +  w_bits,f_bits);
+                        imag_n_sfi(st+1,i+k+2^(st-1)) = sfi(imag_n(st+1,i+k+2^(st-1)),f_bits +  w_bits,f_bits);
+                end
+        end
+    end
+end
+
+%% Plotting out
+
+% for slowly result plotting uncomment pause
+
+figure(5)
+%for i = 1 : bits + 1;
+for i = bits+1 : bits + 1
+    %plot( fax_kHz, abs( fftshift( real_n(i, :) + j.*imag_n(i,:) ) ) ),
+    plot( bin_vals, abs( fftshift( stage(i,:) ) ) ),
+    grid minor, title('Linear Magnitude FFT'), ylabel('magnitude'), xlabel(' ');
+    %pause(1);
+end
+
+figure(6)
+%for i = 1 : bits + 1;
+for i = bits+1 : bits + 1
+    plot( bin_vals, abs( fftshift( real_n_sfi(i, :) + j.*imag_n_sfi(i,:) ) ) ),
+    grid minor, title('Linear Magnitude FFT, ploted from Real + Imag'), ylabel('magnitude'), xlabel(' ');
+    %plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ), grid minor,;
+    %pause(1);
+end
+
+figure(7)
+dif = abs( fftshift( stage(bits+1,:) ) ) - abs( fftshift( real_n_sfi(bits+1, :) + j.*imag_n_sfi(bits+1,:) ) )  ;
+plot( bin_vals, dif )
+grid minor, title('Difference in plots'), ylabel('diff magnitude'), xlabel(' ');
+
@@ -1,16 +1,28 @@
-f = 4000; 
-fs = 22050; 
-fftLength=1024;             %windowlength 
-x =sin(2*pi*f*[0:1/fs:1]);  %makethesinewave 
-ft =fft(x,fftLength);       %doFFT,userect.window 
-ftMag=abs(ft);              %computemagnitude 
+f = 4300; 
+fs =  44100; 
+fftLength=512;             % windowlength 
+x =sin(2*pi*1000*[0:1/fs:1]) + sin(2*pi*f*[0:1/fs:1])  +  sin(2*pi*20000*[0:1/fs:1]);  % makethesinewave 
+ft =fft(x,fftLength);       % doFFT,userect.window 
+ftMag=abs(ft(1:fftLength/2));          % computemagnitude ( half )

 % plot the results both in linear and dB magnitudes 

 subplot(2, 1, 1), plot(ftMag) 
 title('Linear Magnitude') 
-ylabel('magnitude'), xlabel('bins') 
+ylabel('magnitude'), xlabel('kHz') 

+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = fs/fftLength;       % tick of f axis in f domain 
+xtnew = round(xt*fstep)/1000 ;   % calculate new tick in kHz
+xticklabels(xtnew)      % set new tick labels
+ 
 subplot(2, 1, 2), plot(20*log10(ftMag)) 
 title('dB Magnitude') 
-ylabel('dB'), xlabel('bins')
+ylabel('dB'), xlabel('kHz')
+
+xt = xticks;        % returns the current x-axis tick values as a vector
+fstep = (fs/fftLength);       % tick of f axis in f domain 
+xtnew = round(xt*fstep)/1000;   % calculate new tick in kHz
+xticklabels(xtnew)        % set new tick labels
+
+    
@@ -0,0 +1,146 @@
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - 7 segmet display module
+//
+// Detailed module description:
+// Outputs information on 7 segmet display
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////
+module segment4x7(
+    input           clk,  // 10kHz clock
+    input   [15:0]  in,   // input
+    output  [6:0]   seg,  // individual segments of number
+    output  [3:0]   an,   // anode to select character
+    output          dp    // dot on 7segment display
+    );
+
+//-------------Internal Constants---------------------------
+parameter SIZE = 2;
+parameter [SIZE-1:0]    ONE     = 2'b00,
+                        TWO     = 2'b01,
+                        THREE   = 2'b10,
+                        FOUR    = 2'b11;
+
+reg [SIZE-1:0] state=ONE, next=TWO;
+reg [3:0] nibble = 'b0 ;
+
+//---------State register sequential always block-----------
+always @(posedge clk ) begin
+    state <= next;
+end
+//----Next state & outputs, combinational always block------
+
+always@(state or in)begin
+  case(state)
+    ONE : begin 
+        next <= TWO;
+        nibble <= in[3:0]; 
+    end
+    TWO : begin
+        next <= THREE;
+        nibble <= in[7:4];
+    end
+    THREE : begin 
+        next <= FOUR;
+        nibble <= in[11:8];
+    end
+    FOUR : begin 
+        next <= ONE;
+        nibble <= in[15:12];
+    end
+  endcase
+end
+
+  assign seg[6] = ( nibble == 4'h2 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h4 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hB ||
+                    nibble == 4'hD ||
+                    nibble == 4'hE ||
+                    nibble == 4'hF ) ? 1'b0 : 1'b1;
+  assign seg[5] = ( nibble == 4'h0 ||
+                    nibble == 4'h4 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hB ||
+                    nibble == 4'hC ||
+                    nibble == 4'hE ||
+                    nibble == 4'hF ) ? 1'b0 : 1'b1;
+  assign seg[4] = ( nibble == 4'h0 ||
+                    nibble == 4'h2 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hB ||
+                    nibble == 4'hC ||
+                    nibble == 4'hD ||
+                    nibble == 4'hE ||
+                    nibble == 4'hF ) ? 1'b0 : 1'b1;
+  assign seg[3] = ( nibble == 4'h0 ||
+                    nibble == 4'h2 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hB ||
+                    nibble == 4'hC ||
+                    nibble == 4'hD ||
+                    nibble == 4'hE ) ? 1'b0 : 1'b1;
+  assign seg[2] = ( nibble == 4'h0 ||
+                    nibble == 4'h1 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h4 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h7 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hB ||
+                    nibble == 4'hD ) ? 1'b0 : 1'b1;
+  assign seg[1] = ( nibble == 4'h0 ||
+                    nibble == 4'h1 ||
+                    nibble == 4'h2 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h4 ||
+                    nibble == 4'h7 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hD ) ? 1'b0 : 1'b1;
+  assign seg[0] = ( nibble == 4'h0 ||
+                    nibble == 4'h2 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h7 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hC ||
+                    nibble == 4'hE ||
+                    nibble == 4'hF) ? 1'b0 : 1'b1;
+  assign dp = 1'b1;     //dot not using
+
+  assign an[0] = (state==ONE)   ? 1'b0 : 1'b1;   
+  assign an[1] = (state==TWO)   ? 1'b0 : 1'b1;
+  assign an[2] = (state==THREE) ? 1'b0 : 1'b1;
+  assign an[3] = (state==FOUR)  ? 1'b0 : 1'b1;
+  
+endmodule
@@ -1,15 +1,40 @@
-//      TOP module 
-//       
-
-
-
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - Top module
+//
+// Detailed module description:
+//
+// 
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////
 module top #( parameter
    sclk_ws_ratio = 64,         // number of sclk periods per word select period
    mclk_sclk_ratio = 4,        // number of mclk periods per sclk period
-    d_width = 24                // data width
+    d_width = 24,               // data width for I2S
+    memory_d_width = 16         // data width for memory (and effects). lower bits are ignored
 )(
    input           clk,
    input           btnC,
+    output  [15:0]  led, 
+    // 7 segment display
+    output  [6:0]   seg,
+    output          dp,
+    output  [3:0]   an, 
+    //VGA  inputs outputs
+    output [3:0]    vgaRed,
+    output [3:0]    vgaBlue,
+    output [3:0]    vgaGreen,
+    output          Hsync,
+    output          Vsync,
+
+    input   [15:0]  sw,         // swiches on board to control effects
    output          da_mclk,
    output          ad_mclk,
    output          da_sclk,
@@ -21,113 +46,139 @@ module top #( parameter
    output  [7: 0]  JXADC       // output for logic analizer
    );

-//------internal wires and registers--------
-wire master_clk;            // 11.29 MHz master clock
-wire serial_clk_sender;
-wire word_select_sender;
-wire serial_clk_receicer;
-wire word_select_receicer;
-wire reset_n;
-wire [d_width-1: 0] r_data_tx;
-wire [d_width-1: 0] l_data_tx;
-wire [d_width-1: 0] r_data_rx;
-wire [d_width-1: 0] l_data_rx;
-
-wire w_sd_tx;               //internal wire
-
-//-----sub modules--------------------------
-// connecting signals to JXADC PMOD to monitor them with signal analyzer
-JXADC_controler JXADC_controler(
-    .ch0(master_clk),
-    .ch1(serial_clk_receicer),
-    .ch2(word_select_receicer),
-    .ch3(ad_sdout),     // serial data in
-    .ch4(master_clk),
-    .ch5(serial_clk_sender),
-    .ch6(word_select_sender),
-    .ch7(w_sd_tx),      // serial data out
-    .JXADC(JXADC)       // output for logic analizer   
-);
-
-
-//declare PLL to create 11.29 MHz master clock from 100 MHz system clock
-clk_wiz_0 m_clk(
-    .clk_in1(clk),
-    .clk_out1(master_clk)
-);
-
-// // instantiate I2S Transceiver component
-// i2s_transceiver  #(
-//     .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
-//     .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
-//     .d_width(d_width)                       //data width
-// ) i2s_transceiver (
-//     .reset_n(reset_n),         //asynchronous active high reset
-//     .mclk(master_clk),      //master clock
-//     .sclk(serial_clk),      //serial clock (or bit clock)
-//     .ws(word_select),       //word select (or left-right clock)
-//     .sd_rx(ad_sdout),       //serial data transmit
-//     .sd_tx(w_sd_tx),        //serial data receive
-//     .l_data_tx(l_data_tx),  //left channel data to transmit
-//     .r_data_tx(r_data_tx),  //right channel data to transmit
-//     .l_data_rx(l_data_rx),  //left channel data received
-//     .r_data_rx(r_data_rx)   //right channel data received
-// );
-
-i2s_sender  #(
-    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
-    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
-    .d_width(d_width)                       //data width
-) i2s_sender (
-    .reset_n(reset_n),      //asynchronous active high reset
-    .mclk(master_clk),      //master clock
-    .sclk(serial_clk_sender),      //serial clock (or bit clock)
-    .ws(word_select_sender),       //word select (or left-right clock)
-    .sd_tx(w_sd_tx),        //serial data transmit
-    .l_data_tx(l_data_tx),  //left channel data to transmit
-    .r_data_tx(r_data_tx)   //right channel data to transmit
-);
-
-i2s_receicer  #(
-    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
-    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
-    .d_width(d_width)                       //data width
-) i2s_receicer (
-    .reset_n(reset_n),         //asynchronous active high reset
-    .mclk(master_clk),      //master clock
-    .sclk(serial_clk_receicer),      //serial clock (or bit clock)
-    .ws(word_select_receicer),       //word select (or left-right clock)
-    .sd_rx(ad_sdout),       //serial data receive
-    .l_data_rx(l_data_rx),  //left channel data received
-    .r_data_rx(r_data_rx)   //right channel data received
-);
-
-//passing data to effect controler
-effect_controler #(
-    .d_width(d_width)                       //data width
-) effect_controler (
-//  .clk(clk),
-    .i_l_data(l_data_rx),               //left channel data received         
-    .i_r_data(r_data_rx),               //right channel data received
-    .o_l_data(l_data_tx),               //left channel data to transmit
-    .o_r_data(r_data_tx)                //right channel data to transmit
-);
-
-//debounce reset button
-debounce_switch debounce_switch_reset(
-    .clk(master_clk),
-    .i_switch(btnC),
-    .o_switch(reset_n)
-);
+//assign output from effect controler to leds
+assign led = sw;

 assign da_mclk = master_clk;    //output master clock to ADC
 assign ad_mclk = master_clk;    //output master clock to DAC
-assign da_sclk = serial_clk_sender;    //output serial clock (from I2S Transceiver) to ADC
-assign ad_sclk = serial_clk_receicer;    //output serial clock (from I2S Transceiver) to DAC
-assign da_lrck = word_select_sender;   //output word select (from I2S Transceiver) to ADC
-assign ad_lrck = word_select_receicer;   //output word select (from I2S Transceiver) to DAC
+// assign da_sdin = w_sd_tx;      //assign received data to transmit (to playback out received data)

-assign da_sdin = w_sd_tx;      //assign right channel received data to transmit (to playback out received data)

+//------internal wires and registers--------
+wire master_clk;            // 11.29 MHz master clock
+wire clk_50MHz;             // 50 MHz clock 
+wire clk_25MHz;             // 25 MHz clock 
+
+wire                w_reset; 
+wire                w_internal_reset;
+
+// wire signed [d_width-1: 0] r_data_tx;
+// wire signed [d_width-1: 0] l_data_tx;
+wire signed [d_width-1: 0] r_data_rx;
+wire signed [d_width-1: 0] l_data_rx;
+
+
+wire [d_width-1: 0] w_data_to_eff;
+wire                w_dv_to_eff;  
+
+wire                w_dv_from_eff; 
+wire                w_rd_en_from_eff;
+
+wire                w_read_done_eff;        // read done from effects module to mixer 
+wire                w_read_ready_eff;       // ready to read from effects module   
+
+// Data wires from effects module to effect controler
+wire [d_width-1: 0] w_data_from_eff_sw0;
+wire [d_width-1: 0] w_data_from_eff_sw1;
+
+
+
+//-----sub modules--------------------------
+
+// declare PLL to create 11.29 MHz master clock from 100 MHz system clock for I2S
+//
+// Common clocking errors with 7-Series FPGAs
+// http://www.markharvey.info/art/7clk_19.10.2015/7clk_19.10.2015.html
+clk_wiz_0 m_clk(
+    .clk_in1(clk),
+    .clk_out1(master_clk),  // 11.29 MHz master clock for I2S
+    .clk_out2(clk_50MHz),   // 50MHz main clock
+    .clk_out3(clk_25MHz),   // 25MHz main clock
+    .locked(w_internal_reset),
+    .reset(btnC)
+);
+
+// Flip-flop for reset
+d_flipflop_sync_rst D_flipflop1 (
+    .D(1'b0),
+    .Q(w_reset),
+    .clk(master_clk),
+    .reset(~w_internal_reset));
+
+
+io_module  #(
+    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
+    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
+    .d_width(d_width)                       //data width
+) io_module (
+    .reset(reset_n),                    //asynchronous active high reset
+    .mclk(master_clk),                  //master clock
+    .da_sclk(da_sclk),                  //serial clock (or bit clock)
+    .da_ws(da_lrck),                    //word select (or left-right clock)
+    .ad_sclk(ad_sclk),                  //serial clock (or bit clock)
+    .ad_ws(ad_lrck),                    //word select (or left-right clock)
+    .sd_tx(da_sdin),                    //serial data transmit
+    .sd_rx(ad_sdout),                   //serial data receive
+    .l_data_tx(l_data_rx),              //left channel data to transmit
+    .r_data_tx(r_data_rx),              //right channel data to transmit
+
+    .reset(w_reset),           //reset 
+
+    .l_data_rx(l_data_rx),              //left channel data received
+    .r_data_rx(r_data_rx),              //right channel data received
+
+
+    // inputs to logic analyzer
+    .ch0(Hsync),
+    .ch1(Vsync),
+    .ch2(),
+    .ch3(),
+    .ch4(),
+    .ch5(),
+    .ch6(),
+    .ch7(),
+
+    .JXADC(JXADC)                       // output for logic analizer
+);
+
+segment4x7 segment4x7(
+    .clk(clk10k),       // 10kHz clock
+    .in(sw),            // input
+    .seg(seg),          // individual segments of number
+    .an(an),            // anode to select character
+    .dp(dp)             // dot on 7segment display
+    );
+
+clock_divider #(.WIDTH(11)) 
+clock_divider7seg (
+    .clk_in(clk_50MHz),
+    .clk_out(clk10k)
+);
+
+vga_module #(  
+        // .ADDR_WIDTH(ADDR_WIDTH),
+        // .DATA_WIDTH(DATA_WIDTH),
+        // .DEPTH(DEPTH),
+        // .HSYNC_CLKS(HSYNC_CLKS),
+        // .HSYNC_DISPLAY(HSYNC_DISPLAY),
+        // .HSYNC_PULSE(HSYNC_PULSE),
+        // .HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH),
+        // .HSYNC_BACK_PORCH(HSYNC_BACK_PORCH),
+        // .VSYNC_LINES(VSYNC_LINES) ,
+        // .VSYNC_DISPLAY(VSYNC_DISPLAY) ,
+        // .VSYNC_PULSE(VSYNC_PULSE) ,
+        // .VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
+        // .VSYNC_BACK_PORCH(VSYNC_BACK_PORCH) 
+) vga_module1 (
+    .clk(clk_25MHz),
+    .o_vgaRed(vgaRed),
+    .o_vgaBlue(vgaBlue),
+    .o_vgaGreen(vgaGreen),
+    .o_Hsync(Hsync),
+    .o_Vsync(Vsync),
+    .o_display(),
+    .o_addr_rd(),
+    .i_data_rd()
+   );

 endmodule
@@ -1,6 +1,19 @@
-// This file is Test Bench for top_vga_mem module
-//  
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - Test Bench for top module
+//
+// Detailed module description:
+// This file is Test Bench for top module
 // 
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////

 // 100MHz clock on Basys3 -> 10ns period
 // 50% duty cycle 5ns HIGH and 5ns LOW
@@ -0,0 +1,89 @@
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - vertical counter
+//
+// Detailed module description:
+//
+// 
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////
+module vertical_counter #( 
+    parameter
+        VSYNC_LINES = 521,
+        VSYNC_DISPLAY = 480,
+        VSYNC_PULSE = 2,
+        VSYNC_FRONT_PORCH = 10,
+        VSYNC_BACK_PORCH = 29
+    )(
+        //input clk,
+        input i_Hsync,
+        output o_Vsync,
+        output o_v_display,
+        output [8:0] o_v_line
+        );
+//----------Internal registers, constants and wariables-----
+reg vsync_reg = 1'b1;
+reg [9:0] counter_reg = 'h0;
+reg [8:0] counter_line_reg = 'h0;
+reg [2:0] r_state=VS_FRONT_PORCH, r_next=VS_FRONT_PORCH;
+localparam [2:0]        VS_FRONT_PORCH  = 'h0,
+                        VS_PULSE        = 'h1,
+                        VS_BACK_PORCH   = 'h2,
+                        VS_DISPLAY      = 'h3;
+
+//---------state register sequential always block-----------
+always @(posedge i_Hsync ) begin
+        r_state <= r_next; 
+end
+
+//----next state & outputs, combinational always block------
+always@(posedge i_Hsync) begin
+  counter_reg <= counter_reg + 1;
+
+    case (r_state)
+      VS_FRONT_PORCH: begin
+        vsync_reg <= 1'b1;
+        if(counter_reg ==   VSYNC_FRONT_PORCH - 2)
+            r_next <= VS_PULSE;
+      end
+      VS_PULSE:begin
+        vsync_reg <= 1'b0;
+        if(counter_reg ==   VSYNC_FRONT_PORCH +
+                            VSYNC_PULSE - 2)
+            r_next <= VS_BACK_PORCH;
+      end
+      VS_BACK_PORCH:begin
+        vsync_reg <= 1'b1;
+        if(counter_reg ==   VSYNC_FRONT_PORCH +
+                            VSYNC_PULSE +
+                            VSYNC_BACK_PORCH - 2) begin
+            r_next <= VS_DISPLAY;
+            counter_line_reg <= 'h0;
+            end
+      end
+      VS_DISPLAY:begin
+        vsync_reg <= 1'b1;
+        counter_line_reg <= counter_line_reg + 1;
+        if(counter_reg ==   VSYNC_FRONT_PORCH +
+                            VSYNC_PULSE +
+                            VSYNC_BACK_PORCH +
+                            VSYNC_DISPLAY - 1) begin
+            r_next <= VS_FRONT_PORCH;
+            counter_reg <= 'h0;
+        end
+      end
+    endcase
+end
+
+assign o_Vsync = vsync_reg;
+assign o_v_display = (counter_line_reg >= 1 && counter_line_reg <= VSYNC_DISPLAY) ? 1'b1 : 1'b0 ;
+assign o_v_line = counter_line_reg  - 1 ;
+
+endmodule
@@ -0,0 +1,92 @@
+///////////////////////////////////////////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 04.04.2020
+// Project name - Audio FFT on FPGA
+// Module name - VGA module
+//
+// Detailed module description:
+//
+// 
+//
+// Revision:
+// A - initial design
+// B - 
+// C - 
+//
+///////////////////////////////////////////////////////////////////
+module vga_module#( 
+    parameter
+        ADDR_WIDTH = 17, 
+        DATA_WIDTH = 12, 
+        DEPTH =  76_800, // 307_200,//
+        HSYNC_CLKS = 800,
+        HSYNC_DISPLAY = 640,
+        HSYNC_PULSE = 96,
+        HSYNC_FRONT_PORCH = 16,
+        HSYNC_BACK_PORCH = 48,
+        VSYNC_LINES = 521,
+        VSYNC_DISPLAY = 480,
+        VSYNC_PULSE = 2,
+        VSYNC_FRONT_PORCH = 10,
+        VSYNC_BACK_PORCH = 29
+    )(
+        input clk,
+        output [3:0] o_vgaRed,
+        output [3:0] o_vgaBlue,
+        output [3:0] o_vgaGreen,
+        output o_Hsync,
+        output o_Vsync,
+        output o_display,
+        output [ADDR_WIDTH-1:0] o_addr_rd,
+        input [DATA_WIDTH-1:0] i_data_rd
+        );
+
+//-------Internal registers and wires--------------
+wire w_v_display;
+wire w_h_display;
+wire [9:0] pixel;
+wire [8:0] line;
+
+//-------sub modules-------------------------------
+
+horizontal_counter #( 
+        .HSYNC_CLKS(HSYNC_CLKS) ,
+        .HSYNC_DISPLAY(HSYNC_DISPLAY) ,
+        .HSYNC_PULSE(HSYNC_PULSE) ,
+        .HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH) ,
+        .HSYNC_BACK_PORCH(HSYNC_BACK_PORCH) 
+    ) horizontal_counter1 (
+        .clk(clk),
+        .o_Hsync(o_Hsync),
+        .o_h_display(w_h_display),
+        .o_h_pixel(pixel)
+        );
+
+vertical_counter #( 
+        .VSYNC_LINES(VSYNC_LINES) ,
+        .VSYNC_DISPLAY(VSYNC_DISPLAY) ,
+        .VSYNC_PULSE(VSYNC_PULSE) ,
+        .VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
+        .VSYNC_BACK_PORCH(VSYNC_BACK_PORCH) 
+    ) vertical_counter1 (
+        //.clk(clk),
+        .i_Hsync(o_Hsync),
+        .o_Vsync(o_Vsync),
+        .o_v_display(w_v_display),
+        .o_v_line(line)
+        );
+
+assign o_display = (w_v_display && w_h_display) ;
+assign o_vgaRed = o_display ? i_data_rd[11:8] : 4'h0;
+assign o_vgaBlue = o_display ? i_data_rd[3:0] : 4'h0; 
+assign o_vgaGreen = o_display ? i_data_rd[7:4] : 4'h0;
+
+/*
+assign o_addr_rd = (((line*HSYNC_DISPLAY) + pixel + 1) == HSYNC_DISPLAY * VSYNC_DISPLAY ) ?
+                        'h0 : ((line[8:1]) * HSYNC_DISPLAY/2 ) + pixel[9:1] + 1 ;   // get next pixel
+*/
+assign o_addr_rd =  
+                    ((line[8:1]) * 'd320 ) + pixel[9:1];// + 1;
+
+
+endmodule
Author	SHA1	Message	Date
Imants Pulkstenis	ad59f40a9d	Changes to Matlab model	2020-04-04 16:06:23 +03:00
Imants Pulkstenis	5f98346282	Add VGA module	2020-04-04 01:40:11 +03:00
Imants Pulkstenis	ab92a0c8a8	Initial commit for new branch	2020-04-04 00:16:44 +03:00
Imants PulkstenisandGitHub	b132a68ca2	Update README.md	2020-02-10 21:28:51 +02:00
Imants PulkstenisandGitHub	2b997daa7e	Merge pull request #1 from Clockfix/add-license-1 Create LICENSE	2020-02-10 21:19:15 +02:00
Imants PulkstenisandGitHub	ac81b247d7	Create LICENSE	2020-02-10 21:19:05 +02:00
Imants PulkstenisandGitHub	575e4fee34	Update README.md	2020-02-10 21:06:18 +02:00
Imants Pulkstenis	c9e3a92ccb	Trying to fix audio issues	2020-01-21 21:26:29 +02:00
Imants Pulkstenis	e8095a4e68	add test beches	2020-01-21 21:23:47 +02:00
Imants Pulkstenis	bb79fe8730	Updated myfft3 file. Add calculations using fixed point integers and seperatly calculated real and imaginary numbers	2019-12-27 17:19:28 +02:00
Imants Pulkstenis	1a2289d877	minor changes	2019-12-27 13:17:42 +02:00
Aleksejs Mirnijs	6a422ee888	updatet figure plot Added xlim to figure(1)	2019-12-27 06:39:48 +02:00
Aleksejs Mirnijs	cf30046dbf	Added check for fftLength and some code minor updates	2019-12-25 15:50:56 +02:00
Aleksejs Mirnijs	e04020511a	Corrected separately complex number counting.	2019-12-25 11:08:18 +02:00
Aleksejs Mirnijs	790c73cab6	Updated comments	2019-12-23 15:06:02 +02:00
Aleksejs Mirnijs	f876a6a77a	Works separately with Real & Imag parts	2019-12-23 14:58:47 +02:00
Aleksejs Mirnijs	f1946c3b19	Corrected fft matlab code FFT Butterfly 4-1024 point code	2019-12-23 13:40:27 +02:00
Imants PulkstenisandGitHub	2ca0dd08ee	upload photo	2019-12-15 21:50:54 +02:00
Imants Pulkstenis	ae6b8e4ef9	add matlab files	2019-12-15 14:24:12 +02:00
Imants Pulkstenis	6519459430	treshold change	2019-12-03 22:48:43 +02:00
Imants Pulkstenis	9701ead6d3	Main clk speed changed from 25MHz to 50MHz add LEDs (outputs data from effects controler) add switches to control cliping treshold	2019-12-03 22:41:14 +02:00
Imants Pulkstenis	c86c2a267b	Merge branch 'master' of https://github.com/Clockfix/audio_effects_FPGA	2019-11-25 21:11:18 +02:00
Imants Pulkstenis	888bc47cd5	effect mixer update	2019-11-25 21:10:31 +02:00
Imants PulkstenisandGitHub	31c2b30c5a	Update README.md	2019-11-24 22:22:11 +02:00
Imants PulkstenisandGitHub	97649d2265	Update README.md	2019-11-24 22:13:20 +02:00
Imants PulkstenisandGitHub	85553b8660	Update README.md	2019-11-24 22:12:53 +02:00
Imants PulkstenisandGitHub	ce694c9844	Update README.md	2019-11-24 22:09:00 +02:00
Imants Pulkstenis	11c36aec2d	add effect mixer module and posibility to switch effects	2019-11-24 21:59:44 +02:00
Imants Pulkstenis	518bbe43cb	add flipflop module	2019-11-24 19:27:46 +02:00
Imants PulkstenisandGitHub	5e318949b6	Update README.md	2019-11-24 01:49:00 +02:00
Imants Pulkstenis	2d9f369ae9	readme commit	2019-11-24 01:44:24 +02:00
Imants Pulkstenis	60b57ed374	Merge branch 'master' of https://github.com/Clockfix/audio_effects_FPGA	2019-11-24 01:43:50 +02:00
Imants Pulkstenis	edf1ece511	Clipping effect now working	2019-11-24 01:43:20 +02:00
Imants PulkstenisandGitHub	cea943ba27	Update README.md	2019-11-23 23:05:41 +02:00
Imants PulkstenisandGitHub	af24d9fb43	Update README.md	2019-11-23 23:05:27 +02:00
Imants PulkstenisandGitHub	499869df4f	Update README.md	2019-11-23 23:03:15 +02:00
Imants PulkstenisandGitHub	12afd25ebf	Update README.md	2019-11-23 23:01:37 +02:00
Imants Pulkstenis	45caf399a1	readme file commit	2019-11-23 23:00:09 +02:00
Imants Pulkstenis	65b1690a47	Effect module added	2019-11-23 22:47:53 +02:00
Imants PulkstenisandGitHub	ee7edb0638	Update README.md	2019-11-22 01:02:10 +02:00
Imants PulkstenisandGitHub	131dee3643	Update README.md	2019-11-22 01:00:33 +02:00
Imants PulkstenisandGitHub	43d37fb9ad	Update README.md	2019-11-22 01:00:13 +02:00
Imants Pulkstenis	15dbd68ee2	Add fifo memory size variable.	2019-11-22 00:49:32 +02:00
Imants Pulkstenis	07cfe9893d	fifo module now working in loopback mode	2019-11-21 23:01:00 +02:00
Imants Pulkstenis	b8bfb00389	add fifo memory block	2019-11-21 22:21:35 +02:00
Imants Pulkstenis	4fc31319df	delete fifo files	2019-11-21 21:04:09 +02:00
Imants Pulkstenis	acef4ab3f2	update fifo files	2019-11-21 21:02:10 +02:00
Imants Pulkstenis	681d20fbf4	add FIFO files	2019-11-20 21:09:14 +02:00