Initial commit
This commit is contained in:
Imants Pulkstenis
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## This file is a general .xdc for the Basys3 rev B board
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock signal
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#set_property PACKAGE_PIN W5 [get_ports clk]
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#set_property IOSTANDARD LVCMOS33 [get_ports clk]
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#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
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## Switches
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#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
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#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
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#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
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#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
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#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
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#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
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#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
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#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
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#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
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#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
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#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
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#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
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#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
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#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
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#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
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#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
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## LEDs
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#set_property PACKAGE_PIN U16 [get_ports {led[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
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#set_property PACKAGE_PIN E19 [get_ports {led[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
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#set_property PACKAGE_PIN U19 [get_ports {led[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
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#set_property PACKAGE_PIN V19 [get_ports {led[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
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#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
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#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
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#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
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#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
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#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
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#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
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#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
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#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
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#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
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#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
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#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
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#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
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##7 segment display
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#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
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#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
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#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
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#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
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#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
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#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
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#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
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#set_property PACKAGE_PIN V7 [get_ports dp]
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#set_property IOSTANDARD LVCMOS33 [get_ports dp]
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#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
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#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
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#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
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#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
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##Buttons
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#set_property PACKAGE_PIN U18 [get_ports btnC]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
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#set_property PACKAGE_PIN T18 [get_ports btnU]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
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#set_property PACKAGE_PIN W19 [get_ports btnL]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
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#set_property PACKAGE_PIN T17 [get_ports btnR]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
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#set_property PACKAGE_PIN U17 [get_ports btnD]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
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##Pmod Header JA
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##Sch name = JA1
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#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
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##Sch name = JA2
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#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
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##Sch name = JA3
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#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
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##Sch name = JA4
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#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
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##Sch name = JA7
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#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
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##Sch name = JA8
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#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
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##Sch name = JA9
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#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
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##Sch name = JA10
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#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
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##Pmod Header JB
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##Sch name = JB1
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#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
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##Sch name = JB2
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#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
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##Sch name = JB3
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#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
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##Sch name = JB4
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#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
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##Sch name = JB7
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#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
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##Sch name = JB8
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#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
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##Sch name = JB9
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#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
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##Sch name = JB10
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#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
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##Pmod Header JC
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##Sch name = JC1
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#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
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##Sch name = JC2
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#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
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##Sch name = JC3
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#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
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##Sch name = JC4
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#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
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##Sch name = JC7
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#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
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##Sch name = JC8
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#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
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##Sch name = JC9
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#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
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##Sch name = JC10
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#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
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##Pmod Header JXADC
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##Sch name = XA1_P
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#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
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##Sch name = XA2_P
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#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
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##Sch name = XA3_P
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#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
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##Sch name = XA4_P
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#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
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##Sch name = XA1_N
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#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
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##Sch name = XA2_N
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#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
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##Sch name = XA3_N
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#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
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##Sch name = XA4_N
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#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
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##VGA Connector
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#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
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#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
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#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
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#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
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#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
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#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
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#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
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#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
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#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
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#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
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#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
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#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
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#set_property PACKAGE_PIN P19 [get_ports Hsync]
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#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
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#set_property PACKAGE_PIN R19 [get_ports Vsync]
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#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
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##USB-RS232 Interface
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#set_property PACKAGE_PIN B18 [get_ports RsRx]
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#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
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#set_property PACKAGE_PIN A18 [get_ports RsTx]
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#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
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##USB HID (PS/2)
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#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
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#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
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#set_property PULLUP true [get_ports PS2Clk]
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#set_property PACKAGE_PIN B17 [get_ports PS2Data]
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#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
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#set_property PULLUP true [get_ports PS2Data]
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##Quad SPI Flash
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##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
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##STARTUPE2 primitive.
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#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
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#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
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#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
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#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
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#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
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#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
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@@ -0,0 +1,28 @@
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// This module devide FPGA input clock
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// by DIVIDER. Result is 50% duty cicle
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// pulses.
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//
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//
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module clock_divider #(
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parameter DIVIDER =2,
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parameter WIDTH =2
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) (
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input clk,
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output clk_out);
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reg state=1'b0, next_state=1'b1;
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reg [WIDTH-1:0] counter = DIVIDER-1 ;
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always@(posedge clk)begin
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state <= next_state;
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if ( counter == 0) begin
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next_state <= ~next_state;
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counter <= DIVIDER-1;
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end
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else if (counter >= 0 )
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counter <= counter - 1;
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end
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assign clk_out = state;
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endmodule
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@@ -0,0 +1,40 @@
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// `timescale [time unit] / [time precision]
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||||
`timescale 10 ps / 1 ps
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||||
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`include "clock_divider_param.v"
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module clock_divider_param_tb ();
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reg clk = 1'b0;
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wire enable;
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|
||||
always #1 clk <= ~clk;
|
||||
|
||||
initial
|
||||
begin
|
||||
#100;
|
||||
$finish();
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
$display(" ");
|
||||
$display("----------------------------------------------");
|
||||
$display(" Starting Testbench...");
|
||||
$dumpfile("wave.vcd");
|
||||
$dumpvars(0);
|
||||
$display("----------------------------------------------");
|
||||
$display(" ");
|
||||
end
|
||||
|
||||
clock_divider #(
|
||||
.DIVIDER(2),
|
||||
.WIDTH(2)
|
||||
) test_unit1 (
|
||||
.clk(clk),
|
||||
.enable(enable)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,31 @@
|
||||
// This module devide FPGA input clock
|
||||
// by DIVIDER.
|
||||
//
|
||||
//
|
||||
module clock_enable_param #(
|
||||
parameter WAIT =1,
|
||||
parameter WIDTH =1
|
||||
) (
|
||||
input clk,
|
||||
output enable);
|
||||
|
||||
reg state=1'b0;
|
||||
reg [WIDTH-1:0] counter = 1'b0 ;
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(counter == 0)begin
|
||||
if (state == 1) begin
|
||||
state <= 0;
|
||||
counter <= WAIT - 1;
|
||||
end
|
||||
else begin
|
||||
state <= 1;
|
||||
counter <= 0;
|
||||
end
|
||||
end
|
||||
else counter <= counter -1;
|
||||
end
|
||||
|
||||
assign enable = state;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,61 @@
|
||||
`include "clock_enable_param.v"
|
||||
|
||||
module clock_enable_tb();
|
||||
|
||||
reg clk = 1'b0;
|
||||
wire enable0;
|
||||
wire enable1;
|
||||
wire enable2;
|
||||
wire enable3;
|
||||
|
||||
always #1 clk <= ~clk;
|
||||
|
||||
initial
|
||||
begin
|
||||
#100;
|
||||
$finish();
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
$display(" ");
|
||||
$display("----------------------------------------------");
|
||||
$display(" Starting Testbench...");
|
||||
$dumpfile("wave.vcd");
|
||||
$dumpvars(0);
|
||||
$display("----------------------------------------------");
|
||||
$display(" ");
|
||||
end
|
||||
|
||||
clock_enable_param test_unit0(
|
||||
.clk(clk),
|
||||
.enable(enable0)
|
||||
);
|
||||
|
||||
clock_enable_param #(
|
||||
.WAIT(2),
|
||||
.WIDTH(4)
|
||||
) test_unit1(
|
||||
.clk(clk),
|
||||
.enable(enable1)
|
||||
);
|
||||
|
||||
clock_enable_param #(
|
||||
.WAIT(3),
|
||||
.WIDTH(8)
|
||||
)test_unit2(
|
||||
.clk(clk),
|
||||
.enable(enable2)
|
||||
);
|
||||
|
||||
clock_enable_param #(
|
||||
.WAIT(9),
|
||||
.WIDTH(8)
|
||||
)test_unit3(
|
||||
.clk(clk),
|
||||
.enable(enable3)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,24 @@
|
||||
module debounce_switch(
|
||||
input clk,
|
||||
input i_switch,
|
||||
output o_switch);
|
||||
|
||||
parameter c_debounce_limit=250000;// 10ms at 25MHz
|
||||
|
||||
reg r_state=1'b0;
|
||||
reg [17:0] r_count = 0;
|
||||
|
||||
always@(posedge clk)begin
|
||||
if (i_switch != r_state && r_count < c_debounce_limit)
|
||||
r_count <= r_count +1; //counter
|
||||
else if (r_count == c_debounce_limit)begin
|
||||
r_count <=0;
|
||||
r_state <= i_switch;
|
||||
end
|
||||
else
|
||||
r_count<=0;
|
||||
end
|
||||
|
||||
assign o_switch=r_state;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,46 @@
|
||||
// TOP module
|
||||
//
|
||||
//
|
||||
// `include "clock_divider_param.v"
|
||||
// `include "clock_enable_param.v"
|
||||
|
||||
|
||||
module top #( parameter
|
||||
//pattern generator paremater
|
||||
SPEED = 300,
|
||||
//enable signal parameters
|
||||
WAIT = 1,
|
||||
WAIT_WIDTH = 2,
|
||||
)(
|
||||
input clk
|
||||
);
|
||||
|
||||
//------internal wires and registers--------
|
||||
wire w_enable;
|
||||
|
||||
wire clk50;
|
||||
|
||||
//-----sub modules--------------------------
|
||||
clock_enable_param #(
|
||||
.WAIT(WAIT),
|
||||
.WIDTH(WAIT_WIDTH)
|
||||
) clock_enable1 (
|
||||
.clk(clk),
|
||||
.enable(w_enable)
|
||||
);
|
||||
|
||||
clock_divider #(
|
||||
.DIVIDER(1),
|
||||
.WIDTH(3)
|
||||
) clk50mhz_gen (
|
||||
.clk(clk),
|
||||
.clk_out(clk50)
|
||||
);
|
||||
|
||||
debounce_switch debounce_switch_reset(
|
||||
.clk(clk),
|
||||
.i_switch(),
|
||||
.o_switch()
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,593 @@
|
||||
// This file is Test Bench for top_vga_mem module
|
||||
//
|
||||
//
|
||||
|
||||
// 100MHz clock on Basys3 -> 10ns period
|
||||
// 50% duty cycle 5ns HIGH and 5ns LOW
|
||||
//`timescale [time unit] / [time precision]
|
||||
`timescale 10 ns / 1ns
|
||||
|
||||
//sub modules
|
||||
`include "clock_divider_param.v"
|
||||
`include "clock_enable_param.v"
|
||||
`include "blockram.v"
|
||||
`include "pattern_gen.v"
|
||||
`include "vga_module.v"
|
||||
`include "horizontal_counter.v"
|
||||
`include "vertical_counter.v"
|
||||
`include "UART_Loopback_module.v"
|
||||
`include "UART_TX.v"
|
||||
`include "UART_RX.v"
|
||||
`include "7segment.v"
|
||||
`include "com_to_mem_FSM_hex.v"
|
||||
`include "com_to_mem_module.v"
|
||||
`include "ov7670_top.v"
|
||||
`include "debounce_switch.v"
|
||||
`include "ov7670_capture.v"
|
||||
`include "ov7670_controller.v"
|
||||
`include "imag_procesor.v"
|
||||
`include "default_reg_writer.v"
|
||||
`include "i2c_sender.v"
|
||||
`include "ov7670_registers.v"
|
||||
`include "imag_save.v"
|
||||
`include "rgb2gray.v"
|
||||
`include "imag_transform.v"
|
||||
`include "reg_reader.v"
|
||||
`include "address_gen.v"
|
||||
`include "overlay.v"
|
||||
`include "two_cam_one_screen.v"
|
||||
`include "lookuptable.v"
|
||||
|
||||
//top module
|
||||
`include "top.v"
|
||||
|
||||
module top_vga_mem_tb#( parameter
|
||||
WAIT = 1,
|
||||
WAIT_WIDTH = 2,
|
||||
SPEED = 2,
|
||||
//memory parameters
|
||||
ADDR_WIDTH = 17, //19, //
|
||||
DATA_WIDTH = 12,
|
||||
DEPTH = 307_200//76_800, //
|
||||
)();
|
||||
|
||||
reg clk = 1'b0;
|
||||
reg pclk = 1'b0;
|
||||
reg hs = 1'b0;
|
||||
reg vs = 1'b0;
|
||||
|
||||
// 50% duty cycle clock
|
||||
always #0.5 clk <= ~clk;
|
||||
always #2 pclk <= ~pclk;
|
||||
always #100 hs <= 1;
|
||||
always #102 hs <= 0;
|
||||
always #200 vs <= 1;
|
||||
always #202 vs <= 0;
|
||||
|
||||
reg RsRx;
|
||||
wire RsTx;
|
||||
|
||||
top_vga_mem #(
|
||||
.SPEED(SPEED),
|
||||
.ADDR_WIDTH(ADDR_WIDTH),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.DEPTH(DEPTH)
|
||||
)Test_Unit(
|
||||
.clk(clk),
|
||||
.RsRx(RsRx),
|
||||
.RsTx(RsTx),
|
||||
.sw(3'b101),
|
||||
.ov7670_cam1_pclk(pclk),
|
||||
.ov7670_cam2_pclk(pclk),
|
||||
.ov7670_cam1_vs(vs),
|
||||
.ov7670_cam1_hs(hs),
|
||||
.ov7670_cam2_vs(vs),
|
||||
.ov7670_cam2_hs(hs),
|
||||
.im_p(9'b00_01_01_000)
|
||||
);
|
||||
|
||||
initial begin
|
||||
// starting UART transition
|
||||
// h70 -> P
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h32 -> 2
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h63 -> c
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h38 -> 8
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
|
||||
#868 RsRx = 1;
|
||||
|
||||
#10_000;
|
||||
|
||||
// h72 -> r
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
|
||||
// h35 -> 5
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h35 -> 5
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
#10_000;
|
||||
|
||||
// h70 -> p
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h35 -> 5
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h35 -> 5
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h32 -> 2
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h35 -> 5
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h35 -> 5
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
#10_000;
|
||||
|
||||
// h72 -> r
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h30 -> 0
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h35 -> 5
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
// h35 -> 5
|
||||
#9000;
|
||||
#0 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 1;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 0;
|
||||
#868 RsRx = 1;
|
||||
|
||||
#10_000;
|
||||
|
||||
end
|
||||
|
||||
|
||||
initial begin
|
||||
#000_001;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
#030_000;
|
||||
$display("*");
|
||||
|
||||
$display(" ");
|
||||
$display("Use this command to open timing diagram:");
|
||||
$display("gtkwave -f wave.vcd");
|
||||
$display("----------------------------------------------");
|
||||
$finish();
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
$display(" ");
|
||||
$display("----------------------------------------------");
|
||||
$display(" Starting Testbench...");
|
||||
$dumpfile("wave.vcd");
|
||||
$dumpvars(0);
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user