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c8581dbe6858f7cf2b5f87df302651985e0de57c
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Author SHA1 Message Date
Imants Pulkstenis c8581dbe68 ps4 added 2020-03-29 21:08:14 +03:00
Imants Pulkstenis f19b7c8ca1 Add Lab work No2 2020-03-25 00:08:31 +02:00
Imants Pulkstenis 27e63599f4 Add Lab work No1 2020-03-24 20:23:39 +02:00
Imants Pulkstenis 8ee46486e8 add *.vcd file for GTKWave 2020-02-27 20:50:56 +02:00
Imants Pulkstenis a29e888084 FSM picture 2020-02-24 00:53:46 +02:00
Imants Pulkstenis 5d5a40afe4 minor changes 2020-02-24 00:18:10 +02:00
Imants Pulkstenis 71b037e9fe file raname 2020-02-24 00:14:20 +02:00
Imants Pulkstenis 22851efc71 VHDL Problem set 3 2020-02-23 23:58:12 +02:00
Imants Pulkstenis fcc5a0b050 Compleated Verilog file and started working un VHDL 2020-02-23 22:40:30 +02:00
Imants Pulkstenis 470628a6ac readme.md 2020-02-23 19:28:46 +02:00
Imants Pulkstenis d766660062 changes in readme.md 2020-02-23 19:22:15 +02:00
Imants Pulkstenis c42e0654da add aditional else if for MR_GREEN_1 state 2020-02-23 19:18:36 +02:00
Imants Pulkstenis e6cbc865aa Add Problem set 3 2020-02-23 19:12:32 +02:00
Imants Pulkstenis 40fa3d7bda ALU NAND and NOR rework 2020-02-16 18:40:37 +02:00
Imants Pulkstenis 6d158867bb remove overflow flag 2020-02-16 18:36:07 +02:00
Imants Pulkstenis 818b11e338 add ps02_siggen. file 2020-02-16 16:11:37 +02:00
Imants Pulkstenis 23c36a292b code debug 2020-02-16 15:28:19 +02:00
Imants Pulkstenis 4b4e427c4a ALU flag operation added 2020-02-16 15:26:56 +02:00
Imants Pulkstenis c715347ee5 Merge branch 'master' of https://github.com/Clockfix/RTR532 2020-02-16 13:26:05 +02:00
Imants Pulkstenis 3c38cb75a8 Task 2 - done 2020-02-16 13:22:57 +02:00
Imants Pulkstenis db3eac9c03 add decription 2020-02-16 13:13:02 +02:00
Imants Pulkstenis e2311d5b73 add alu.v file 2020-02-16 13:11:07 +02:00
Imants Pulkstenis 609a9292b3 Task1 done. Code debuging 2020-02-16 12:20:58 +02:00
Imants Pulkstenis 4eb5c37b4f add ps02.v top module in Verilog 2020-02-16 12:09:38 +02:00
Imants Pulkstenis 804dc0eca7 Merge branch 'master' of https://github.com/Clockfix/RTR532 2020-02-16 11:35:51 +02:00
Imants Pulkstenis 9d51d87b7f Problem set 2 added 2020-02-16 11:34:03 +02:00
Imants Pulkstenis 8def5cd7c0 changes in vhdl file and add LUT.jpg file 2020-02-10 22:58:48 +02:00
Imants Pulkstenis 1f0ce57d47 initial commit 2020-02-10 22:03:20 +02:00
Imants Pulkstenis b6f75f6297 Initial commit 2020-02-10 21:40:50 +02:00