imants/RTR532
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13 Commits
Author SHA1 Message Date
Imants Pulkstenis 1598022c70 DDS module and test bench finished 2020-04-01 21:35:27 +03:00
Imants Pulkstenis 40fa3d7bda ALU NAND and NOR rework 2020-02-16 18:40:37 +02:00
Imants Pulkstenis 6d158867bb remove overflow flag 2020-02-16 18:36:07 +02:00
Imants Pulkstenis 818b11e338 add ps02_siggen. file 2020-02-16 16:11:37 +02:00
Imants Pulkstenis 23c36a292b code debug 2020-02-16 15:28:19 +02:00
Imants Pulkstenis 4b4e427c4a ALU flag operation added 2020-02-16 15:26:56 +02:00
Imants Pulkstenis c715347ee5 Merge branch 'master' of https://github.com/Clockfix/RTR532 2020-02-16 13:26:05 +02:00
Imants Pulkstenis 3c38cb75a8 Task 2 - done 2020-02-16 13:22:57 +02:00
Imants Pulkstenis db3eac9c03 add decription 2020-02-16 13:13:02 +02:00
Imants Pulkstenis e2311d5b73 add alu.v file 2020-02-16 13:11:07 +02:00
Imants Pulkstenis 609a9292b3 Task1 done. Code debuging 2020-02-16 12:20:58 +02:00
Imants Pulkstenis 4eb5c37b4f add ps02.v top module in Verilog 2020-02-16 12:09:38 +02:00
Imants Pulkstenis 9d51d87b7f Problem set 2 added 2020-02-16 11:34:03 +02:00