DDS module and test bench finished

2020-04-01 21:35:27 +03:00
parent c8581dbe68
commit 1598022c70
6 changed files with 246 additions and 67 deletions
@@ -7,7 +7,7 @@
 // Detailed module description:
 //
 // This module generete clk signal for 
-// for tom podule of ps02 project
+// top module of ps02 project
 // The test is executed using Icarus Verilog!
 // 
 // The result can be evaluated in GTKwave application.