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Trying to fix audio issues

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Imants Pulkstenis
2020-01-21 21:26:29 +02:00
parent e8095a4e68
commit c9e3a92ccb
6 changed files with 52 additions and 34 deletions
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clipping.v
+26 -17
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@@ -13,11 +13,12 @@ module clipping_effect #( parameter
); );
//-------------Internal Constants--------------------------- //-------------Internal Constants---------------------------
localparam [2:0] IDLE = 'd0, localparam [1:0] IDLE = 'd0,
CLIP = 'd1, CLIP = 'd1,
OUTPUT = 'd2; OUTPUT = 'd2,
CLEAR = 'd3;
reg [2:0] r_state=IDLE, r_next=IDLE; reg [1:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0; reg signed [data_width-1: 0] r_data = 'b0;
reg [data_width-1: 0] r_treshhold_p = 'b0; reg [data_width-1: 0] r_treshhold_p = 'b0;
@@ -32,12 +33,7 @@ assign o_data = r_data;
//---------state register sequential always block----------- //---------state register sequential always block-----------
always @(posedge clk ) begin always @(posedge clk ) begin
if (reset == 1) begin if (~reset) begin
// clear state
r_state <= IDLE;
r_next <= IDLE;
end
else begin
r_state <= r_next; r_state <= r_next;
end end
end end
@@ -45,7 +41,12 @@ end
//----next state & outputs, combinational always block------ //----next state & outputs, combinational always block------
always @(posedge clk ) begin always @(posedge clk ) begin
if (reset) begin
r_next <= IDLE;
r_read_enable <= 0; // redy to read data
r_data_valid <= 0;
end
else begin
case(r_state) case(r_state)
IDLE : begin IDLE : begin
if (i_data_ready == 1) begin if (i_data_ready == 1) begin
@@ -65,12 +66,12 @@ always @(posedge clk ) begin
CLIP : begin CLIP : begin
case (r_data[data_width-1]) case (r_data[data_width-1])
0 : begin // positive number 0 : begin // positive number
if (r_data > r_treshhold_p) if (r_data > r_treshhold_p) begin
r_data <= r_treshhold_p; r_data <= r_treshhold_p; end
end end
1 : begin // negative number 1 : begin // negative number
if (r_data < r_treshhold_n) if (r_data < r_treshhold_n) begin
r_data <= r_treshhold_n; r_data <= r_treshhold_n; end
end end
endcase endcase
r_next <= OUTPUT; r_next <= OUTPUT;
@@ -79,9 +80,9 @@ always @(posedge clk ) begin
end end
OUTPUT : begin OUTPUT : begin
if (i_read_done == 1) begin if (i_read_done == 1) begin
r_next <= IDLE; r_next <= CLEAR;
r_data_valid <= 0; r_data_valid <= 0;
r_read_enable <= 1; r_read_enable <= 0;
end end
else begin else begin
r_next <= OUTPUT; r_next <= OUTPUT;
@@ -89,9 +90,17 @@ always @(posedge clk ) begin
r_read_enable <= 0; // read disable r_read_enable <= 0; // read disable
end end
end end
default: r_next <= IDLE; // on error CLEAR : begin
r_next <= IDLE;
r_data_valid <= 0;
r_read_enable <= 1;
end
default: begin
r_next <= IDLE; // on error
end
endcase endcase
end end
end
effect_controler.v
+1 -1
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@@ -13,7 +13,7 @@ module effect_controler #( parameter
output signed [d_width-1: 0] o_r_data, output signed [d_width-1: 0] o_r_data,
output o_read_done, // read done from effects module output o_read_done, // read done from effects module
output o_read_ready, // ready read from reefects module output o_read_ready, // ready read from effects module
input [1:0] sw, // effect control swiches input [1:0] sw, // effect control swiches
effect_mixer.v
+1
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@@ -36,6 +36,7 @@ reg r_data_valid = 0;
assign o_read_done = r_read_done; assign o_read_done = r_read_done;
assign o_data_valid = r_data_valid; assign o_data_valid = r_data_valid;
assign o_data = r_data_norm; assign o_data = r_data_norm;
assign o_read_ready = r_read_ready;
//---------state register sequential always block----------- //---------state register sequential always block-----------
no_effect.v
+22 -13
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@@ -12,10 +12,11 @@ module no_effect #( parameter
); );
//-------------Internal Constants--------------------------- //-------------Internal Constants---------------------------
localparam [3:0] IDLE = 'd0, localparam [1:0] IDLE = 'd0,
OUTPUT = 'd1; OUTPUT = 'd1,
CLEAR = 'd3;
reg [3:0] r_state=IDLE, r_next=IDLE; reg [1:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0; reg signed [data_width-1: 0] r_data = 'b0;
reg r_read_enable = 0; reg r_read_enable = 0;
@@ -28,12 +29,7 @@ assign o_data = r_data;
//---------state register sequential always block----------- //---------state register sequential always block-----------
always @(posedge clk ) begin always @(posedge clk ) begin
if (reset == 1) begin if (~reset) begin
// clear state
r_state <= IDLE;
r_next <= IDLE;
end
else begin
r_state <= r_next; r_state <= r_next;
end end
end end
@@ -41,7 +37,12 @@ end
//----next state & outputs, combinational always block------ //----next state & outputs, combinational always block------
always @(posedge clk ) begin always @(posedge clk ) begin
if (reset) begin
r_next <= IDLE;
r_read_enable <= 0; // redy to read data
r_data_valid <= 0;
end
else begin
case(r_state) case(r_state)
IDLE : begin IDLE : begin
if (i_data_ready == 1) begin if (i_data_ready == 1) begin
@@ -58,9 +59,9 @@ always @(posedge clk ) begin
end end
OUTPUT : begin OUTPUT : begin
if (i_read_done == 1) begin if (i_read_done == 1) begin
r_next <= IDLE; r_next <= CLEAR;
r_data_valid <= 0; r_data_valid <= 0;
r_read_enable <= 1; r_read_enable <= 0;
end end
else begin else begin
r_next <= OUTPUT; r_next <= OUTPUT;
@@ -68,9 +69,17 @@ always @(posedge clk ) begin
r_read_enable <= 0; // read disable r_read_enable <= 0; // read disable
end end
end end
default: r_next <= IDLE; // on error CLEAR : begin
r_next <= IDLE;
r_data_valid <= 0;
r_read_enable <= 1;
end
default: begin
r_next <= IDLE; // on error
end
endcase endcase
end end
end
top.v
+1 -2
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@@ -38,8 +38,7 @@ wire master_clk; // 11.29 MHz master clock
wire clk_50MHz; // wire clk_50MHz; //
wire w_reset, w_reset1, w_reset2, w_reset3, wire w_reset, w_reset1, w_reset2;
w_reset4, w_reset5;
wire w_internal_reset; wire w_internal_reset;
wire signed [d_width-1: 0] r_data_tx; wire signed [d_width-1: 0] r_data_tx;
top_tb.v
+1 -1
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@@ -1,4 +1,4 @@
// This file is Test Bench for top_vga_mem module // This file is Test Bench for top module
// //
// //