diff --git a/clipping.v b/clipping.v index 2111648..48deaaa 100644 --- a/clipping.v +++ b/clipping.v @@ -13,11 +13,12 @@ module clipping_effect #( parameter ); //-------------Internal Constants--------------------------- -localparam [2:0] IDLE = 'd0, +localparam [1:0] IDLE = 'd0, CLIP = 'd1, - OUTPUT = 'd2; + OUTPUT = 'd2, + CLEAR = 'd3; -reg [2:0] r_state=IDLE, r_next=IDLE; +reg [1:0] r_state=IDLE, r_next=IDLE; reg signed [data_width-1: 0] r_data = 'b0; reg [data_width-1: 0] r_treshhold_p = 'b0; @@ -32,12 +33,7 @@ assign o_data = r_data; //---------state register sequential always block----------- always @(posedge clk ) begin - if (reset == 1) begin - // clear state - r_state <= IDLE; - r_next <= IDLE; - end - else begin + if (~reset) begin r_state <= r_next; end end @@ -45,7 +41,12 @@ end //----next state & outputs, combinational always block------ always @(posedge clk ) begin - + if (reset) begin + r_next <= IDLE; + r_read_enable <= 0; // redy to read data + r_data_valid <= 0; + end + else begin case(r_state) IDLE : begin if (i_data_ready == 1) begin @@ -65,12 +66,12 @@ always @(posedge clk ) begin CLIP : begin case (r_data[data_width-1]) 0 : begin // positive number - if (r_data > r_treshhold_p) - r_data <= r_treshhold_p; + if (r_data > r_treshhold_p) begin + r_data <= r_treshhold_p; end end 1 : begin // negative number - if (r_data < r_treshhold_n) - r_data <= r_treshhold_n; + if (r_data < r_treshhold_n) begin + r_data <= r_treshhold_n; end end endcase r_next <= OUTPUT; @@ -79,9 +80,9 @@ always @(posedge clk ) begin end OUTPUT : begin if (i_read_done == 1) begin - r_next <= IDLE; + r_next <= CLEAR; r_data_valid <= 0; - r_read_enable <= 1; + r_read_enable <= 0; end else begin r_next <= OUTPUT; @@ -89,8 +90,16 @@ always @(posedge clk ) begin r_read_enable <= 0; // read disable end end - default: r_next <= IDLE; // on error + CLEAR : begin + r_next <= IDLE; + r_data_valid <= 0; + r_read_enable <= 1; + end + default: begin + r_next <= IDLE; // on error + end endcase + end end diff --git a/effect_controler.v b/effect_controler.v index 52c6fc4..c7ced2e 100644 --- a/effect_controler.v +++ b/effect_controler.v @@ -13,7 +13,7 @@ module effect_controler #( parameter output signed [d_width-1: 0] o_r_data, output o_read_done, // read done from effects module - output o_read_ready, // ready read from reefects module + output o_read_ready, // ready read from effects module input [1:0] sw, // effect control swiches diff --git a/effect_mixer.v b/effect_mixer.v index 564e7ef..40884c9 100644 --- a/effect_mixer.v +++ b/effect_mixer.v @@ -36,6 +36,7 @@ reg r_data_valid = 0; assign o_read_done = r_read_done; assign o_data_valid = r_data_valid; assign o_data = r_data_norm; +assign o_read_ready = r_read_ready; //---------state register sequential always block----------- diff --git a/no_effect.v b/no_effect.v index ea049bb..db7545c 100644 --- a/no_effect.v +++ b/no_effect.v @@ -12,10 +12,11 @@ module no_effect #( parameter ); //-------------Internal Constants--------------------------- -localparam [3:0] IDLE = 'd0, - OUTPUT = 'd1; +localparam [1:0] IDLE = 'd0, + OUTPUT = 'd1, + CLEAR = 'd3; -reg [3:0] r_state=IDLE, r_next=IDLE; +reg [1:0] r_state=IDLE, r_next=IDLE; reg signed [data_width-1: 0] r_data = 'b0; reg r_read_enable = 0; @@ -28,12 +29,7 @@ assign o_data = r_data; //---------state register sequential always block----------- always @(posedge clk ) begin - if (reset == 1) begin - // clear state - r_state <= IDLE; - r_next <= IDLE; - end - else begin + if (~reset) begin r_state <= r_next; end end @@ -41,7 +37,12 @@ end //----next state & outputs, combinational always block------ always @(posedge clk ) begin - + if (reset) begin + r_next <= IDLE; + r_read_enable <= 0; // redy to read data + r_data_valid <= 0; + end + else begin case(r_state) IDLE : begin if (i_data_ready == 1) begin @@ -58,9 +59,9 @@ always @(posedge clk ) begin end OUTPUT : begin if (i_read_done == 1) begin - r_next <= IDLE; + r_next <= CLEAR; r_data_valid <= 0; - r_read_enable <= 1; + r_read_enable <= 0; end else begin r_next <= OUTPUT; @@ -68,8 +69,16 @@ always @(posedge clk ) begin r_read_enable <= 0; // read disable end end - default: r_next <= IDLE; // on error + CLEAR : begin + r_next <= IDLE; + r_data_valid <= 0; + r_read_enable <= 1; + end + default: begin + r_next <= IDLE; // on error + end endcase + end end diff --git a/top.v b/top.v index e481dbf..2febb7c 100644 --- a/top.v +++ b/top.v @@ -38,8 +38,7 @@ wire master_clk; // 11.29 MHz master clock wire clk_50MHz; // -wire w_reset, w_reset1, w_reset2, w_reset3, - w_reset4, w_reset5; +wire w_reset, w_reset1, w_reset2; wire w_internal_reset; wire signed [d_width-1: 0] r_data_tx; diff --git a/top_tb.v b/top_tb.v index fa451b7..d3ce802 100644 --- a/top_tb.v +++ b/top_tb.v @@ -1,4 +1,4 @@ -// This file is Test Bench for top_vga_mem module +// This file is Test Bench for top module // //