From a4121d16cdb0da5884e9b27ee4285498b2c75aba Mon Sep 17 00:00:00 2001 From: Imants Pulkstenis Date: Fri, 4 Oct 2019 23:40:15 +0300 Subject: [PATCH] Initial commit --- Basys3_Master.xdc | 295 +++++++++++++++++++ clock_divider_param.v | 28 ++ clock_divider_param_tb.v | 40 +++ clock_enable_param.v | 31 ++ clock_enable_tb.v | 61 ++++ debounce_switch.v | 24 ++ top.v | 46 +++ top_tb.v | 593 +++++++++++++++++++++++++++++++++++++++ 8 files changed, 1118 insertions(+) create mode 100644 Basys3_Master.xdc create mode 100644 clock_divider_param.v create mode 100644 clock_divider_param_tb.v create mode 100644 clock_enable_param.v create mode 100644 clock_enable_tb.v create mode 100644 debounce_switch.v create mode 100644 top.v create mode 100644 top_tb.v diff --git a/Basys3_Master.xdc b/Basys3_Master.xdc new file mode 100644 index 0000000..f64d631 --- /dev/null +++ b/Basys3_Master.xdc @@ -0,0 +1,295 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +#set_property PACKAGE_PIN W5 [get_ports clk] + #set_property IOSTANDARD LVCMOS33 [get_ports clk] + #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] + +## Switches +#set_property PACKAGE_PIN V17 [get_ports {sw[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +#set_property PACKAGE_PIN V16 [get_ports {sw[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +#set_property PACKAGE_PIN W16 [get_ports {sw[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +#set_property PACKAGE_PIN W17 [get_ports {sw[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +#set_property PACKAGE_PIN W15 [get_ports {sw[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +#set_property PACKAGE_PIN V15 [get_ports {sw[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +#set_property PACKAGE_PIN W14 [get_ports {sw[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +#set_property PACKAGE_PIN W13 [get_ports {sw[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +#set_property PACKAGE_PIN V2 [get_ports {sw[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +#set_property PACKAGE_PIN T3 [get_ports {sw[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +#set_property PACKAGE_PIN T2 [get_ports {sw[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +#set_property PACKAGE_PIN R3 [get_ports {sw[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +#set_property PACKAGE_PIN W2 [get_ports {sw[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +#set_property PACKAGE_PIN U1 [get_ports {sw[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +#set_property PACKAGE_PIN T1 [get_ports {sw[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +#set_property PACKAGE_PIN R2 [get_ports {sw[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + + +## LEDs +#set_property PACKAGE_PIN U16 [get_ports {led[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +#set_property PACKAGE_PIN E19 [get_ports {led[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +#set_property PACKAGE_PIN U19 [get_ports {led[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +#set_property PACKAGE_PIN V19 [get_ports {led[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +#set_property PACKAGE_PIN W18 [get_ports {led[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +#set_property PACKAGE_PIN U15 [get_ports {led[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +#set_property PACKAGE_PIN U14 [get_ports {led[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +#set_property PACKAGE_PIN V14 [get_ports {led[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +#set_property PACKAGE_PIN V13 [get_ports {led[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +#set_property PACKAGE_PIN V3 [get_ports {led[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +#set_property PACKAGE_PIN W3 [get_ports {led[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +#set_property PACKAGE_PIN U3 [get_ports {led[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +#set_property PACKAGE_PIN P3 [get_ports {led[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +#set_property PACKAGE_PIN N3 [get_ports {led[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +#set_property PACKAGE_PIN P1 [get_ports {led[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +#set_property PACKAGE_PIN L1 [get_ports {led[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] + + +##7 segment display +#set_property PACKAGE_PIN W7 [get_ports {seg[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +#set_property PACKAGE_PIN W6 [get_ports {seg[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +#set_property PACKAGE_PIN U8 [get_ports {seg[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +#set_property PACKAGE_PIN V8 [get_ports {seg[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +#set_property PACKAGE_PIN U5 [get_ports {seg[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +#set_property PACKAGE_PIN V5 [get_ports {seg[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +#set_property PACKAGE_PIN U7 [get_ports {seg[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +#set_property PACKAGE_PIN V7 [get_ports dp] + #set_property IOSTANDARD LVCMOS33 [get_ports dp] + +#set_property PACKAGE_PIN U2 [get_ports {an[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +#set_property PACKAGE_PIN U4 [get_ports {an[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +#set_property PACKAGE_PIN V4 [get_ports {an[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +#set_property PACKAGE_PIN W4 [get_ports {an[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] + + +##Buttons +#set_property PACKAGE_PIN U18 [get_ports btnC] + #set_property IOSTANDARD LVCMOS33 [get_ports btnC] +#set_property PACKAGE_PIN T18 [get_ports btnU] + #set_property IOSTANDARD LVCMOS33 [get_ports btnU] +#set_property PACKAGE_PIN W19 [get_ports btnL] + #set_property IOSTANDARD LVCMOS33 [get_ports btnL] +#set_property PACKAGE_PIN T17 [get_ports btnR] + #set_property IOSTANDARD LVCMOS33 [get_ports btnR] +#set_property PACKAGE_PIN U17 [get_ports btnD] + #set_property IOSTANDARD LVCMOS33 [get_ports btnD] + + + +##Pmod Header JA +##Sch name = JA1 +#set_property PACKAGE_PIN J1 [get_ports {JA[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +##Sch name = JA2 +#set_property PACKAGE_PIN L2 [get_ports {JA[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +##Sch name = JA3 +#set_property PACKAGE_PIN J2 [get_ports {JA[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +##Sch name = JA4 +#set_property PACKAGE_PIN G2 [get_ports {JA[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +##Sch name = JA7 +#set_property PACKAGE_PIN H1 [get_ports {JA[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +##Sch name = JA8 +#set_property PACKAGE_PIN K2 [get_ports {JA[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +##Sch name = JA9 +#set_property PACKAGE_PIN H2 [get_ports {JA[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +##Sch name = JA10 +#set_property PACKAGE_PIN G3 [get_ports {JA[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +##Sch name = JB1 +#set_property PACKAGE_PIN A14 [get_ports {JB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +##Sch name = JB2 +#set_property PACKAGE_PIN A16 [get_ports {JB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +##Sch name = JB3 +#set_property PACKAGE_PIN B15 [get_ports {JB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +##Sch name = JB4 +#set_property PACKAGE_PIN B16 [get_ports {JB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +##Sch name = JB7 +#set_property PACKAGE_PIN A15 [get_ports {JB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +##Sch name = JB8 +#set_property PACKAGE_PIN A17 [get_ports {JB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +##Sch name = JB9 +#set_property PACKAGE_PIN C15 [get_ports {JB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +##Sch name = JB10 +#set_property PACKAGE_PIN C16 [get_ports {JB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +##Sch name = JC1 +#set_property PACKAGE_PIN K17 [get_ports {JC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +##Sch name = JC2 +#set_property PACKAGE_PIN M18 [get_ports {JC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +##Sch name = JC3 +#set_property PACKAGE_PIN N17 [get_ports {JC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +##Sch name = JC4 +#set_property PACKAGE_PIN P18 [get_ports {JC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +##Sch name = JC7 +#set_property PACKAGE_PIN L17 [get_ports {JC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +##Sch name = JC8 +#set_property PACKAGE_PIN M19 [get_ports {JC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +##Sch name = JC9 +#set_property PACKAGE_PIN P17 [get_ports {JC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +##Sch name = JC10 +#set_property PACKAGE_PIN R18 [get_ports {JC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + +##Pmod Header JXADC +##Sch name = XA1_P +#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] +##Sch name = XA2_P +#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] +##Sch name = XA3_P +#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] +##Sch name = XA4_P +#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] +##Sch name = XA1_N +#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] +##Sch name = XA2_N +#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] +##Sch name = XA3_N +#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] +##Sch name = XA4_N +#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + +##VGA Connector +#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] +#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] +#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] +#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] +#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] +#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] +#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] +#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] +#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] +#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] +#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] +#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] +#set_property PACKAGE_PIN P19 [get_ports Hsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] +#set_property PACKAGE_PIN R19 [get_ports Vsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] + + +##USB-RS232 Interface +#set_property PACKAGE_PIN B18 [get_ports RsRx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] +#set_property PACKAGE_PIN A18 [get_ports RsTx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] + + +##USB HID (PS/2) +#set_property PACKAGE_PIN C17 [get_ports PS2Clk] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] + #set_property PULLUP true [get_ports PS2Clk] +#set_property PACKAGE_PIN B17 [get_ports PS2Data] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] + #set_property PULLUP true [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +#set_property PACKAGE_PIN K19 [get_ports QspiCSn] + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + diff --git a/clock_divider_param.v b/clock_divider_param.v new file mode 100644 index 0000000..23676c6 --- /dev/null +++ b/clock_divider_param.v @@ -0,0 +1,28 @@ +// This module devide FPGA input clock +// by DIVIDER. Result is 50% duty cicle +// pulses. +// +// +module clock_divider #( + parameter DIVIDER =2, + parameter WIDTH =2 +) ( + input clk, + output clk_out); + +reg state=1'b0, next_state=1'b1; +reg [WIDTH-1:0] counter = DIVIDER-1 ; + +always@(posedge clk)begin + state <= next_state; + if ( counter == 0) begin + next_state <= ~next_state; + counter <= DIVIDER-1; + end + else if (counter >= 0 ) + counter <= counter - 1; +end + +assign clk_out = state; + +endmodule \ No newline at end of file diff --git a/clock_divider_param_tb.v b/clock_divider_param_tb.v new file mode 100644 index 0000000..cb3ca22 --- /dev/null +++ b/clock_divider_param_tb.v @@ -0,0 +1,40 @@ +// `timescale [time unit] / [time precision] +`timescale 10 ps / 1 ps + +`include "clock_divider_param.v" + +module clock_divider_param_tb (); + +reg clk = 1'b0; +wire enable; + +always #1 clk <= ~clk; + + initial + begin + #100; + $finish(); + end + + initial + begin + $display(" "); + $display("----------------------------------------------"); + $display(" Starting Testbench..."); + $dumpfile("wave.vcd"); + $dumpvars(0); + $display("----------------------------------------------"); + $display(" "); + end + +clock_divider #( + .DIVIDER(2), + .WIDTH(2) + ) test_unit1 ( + .clk(clk), + .enable(enable) +); + + + +endmodule \ No newline at end of file diff --git a/clock_enable_param.v b/clock_enable_param.v new file mode 100644 index 0000000..f9fe52b --- /dev/null +++ b/clock_enable_param.v @@ -0,0 +1,31 @@ +// This module devide FPGA input clock +// by DIVIDER. +// +// +module clock_enable_param #( + parameter WAIT =1, + parameter WIDTH =1 +) ( + input clk, + output enable); + +reg state=1'b0; +reg [WIDTH-1:0] counter = 1'b0 ; + +always@(posedge clk)begin + if(counter == 0)begin + if (state == 1) begin + state <= 0; + counter <= WAIT - 1; + end + else begin + state <= 1; + counter <= 0; + end + end + else counter <= counter -1; +end + +assign enable = state; + +endmodule \ No newline at end of file diff --git a/clock_enable_tb.v b/clock_enable_tb.v new file mode 100644 index 0000000..a7d2da8 --- /dev/null +++ b/clock_enable_tb.v @@ -0,0 +1,61 @@ +`include "clock_enable_param.v" + +module clock_enable_tb(); + +reg clk = 1'b0; +wire enable0; +wire enable1; +wire enable2; +wire enable3; + +always #1 clk <= ~clk; + + initial + begin + #100; + $finish(); + end + + initial + begin + $display(" "); + $display("----------------------------------------------"); + $display(" Starting Testbench..."); + $dumpfile("wave.vcd"); + $dumpvars(0); + $display("----------------------------------------------"); + $display(" "); + end + +clock_enable_param test_unit0( + .clk(clk), + .enable(enable0) +); + +clock_enable_param #( + .WAIT(2), + .WIDTH(4) + ) test_unit1( + .clk(clk), + .enable(enable1) +); + +clock_enable_param #( + .WAIT(3), + .WIDTH(8) + )test_unit2( + .clk(clk), + .enable(enable2) +); + +clock_enable_param #( + .WAIT(9), + .WIDTH(8) + )test_unit3( + .clk(clk), + .enable(enable3) +); + + + +endmodule \ No newline at end of file diff --git a/debounce_switch.v b/debounce_switch.v new file mode 100644 index 0000000..755565b --- /dev/null +++ b/debounce_switch.v @@ -0,0 +1,24 @@ +module debounce_switch( + input clk, + input i_switch, + output o_switch); + + parameter c_debounce_limit=250000;// 10ms at 25MHz + +reg r_state=1'b0; +reg [17:0] r_count = 0; + + always@(posedge clk)begin + if (i_switch != r_state && r_count < c_debounce_limit) + r_count <= r_count +1; //counter + else if (r_count == c_debounce_limit)begin + r_count <=0; + r_state <= i_switch; + end + else + r_count<=0; + end + +assign o_switch=r_state; + +endmodule \ No newline at end of file diff --git a/top.v b/top.v new file mode 100644 index 0000000..0dc51a0 --- /dev/null +++ b/top.v @@ -0,0 +1,46 @@ +// TOP module +// +// +// `include "clock_divider_param.v" +// `include "clock_enable_param.v" + + +module top #( parameter + //pattern generator paremater + SPEED = 300, + //enable signal parameters + WAIT = 1, + WAIT_WIDTH = 2, +)( + input clk + ); + +//------internal wires and registers-------- +wire w_enable; + +wire clk50; + +//-----sub modules-------------------------- +clock_enable_param #( + .WAIT(WAIT), + .WIDTH(WAIT_WIDTH) + ) clock_enable1 ( + .clk(clk), + .enable(w_enable) +); + +clock_divider #( + .DIVIDER(1), + .WIDTH(3) +) clk50mhz_gen ( + .clk(clk), + .clk_out(clk50) +); + +debounce_switch debounce_switch_reset( + .clk(clk), + .i_switch(), + .o_switch() +); + +endmodule \ No newline at end of file diff --git a/top_tb.v b/top_tb.v new file mode 100644 index 0000000..4c74a15 --- /dev/null +++ b/top_tb.v @@ -0,0 +1,593 @@ +// This file is Test Bench for top_vga_mem module +// +// + +// 100MHz clock on Basys3 -> 10ns period +// 50% duty cycle 5ns HIGH and 5ns LOW +//`timescale [time unit] / [time precision] +`timescale 10 ns / 1ns + +//sub modules +`include "clock_divider_param.v" +`include "clock_enable_param.v" +`include "blockram.v" +`include "pattern_gen.v" +`include "vga_module.v" +`include "horizontal_counter.v" +`include "vertical_counter.v" +`include "UART_Loopback_module.v" +`include "UART_TX.v" +`include "UART_RX.v" +`include "7segment.v" +`include "com_to_mem_FSM_hex.v" +`include "com_to_mem_module.v" +`include "ov7670_top.v" +`include "debounce_switch.v" +`include "ov7670_capture.v" +`include "ov7670_controller.v" +`include "imag_procesor.v" +`include "default_reg_writer.v" +`include "i2c_sender.v" +`include "ov7670_registers.v" +`include "imag_save.v" +`include "rgb2gray.v" +`include "imag_transform.v" +`include "reg_reader.v" +`include "address_gen.v" +`include "overlay.v" +`include "two_cam_one_screen.v" +`include "lookuptable.v" + +//top module +`include "top.v" + +module top_vga_mem_tb#( parameter + WAIT = 1, + WAIT_WIDTH = 2, + SPEED = 2, + //memory parameters + ADDR_WIDTH = 17, //19, // + DATA_WIDTH = 12, + DEPTH = 307_200//76_800, // +)(); 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