21 lines
482 B
Verilog
21 lines
482 B
Verilog
module read_pointer(
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output [4:0] rptr,
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output fifo_rd,
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input rd,
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input fifo_empty,
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input clk,
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input rst_n);
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reg [4:0] rptr;
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assign fifo_rd = (~fifo_empty)& rd;
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always @(posedge clk or negedge rst_n)
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begin
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if(~rst_n) rptr <= 'b0;
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else if(fifo_rd)
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rptr <= rptr + 'b1;
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else
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rptr <= rptr;
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end
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endmodule
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