Effect module added
This commit is contained in:
Imants Pulkstenis
@@ -1,8 +1,8 @@
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// TOP module
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//
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//
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//
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//
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module top #( parameter
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sclk_ws_ratio = 64, // number of sclk periods per word select period
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mclk_sclk_ratio = 4, // number of mclk periods per sclk period
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@@ -22,115 +22,111 @@ module top #( parameter
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output [7: 0] JXADC // output for logic analizer
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);
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assign da_mclk = master_clk; //output master clock to ADC
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assign ad_mclk = master_clk; //output master clock to DAC
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// assign da_sdin = w_sd_tx; //assign received data to transmit (to playback out received data)
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//------internal wires and registers--------
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wire master_clk; // 11.29 MHz master clock
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wire serial_clk_sender;
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wire word_select_sender;
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wire serial_clk_receicer;
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wire word_select_receicer;
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wire clk_25MHz; //
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wire reset_n;
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wire [d_width-1: 0] r_data_tx;
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wire [d_width-1: 0] l_data_tx;
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wire [d_width-1: 0] r_data_rx;
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wire [d_width-1: 0] l_data_rx;
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wire w_sd_tx; //internal wire
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wire [d_width-1: 0] w_data_to_eff;
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wire w_dv_to_eff;
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wire [d_width-1: 0] w_data_from_eff;
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wire w_dv_from_eff;
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wire w_rd_en_from_eff;
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//-----sub modules--------------------------
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// connecting signals to JXADC PMOD to monitor them with signal analyzer
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JXADC_controler JXADC_controler(
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.ch0(master_clk),
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.ch1(serial_clk_receicer),
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.ch2(word_select_receicer),
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.ch3(ad_sdout), // serial data in
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.ch4(master_clk),
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.ch5(serial_clk_sender),
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.ch6(word_select_sender),
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.ch7(w_sd_tx), // serial data out
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.JXADC(JXADC) // output for logic analizer
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);
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//declare PLL to create 11.29 MHz master clock from 100 MHz system clock
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//declare PLL to create 11.29 MHz master clock from 100 MHz system clock for I2S
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clk_wiz_0 m_clk(
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.clk_in1(clk),
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.clk_out1(master_clk)
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.clk_out1(master_clk), // 11.29 MHz master clock for I2S
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.clk_out2(clk_25MHz) // 25MHz main clock
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);
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// // instantiate I2S Transceiver component
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// i2s_transceiver #(
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// .mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
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// .sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
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// .d_width(d_width) //data width
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// ) i2s_transceiver (
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// .reset_n(reset_n), //asynchronous active high reset
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// .mclk(master_clk), //master clock
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// .sclk(serial_clk), //serial clock (or bit clock)
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// .ws(word_select), //word select (or left-right clock)
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// .sd_rx(ad_sdout), //serial data transmit
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// .sd_tx(w_sd_tx), //serial data receive
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// .l_data_tx(l_data_tx), //left channel data to transmit
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// .r_data_tx(r_data_tx), //right channel data to transmit
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// .l_data_rx(l_data_rx), //left channel data received
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// .r_data_rx(r_data_rx) //right channel data received
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// );
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i2s_sender #(
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io_module #(
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.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
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.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
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.d_width(d_width) //data width
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) i2s_sender (
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.reset_n(reset_n), //asynchronous active high reset
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.mclk(master_clk), //master clock
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.sclk(serial_clk_sender), //serial clock (or bit clock)
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.ws(word_select_sender), //word select (or left-right clock)
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.sd_tx(w_sd_tx), //serial data transmit
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.l_data_tx(l_data_tx), //left channel data to transmit
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.r_data_tx(r_data_tx) //right channel data to transmit
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) io_module (
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.reset_n(reset_n), //asynchronous active high reset
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.mclk(master_clk), //master clock
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.da_sclk(da_sclk), //serial clock (or bit clock)
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.da_ws(da_lrck), //word select (or left-right clock)
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.ad_sclk(ad_sclk), //serial clock (or bit clock)
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.ad_ws(ad_lrck), //word select (or left-right clock)
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.sd_tx(da_sdin), //serial data transmit
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.sd_rx(ad_sdout), //serial data receive
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.l_data_tx(l_data_tx), //left channel data to transmit
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.r_data_tx(r_data_tx), //right channel data to transmit
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.btnC(btnC), //reset button input
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.l_data_rx(l_data_rx), //left channel data received
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.r_data_rx(r_data_rx), //right channel data received
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// // inputs to logic analyzer
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// .ch0(),
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// .ch1(),
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// .ch2(),
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// .ch3(),
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// .ch4(),
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// .ch5(),
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// .ch6(),
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// .ch7(),
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.JXADC(JXADC) // output for logic analizer
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);
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i2s_receicer #(
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.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
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.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
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.d_width(d_width) //data width
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) i2s_receicer (
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.reset_n(reset_n), //asynchronous active high reset
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.mclk(master_clk), //master clock
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.sclk(serial_clk_receicer), //serial clock (or bit clock)
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.ws(word_select_receicer), //word select (or left-right clock)
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.sd_rx(ad_sdout), //serial data receive
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.l_data_rx(l_data_rx), //left channel data received
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.r_data_rx(r_data_rx) //right channel data received
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);
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//passing data to effect controler
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//Effect controler controls effects and perfoms multiplexing and data marging
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effect_controler #(
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.d_width(d_width), //data width
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.memory_d_width(memory_d_width)
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) effect_controler (
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.reset(reset_n), //asynchronous active high reset
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.clk(master_clk),
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.mclk(master_clk),
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.clk(clk_25MHz),
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.i_l_data(l_data_rx), //left channel data received
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.i_r_data(r_data_rx), //right channel data received
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.o_l_data(l_data_tx), //left channel data to transmit
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.o_r_data(r_data_tx) //right channel data to transmit
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.o_r_data(r_data_tx), //right channel data to transmit
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.o_data_to_eff(w_data_to_eff), // Data output to effects module
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.o_data_valid(w_dv_to_eff), // data valid to read (FIFO not empty). data valid signal to effect module
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.i_read_enable(w_rd_en_from_eff), //read enable from Effect module
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.i_data_from_eff(w_data_from_eff), // Data input from effects module
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.i_dv_from_eff(w_dv_from_eff) // data valid write (FIFO not full). data valid signal from effect module
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);
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//debounce reset button
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debounce_switch debounce_switch_reset(
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.clk(master_clk),
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.i_switch(btnC),
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.o_switch(reset_n)
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//Effect module contains all individual effects
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effect_module #(
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.d_width(memory_d_width) //data width
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) effect_module (
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.clk(clk_25MHz),
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.reset(reset_n),
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.i_data_ready(w_dv_to_eff), // data ready to read
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.i_data(w_data_to_eff), // data input form effect controler
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.read_enable(w_rd_en_from_eff), // enable data reading
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.o_data(w_data_from_eff),
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.data_valid(w_dv_from_eff)
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);
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assign da_mclk = master_clk; //output master clock to ADC
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assign ad_mclk = master_clk; //output master clock to DAC
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assign da_sclk = serial_clk_sender; //output serial clock (from I2S Transceiver) to ADC
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assign ad_sclk = serial_clk_receicer; //output serial clock (from I2S Transceiver) to DAC
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assign da_lrck = word_select_sender; //output word select (from I2S Transceiver) to ADC
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assign ad_lrck = word_select_receicer; //output word select (from I2S Transceiver) to DAC
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assign da_sdin = w_sd_tx; //assign right channel received data to transmit (to playback out received data)
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endmodule
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