diff --git a/clipping.v b/clipping.v
new file mode 100644
index 0000000..a6668e9
--- /dev/null
+++ b/clipping.v
@@ -0,0 +1,16 @@
+module eclipping_effect #( parameter
+    data_width = 16          // data width 
+)(
+    input                                   clk,
+    input                                   reset,
+    input   signed      [data_width-1: 0]   i_data,
+    output  signed      [data_width-1: 0]   o_data,
+    input               [data_width-1: 0]   i_treshhold
+);
+
+
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/clock_divider_param.v b/clock_divider_param.v
index 23676c6..9e2d2bd 100644
--- a/clock_divider_param.v
+++ b/clock_divider_param.v
@@ -7,13 +7,13 @@ module clock_divider #(
     parameter DIVIDER =2,
     parameter WIDTH =2
 ) (
-    input clk,
+    input clk_in,
     output clk_out);
 
 reg state=1'b0, next_state=1'b1;
 reg [WIDTH-1:0] counter = DIVIDER-1 ; 
 
-always@(posedge clk)begin
+always@(posedge clk_in)begin
     state <= next_state;
     if ( counter == 0) begin
         next_state <= ~next_state;
diff --git a/effect_controler.v b/effect_controler.v
index 89abe14..622fc07 100644
--- a/effect_controler.v
+++ b/effect_controler.v
@@ -4,65 +4,72 @@ module effect_controler #( parameter
     ram_depth = 16,              //
     memory_d_width = 16          // 
 )(
-    input                               clk,
+    input                               mclk,   // io_module clock
+    input                               clk,    // main clock   
     input                               reset,
     input   signed      [d_width-1: 0]  i_l_data,
     input   signed      [d_width-1: 0]  i_r_data,   // not used
     output  signed      [d_width-1: 0]  o_l_data,
-    output  signed      [d_width-1: 0]  o_r_data
+    output  signed      [d_width-1: 0]  o_r_data,
+
+    output  signed      [memory_d_width-1: 0]   o_data_to_eff,     // Data output to effects module
+    output                                      o_data_valid,         // data valid to read (FIFO not empty). data valid signal to effect module
+    input                                       i_read_enable,
+    input  signed      [memory_d_width-1: 0]    i_data_from_eff,     // Data output to effects module
+    input                                       i_dv_from_eff         // data valid to read (FIFO not empty). data valid signal to effect module
+     
 );
 
-wire signed [memory_d_width: 0]  w_o_data;
+wire signed [memory_d_width-1: 0]  w_o_data;        //output data to io_module 
 
-wire w_empty, w_full;
-wire  [address_width:0]     w_data_fill;
+//wire signed [memory_d_width-1: 0]  w_o_data_eff;    //output data to effects module 
+
+wire                            w_empty_in, w_full_in;
+wire                            w_empty_out, w_full_out;
+wire  [address_width-1:0]       w_data_fill_input;      // shows how full are in FIFO memmory for intput
+wire  [address_width-1:0]       w_data_fill_output;     // shows how full are in FIFO memmory for output
 
 assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data;         // only left chanal are used in controler
 assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data;         // same as left
 
+assign o_data_valid = ~w_empty_in;
+
+// Input FIFO
 sync_fifo #( 
    .ram_depth(ram_depth),               // ram memory depth
    .address_width(address_width),       // ram memory address width
-   //.data_width(d_width)               // data width
    .data_width(memory_d_width)          // memory data width
-) fifo_l (
-   .data_out(w_o_data),
-   .full(w_full),
-   .empty(w_empty),
-   .data_fill(w_data_fill),
-   .data_in(i_l_data[ d_width-1 : d_width-memory_d_width ]),       
-   .clk(clk),
-   .rst_a(reset),
-   .wr_en( w_full ? 1'b0 : 1'b1 ),
-   .rd_en((w_empty & (w_data_fill > 1 )) ? 1'b0 : 1'b1)
+) fifo_input (
+   .data_out(o_data_to_eff),
+   .full(w_full_in),
+   .empty(w_empty_in),
+   .data_fill(w_data_fill_input),
+   .data_in(i_l_data[ d_width-1 : d_width - memory_d_width ]),       
+   .w_clk(mclk),
+   .r_clk(clk),
+   .reset(reset),
+   .wr_en( w_full_in  ? 1'b0 : 1'b1 ),          // checking is FIFO full
+   .rd_en( w_empty_in ? 1'b0 : i_read_enable )           // checking is FIFO empty
 );
 
-// sync_fifo #( 
-//    .ram_depth(ram_depth),               // ram memory depth
-//    .address_width(address_width),       // ram memory address width
-//    .data_width(d_width)                 // data width
-// ) fifo_r (
-//    .data_out(o_r_data),
-//    .full(),
-//    .empty(),
-//    .data_in(i_r_data),
-//    .clk(clk),
-//    .rst_a(reset),
-//    .wr_en(1'b1),
-//    .rd_en(1'b1)
-// );
+// Output FIFO
+sync_fifo #( 
+   .ram_depth(ram_depth),               // ram memory depth
+   .address_width(address_width),       // ram memory address width
+   .data_width(memory_d_width)          // memory data width
+) fifo_output (
+   .data_out(w_o_data),
+   .full(w_full_out),
+   .empty(w_empty_out),
+   .data_fill(w_data_fill),
+   .data_in(i_data_from_eff),       
+   .w_clk(clk),
+   .r_clk(mclk),
+   .reset(reset),
+   .wr_en( w_full_out  ? 1'b0 : i_dv_from_eff ),     // checking is FIFO full
+   .rd_en( w_empty_out ? 1'b0 : 1'b1 )                  // checking is FIFO empty
+);
 
 
-// always@* begin
-//     o_l_data <= i_l_data;
-//     o_r_data <= i_r_data;
-// end
-
-//assign o_l_data = i_l_data;
-//assign o_r_data = i_r_data;
-
-
-//assign o_l_data = 24'h000000;
-//assign o_r_data = 24'h400008;
 
 endmodule
\ No newline at end of file
diff --git a/effect_module.v b/effect_module.v
new file mode 100644
index 0000000..1bb3e5c
--- /dev/null
+++ b/effect_module.v
@@ -0,0 +1,30 @@
+module effect_module #( parameter
+    d_width = 16                // data width
+)(
+    input                               clk,
+    input                               reset,
+    input                               i_data_ready,     // data ready to read
+    input   signed      [d_width-1: 0]  i_data,         // data input form effect controler
+    output                              read_enable,    // enable data reading
+    output  signed      [d_width-1: 0]  o_data,         // data output form effect controler
+
+    output                              data_valid
+
+    );
+
+assign o_data = i_data_ready ? i_data : 'b0 ;
+assign read_enable = i_data_ready ? 1 : 0 ;
+assign data_valid = i_data_ready ? 1 : 0 ;
+
+// // cliping effect
+// eclipping_effect #(
+//    .data_width(d_width)               // data width
+// ) eclipping_effect (
+//    .clk(clk),
+//    .reset(reset),
+//    .i_data(i_data),
+//    .o_data(o_data)
+// );
+
+
+endmodule
\ No newline at end of file
diff --git a/io_module.v b/io_module.v
new file mode 100644
index 0000000..b1af59d
--- /dev/null
+++ b/io_module.v
@@ -0,0 +1,90 @@
+module io_module #( parameter
+    sclk_ws_ratio = 64,         // number of sclk periods per word select period
+    mclk_sclk_ratio = 4,        // number of mclk periods per sclk period
+    d_width = 24                // data width
+)(
+    output reset_n,                             //asynchronous active low reset
+    input  mclk,                                //master clock
+    output ad_sclk,                             //serial clock (or bit clock)
+    output ad_ws,                               //word select (or left-right clock)
+    output da_sclk,                             //serial clock (or bit clock)
+    output da_ws,                               //word select (or left-right clock)
+    output sd_tx,                               //serial data transmit
+    input  sd_rx,                               //serial data receive
+
+    input signed [d_width-1: 0] l_data_tx,      //left channel data to transmit
+    input signed [d_width-1: 0] r_data_tx,      //right channel data to transmit
+
+    output signed [d_width-1: 0] l_data_rx,            //left channel data received
+    output signed [d_width-1: 0] r_data_rx,             //right channel data received   
+
+    input btnC,
+    
+    // // inputs to logic analyzer
+    // input           ch0,
+    // input           ch1,
+    // input           ch2,
+    // input           ch3,
+    // input           ch4,
+    // input           ch5,
+    // input           ch6,
+    // input           ch7,
+
+    output  [7: 0]  JXADC      // output for logic analizer
+
+    );
+
+
+
+i2s_sender  #(
+    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
+    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
+    .d_width(d_width)                       //data width
+) i2s_sender (
+    .reset_n(reset_n),      //asynchronous active high reset
+    .mclk(mclk),            //master clock
+    .sclk(da_sclk),         //serial clock (or bit clock)
+    .ws(da_ws),             //word select (or left-right clock)
+    .sd_tx(sd_tx),          //serial data transmit
+    .l_data_tx(l_data_tx),  //left channel data to transmit
+    .r_data_tx(r_data_tx)   //right channel data to transmit
+);
+
+
+
+i2s_receicer  #(
+    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
+    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
+    .d_width(d_width)                       //data width
+) i2s_receicer (
+    .reset_n(reset_n),          //asynchronous active high reset
+    .mclk(mclk),                //master clock
+    .sclk(ad_sclk),             //serial clock (or bit clock)
+    .ws(ad_ws),                //word select (or left-right clock)
+    .sd_rx(sd_rx),              //serial data receive
+    .l_data_rx(l_data_rx),      //left channel data received
+    .r_data_rx(r_data_rx)       //right channel data received
+);
+
+
+// connecting signals to JXADC PMOD to monitor them with signal analyzer
+JXADC_controler JXADC_controler(
+    .ch0(mclk),
+    .ch1(ad_sclk),
+    .ch2(ad_ws),
+    .ch3(sd_rx),        // serial data in
+    .ch4(mclk),
+    .ch5(da_sclk),
+    .ch6(da_ws),
+    .ch7(sd_tx),        // serial data out
+    .JXADC(JXADC)       // output for logic analizer   
+);
+
+// debounce reset button
+debounce_switch debounce_switch_reset(
+    .clk(mclk),
+    .i_switch(btnC),
+    .o_switch(reset_n)
+);
+
+endmodule
\ No newline at end of file
diff --git a/sync_fifo.v b/sync_fifo.v
index 12787aa..6a24dc5 100644
--- a/sync_fifo.v
+++ b/sync_fifo.v
@@ -5,16 +5,17 @@ module sync_fifo #( parameter
 //---------------parametre declaration
    data_width       = 4,
    address_width    = 4,
-   ram_depth        = 16 
+   ram_depth        = 16         // must be 2^n
 )(
 //--------------input output port declaration
    output reg signed [data_width-1:0]  data_out,
    output                        full,
    output                        empty,
-   output  [address_width:0]     data_fill,
-   input     signed  [data_width-1:0]  data_in,
-   input                         clk,
-   input                         rst_a,
+   output  [address_width-1:0]     data_fill,
+   input signed  [data_width-1:0]  data_in,
+   input                         w_clk,      // write clock
+   input                         r_clk,      // read clock
+   input                         reset,
    input                         wr_en,
    input                         rd_en);
  
@@ -22,51 +23,78 @@ module sync_fifo #( parameter
 //--------------internal register declaration
 reg      [address_width-1:0]     wr_pointer = 0;
 reg      [address_width-1:0]     rd_pointer = 0;
-reg      [address_width :0]      status_count = 0;
+// reg      [address_width :0]      status_count = 0;
 wire  signed   [data_width-1:0]        data_ram ;
 
+// reg addition = 0;
+// reg subtractor = 0; 
 
+// always@(posedge addition )
+// begin
+//    if (addition ^ subtractor)    // if XOR
+//    begin  
+//       if (status_count != 0) 
+//                status_count = status_count + 1;  
+//    end
+//    addition = 0;        // reset addition 
+// end
+
+// always@(posedge subtractor)
+// begin
+//    if (addition ^ subtractor)    // if XOR
+//    begin
+//       if (status_count != 0) 
+//                status_count = status_count - 1;  
+//    end 
+//    subtractor = 0;      // reset subtractor
+// end
  
 //--------------wr_pointer pointing to write address
-   always @ (posedge clk,posedge rst_a)
+   always @ (posedge w_clk,posedge reset)
    begin
-      if(rst_a)
+      if(reset)
          wr_pointer = 0;
       else if(wr_en)
          wr_pointer = wr_pointer+1;
+         //addition = 1;
    end
 //-------------rd_pointer points to read address
-   always @ (posedge clk,posedge rst_a)
+   always @ (posedge r_clk,posedge reset)
    begin
-      if(rst_a)
+      if(reset)
          rd_pointer = 0;
       else if(rd_en)
-         rd_pointer = rd_pointer+1;
+         rd_pointer = rd_pointer + 1;
+         //subtractor = 1;
    end
 //-------------read from FIFO
-   always @ (posedge clk,posedge rst_a)
+   always @ (posedge r_clk,posedge reset)
    begin
-      if(rst_a)
+      if(reset)
          data_out=0;
       else if(rd_en)
          data_out=data_ram;
    end
 
-//--------------Status pointer for full and empty checking
-   always @ (posedge clk,posedge rst_a)
-   begin
-      if(rst_a)
-         status_count = 0;
-      else if(wr_en && !rd_en && (status_count != ram_depth))
-         status_count = status_count + 1;
-      else if(rd_en && !wr_en && (status_count != 0))
-         status_count = status_count - 1;
-   end // always @ (posedge clk,posedge rst_a)
+// //--------------Status pointer for full and empty checking
+//    always @ (posedge w_clk,posedge r_clk,posedge reset)
+//    begin
+//       if(reset)
+//          status_count = 0;
+//       else if(wr_en && !rd_en && (status_count != ram_depth))
+//          status_count = status_count + 1;
+//       else if(rd_en && !wr_en && (status_count != 0))
+//          status_count = status_count - 1;
+//    end // always @ (posedge clk,posedge reset)
 
 
-assign full = (status_count == (ram_depth));
-assign empty = (status_count == 0);
-assign data_fill = status_count;       // how full are FIFO
+// assign full = (status_count == (ram_depth));
+// assign empty = (status_count == 0);
+// assign data_fill = status_count;       // how full are FIFO
+
+assign full = (wr_pointer - rd_pointer  == ram_depth) ? 1'b1 : 1'b0 ;
+assign empty = (wr_pointer - rd_pointer == 0) ? 1'b1 : 1'b0 ;
+assign data_fill = wr_pointer - rd_pointer ;       // how full are FIFO
  
 rams_tdp_rf_rf #( 
    .DEPTH(ram_depth),
@@ -83,8 +111,8 @@ rams_tdp_rf_rf #(
    .web(1'b0),
    .ena(1'b1),
    .enb(rd_en),
-   .clka(clk),
-   .clkb(clk)
+   .clka(w_clk),
+   .clkb(r_clk)
 );
 
 endmodule // sync_fifo
diff --git a/top.v b/top.v
index ec4ea4f..47aa6c6 100644
--- a/top.v
+++ b/top.v
@@ -1,8 +1,8 @@
 //      TOP module 
 //       
-
-
-
+//
+//
+//
 module top #( parameter
     sclk_ws_ratio = 64,         // number of sclk periods per word select period
     mclk_sclk_ratio = 4,        // number of mclk periods per sclk period
@@ -22,115 +22,111 @@ module top #( parameter
     output  [7: 0]  JXADC       // output for logic analizer
     );
 
+assign da_mclk = master_clk;    //output master clock to ADC
+assign ad_mclk = master_clk;    //output master clock to DAC
+// assign da_sdin = w_sd_tx;      //assign received data to transmit (to playback out received data)
+
+
 //------internal wires and registers--------
 wire master_clk;            // 11.29 MHz master clock
-wire serial_clk_sender;
-wire word_select_sender;
-wire serial_clk_receicer;
-wire word_select_receicer;
+
+wire clk_25MHz;             // 
+
 wire reset_n;
 wire [d_width-1: 0] r_data_tx;
 wire [d_width-1: 0] l_data_tx;
 wire [d_width-1: 0] r_data_rx;
 wire [d_width-1: 0] l_data_rx;
 
-wire w_sd_tx;               //internal wire
+wire [d_width-1: 0] w_data_to_eff;
+wire                w_dv_to_eff;  
+
+wire [d_width-1: 0] w_data_from_eff;
+wire                w_dv_from_eff; 
+
+wire                w_rd_en_from_eff;
 
 //-----sub modules--------------------------
-// connecting signals to JXADC PMOD to monitor them with signal analyzer
-JXADC_controler JXADC_controler(
-    .ch0(master_clk),
-    .ch1(serial_clk_receicer),
-    .ch2(word_select_receicer),
-    .ch3(ad_sdout),     // serial data in
-    .ch4(master_clk),
-    .ch5(serial_clk_sender),
-    .ch6(word_select_sender),
-    .ch7(w_sd_tx),      // serial data out
-    .JXADC(JXADC)       // output for logic analizer   
-);
 
-
-//declare PLL to create 11.29 MHz master clock from 100 MHz system clock
+//declare PLL to create 11.29 MHz master clock from 100 MHz system clock for I2S
 clk_wiz_0 m_clk(
     .clk_in1(clk),
-    .clk_out1(master_clk)
+    .clk_out1(master_clk),  // 11.29 MHz master clock for I2S
+    .clk_out2(clk_25MHz)   // 25MHz main clock
 );
 
-// // instantiate I2S Transceiver component
-// i2s_transceiver  #(
-//     .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
-//     .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
-//     .d_width(d_width)                       //data width
-// ) i2s_transceiver (
-//     .reset_n(reset_n),         //asynchronous active high reset
-//     .mclk(master_clk),      //master clock
-//     .sclk(serial_clk),      //serial clock (or bit clock)
-//     .ws(word_select),       //word select (or left-right clock)
-//     .sd_rx(ad_sdout),       //serial data transmit
-//     .sd_tx(w_sd_tx),        //serial data receive
-//     .l_data_tx(l_data_tx),  //left channel data to transmit
-//     .r_data_tx(r_data_tx),  //right channel data to transmit
-//     .l_data_rx(l_data_rx),  //left channel data received
-//     .r_data_rx(r_data_rx)   //right channel data received
-// );
 
-i2s_sender  #(
+io_module  #(
     .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
     .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
     .d_width(d_width)                       //data width
-) i2s_sender (
-    .reset_n(reset_n),      //asynchronous active high reset
-    .mclk(master_clk),      //master clock
-    .sclk(serial_clk_sender),      //serial clock (or bit clock)
-    .ws(word_select_sender),       //word select (or left-right clock)
-    .sd_tx(w_sd_tx),        //serial data transmit
-    .l_data_tx(l_data_tx),  //left channel data to transmit
-    .r_data_tx(r_data_tx)   //right channel data to transmit
+) io_module (
+    .reset_n(reset_n),                  //asynchronous active high reset
+    .mclk(master_clk),                  //master clock
+    .da_sclk(da_sclk),                  //serial clock (or bit clock)
+    .da_ws(da_lrck),                    //word select (or left-right clock)
+    .ad_sclk(ad_sclk),                  //serial clock (or bit clock)
+    .ad_ws(ad_lrck),                    //word select (or left-right clock)
+    .sd_tx(da_sdin),                    //serial data transmit
+    .sd_rx(ad_sdout),                   //serial data receive
+    .l_data_tx(l_data_tx),              //left channel data to transmit
+    .r_data_tx(r_data_tx),              //right channel data to transmit
+
+    .btnC(btnC),                        //reset button input
+
+    .l_data_rx(l_data_rx),              //left channel data received
+    .r_data_rx(r_data_rx),              //right channel data received
+
+
+    // // inputs to logic analyzer
+    // .ch0(),
+    // .ch1(),
+    // .ch2(),
+    // .ch3(),
+    // .ch4(),
+    // .ch5(),
+    // .ch6(),
+    // .ch7(),
+
+    .JXADC(JXADC)                       // output for logic analizer
 );
 
-i2s_receicer  #(
-    .mclk_sclk_ratio(mclk_sclk_ratio),      //number of mclk periods per sclk period
-    .sclk_ws_ratio(sclk_ws_ratio),          //number of sclk periods per word select period
-    .d_width(d_width)                       //data width
-) i2s_receicer (
-    .reset_n(reset_n),         //asynchronous active high reset
-    .mclk(master_clk),      //master clock
-    .sclk(serial_clk_receicer),      //serial clock (or bit clock)
-    .ws(word_select_receicer),       //word select (or left-right clock)
-    .sd_rx(ad_sdout),       //serial data receive
-    .l_data_rx(l_data_rx),  //left channel data received
-    .r_data_rx(r_data_rx)   //right channel data received
-);
 
-//passing data to effect controler
+//Effect controler controls effects and perfoms multiplexing and data marging
 effect_controler #(
     .d_width(d_width),                       //data width
     .memory_d_width(memory_d_width)
 ) effect_controler (
     .reset(reset_n),                    //asynchronous active high reset
-    .clk(master_clk),
+    .mclk(master_clk),
+    .clk(clk_25MHz),
     .i_l_data(l_data_rx),               //left channel data received         
     .i_r_data(r_data_rx),               //right channel data received
     .o_l_data(l_data_tx),               //left channel data to transmit
-    .o_r_data(r_data_tx)                //right channel data to transmit
+    .o_r_data(r_data_tx),               //right channel data to transmit
+
+    .o_data_to_eff(w_data_to_eff),      // Data output to effects module
+    .o_data_valid(w_dv_to_eff),         // data valid to read (FIFO not empty). data valid signal to effect module
+    
+    .i_read_enable(w_rd_en_from_eff),       //read enable from Effect module
+    .i_data_from_eff(w_data_from_eff),     // Data input from effects module
+    .i_dv_from_eff(w_dv_from_eff)         // data valid write (FIFO not full). data valid signal from effect module
 );
 
-//debounce reset button
-debounce_switch debounce_switch_reset(
-    .clk(master_clk),
-    .i_switch(btnC),
-    .o_switch(reset_n)
+
+//Effect module contains all individual effects  
+effect_module #(
+    .d_width(memory_d_width)                    //data width
+) effect_module (
+    .clk(clk_25MHz),
+    .reset(reset_n),
+    .i_data_ready(w_dv_to_eff),                // data ready to read
+    .i_data(w_data_to_eff),                     // data input form effect controler
+    .read_enable(w_rd_en_from_eff),                             // enable data reading
+    .o_data(w_data_from_eff),
+    .data_valid(w_dv_from_eff)
+
 );
 
-assign da_mclk = master_clk;    //output master clock to ADC
-assign ad_mclk = master_clk;    //output master clock to DAC
-assign da_sclk = serial_clk_sender;    //output serial clock (from I2S Transceiver) to ADC
-assign ad_sclk = serial_clk_receicer;    //output serial clock (from I2S Transceiver) to DAC
-assign da_lrck = word_select_sender;   //output word select (from I2S Transceiver) to ADC
-assign ad_lrck = word_select_receicer;   //output word select (from I2S Transceiver) to DAC
-
-assign da_sdin = w_sd_tx;      //assign right channel received data to transmit (to playback out received data)
-
 
 endmodule
\ No newline at end of file