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Add fifo memory size variable.

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Imants Pulkstenis
2019-11-22 00:49:32 +02:00
parent 07cfe9893d
commit 15dbd68ee2
4 changed files with 45 additions and 33 deletions
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blockram.v
+3 -3
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@@ -7,15 +7,15 @@
// Dual-Port Block RAM with Two Write Ports // Dual-Port Block RAM with Two Write Ports
// File: blobkram.v // File: blobkram.v
module blockram #( parameter module rams_tdp_rf_rf #( parameter
DEPTH = 16, DEPTH = 16,
ADDR_WIDTH = 4, ADDR_WIDTH = 4,
DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob); DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
input clka,clkb,ena,enb,wea,web; input clka,clkb,ena,enb,wea,web;
input [ADDR_WIDTH-1:0] addra,addrb; input [ADDR_WIDTH-1:0] addra,addrb;
input signed [DATA_WIDTH-1:0] dia,dib; input [DATA_WIDTH-1:0] dia,dib;
output signed [DATA_WIDTH-1:0] doa,dob; output [DATA_WIDTH-1:0] doa,dob;
reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0]; reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0];
reg [DATA_WIDTH-1:0] doa,dob; reg [DATA_WIDTH-1:0] doa,dob;
effect_controler.v
+32 -23
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@@ -1,47 +1,56 @@
module effect_controler #( parameter module effect_controler #( parameter
d_width = 24, // data width d_width = 24, // data width
address_width = 4, // address_width = 4, //
ram_depth = 16 // ram_depth = 16, //
memory_d_width = 16 //
)( )(
input clk, input clk,
input reset, input reset,
input signed [d_width-1: 0] i_l_data, input signed [d_width-1: 0] i_l_data,
input signed [d_width-1: 0] i_r_data, input signed [d_width-1: 0] i_r_data, // not used
output signed [d_width-1: 0] o_l_data, output signed [d_width-1: 0] o_l_data,
output signed [d_width-1: 0] o_r_data output signed [d_width-1: 0] o_r_data
); );
wire signed [memory_d_width: 0] w_o_data;
wire w_empty, w_full;
wire [address_width:0] w_data_fill;
assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler
assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left
sync_fifo #( sync_fifo #(
.ram_depth(ram_depth), // ram memory depth .ram_depth(ram_depth), // ram memory depth
.address_width(address_width), // ram memory address width .address_width(address_width), // ram memory address width
.data_width(d_width) // data width //.data_width(d_width) // data width
.data_width(memory_d_width) // memory data width
) fifo_l ( ) fifo_l (
.data_out(o_l_data), .data_out(w_o_data),
.full(), .full(w_full),
.empty(), .empty(w_empty),
.data_in(i_l_data), .data_fill(w_data_fill),
.data_in(i_l_data[ d_width-1 : d_width-memory_d_width ]),
.clk(clk), .clk(clk),
.rst_a(reset), .rst_a(reset),
.wr_en(1'b1), .wr_en( w_full ? 1'b0 : 1'b1 ),
.rd_en(1'b1) .rd_en((w_empty & (w_data_fill > 1 )) ? 1'b0 : 1'b1)
); );
sync_fifo #( // sync_fifo #(
.ram_depth(ram_depth), // ram memory depth // .ram_depth(ram_depth), // ram memory depth
.address_width(address_width), // ram memory address width // .address_width(address_width), // ram memory address width
.data_width(d_width) // data width // .data_width(d_width) // data width
) fifo_r ( // ) fifo_r (
.data_out(o_r_data), // .data_out(o_r_data),
.full(), // .full(),
.empty(), // .empty(),
.data_in(i_r_data), // .data_in(i_r_data),
.clk(clk), // .clk(clk),
.rst_a(reset), // .rst_a(reset),
.wr_en(1'b1), // .wr_en(1'b1),
.rd_en(1'b1) // .rd_en(1'b1)
); // );
// always@* begin // always@* begin
sync_fifo.v
+6 -5
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@@ -11,6 +11,7 @@ module sync_fifo #( parameter
output reg signed [data_width-1:0] data_out, output reg signed [data_width-1:0] data_out,
output full, output full,
output empty, output empty,
output [address_width:0] data_fill,
input signed [data_width-1:0] data_in, input signed [data_width-1:0] data_in,
input clk, input clk,
input rst_a, input rst_a,
@@ -19,10 +20,9 @@ module sync_fifo #( parameter
//--------------internal register declaration //--------------internal register declaration
reg [address_width-1:0] wr_pointer; reg [address_width-1:0] wr_pointer = 0;
reg [address_width-1:0] rd_pointer; reg [address_width-1:0] rd_pointer = 0;
reg [address_width :0] status_count; reg [address_width :0] status_count = 0;
reg signed [data_width-1:0] data_out ;
wire signed [data_width-1:0] data_ram ; wire signed [data_width-1:0] data_ram ;
@@ -66,8 +66,9 @@ wire signed [data_width-1:0] data_ram ;
assign full = (status_count == (ram_depth)); assign full = (status_count == (ram_depth));
assign empty = (status_count == 0); assign empty = (status_count == 0);
assign data_fill = status_count; // how full are FIFO
blockram #( rams_tdp_rf_rf #(
.DEPTH(ram_depth), .DEPTH(ram_depth),
.ADDR_WIDTH(address_width), .ADDR_WIDTH(address_width),
.DATA_WIDTH(data_width) .DATA_WIDTH(data_width)
top.v
+4 -2
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@@ -6,7 +6,8 @@
module top #( parameter module top #( parameter
sclk_ws_ratio = 64, // number of sclk periods per word select period sclk_ws_ratio = 64, // number of sclk periods per word select period
mclk_sclk_ratio = 4, // number of mclk periods per sclk period mclk_sclk_ratio = 4, // number of mclk periods per sclk period
d_width = 24 // data width d_width = 24, // data width for I2S
memory_d_width = 16 // data width for memory (and effects). lower bits are ignored
)( )(
input clk, input clk,
input btnC, input btnC,
@@ -104,7 +105,8 @@ i2s_receicer #(
//passing data to effect controler //passing data to effect controler
effect_controler #( effect_controler #(
.d_width(d_width) //data width .d_width(d_width), //data width
.memory_d_width(memory_d_width)
) effect_controler ( ) effect_controler (
.reset(reset_n), //asynchronous active high reset .reset(reset_n), //asynchronous active high reset
.clk(master_clk), .clk(master_clk),