From 15dbd68ee204f9c6cc856b87ce853583a1676bca Mon Sep 17 00:00:00 2001 From: Imants Pulkstenis Date: Fri, 22 Nov 2019 00:49:32 +0200 Subject: [PATCH] Add fifo memory size variable. --- blockram.v | 6 ++--- effect_controler.v | 55 +++++++++++++++++++++++++++------------------- sync_fifo.v | 11 +++++----- top.v | 6 +++-- 4 files changed, 45 insertions(+), 33 deletions(-) diff --git a/blockram.v b/blockram.v index 44cb0a2..a3d8268 100644 --- a/blockram.v +++ b/blockram.v @@ -7,15 +7,15 @@ // Dual-Port Block RAM with Two Write Ports // File: blobkram.v -module blockram #( parameter +module rams_tdp_rf_rf #( parameter DEPTH = 16, ADDR_WIDTH = 4, DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob); input clka,clkb,ena,enb,wea,web; input [ADDR_WIDTH-1:0] addra,addrb; -input signed [DATA_WIDTH-1:0] dia,dib; -output signed [DATA_WIDTH-1:0] doa,dob; +input [DATA_WIDTH-1:0] dia,dib; +output [DATA_WIDTH-1:0] doa,dob; reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0]; reg [DATA_WIDTH-1:0] doa,dob; diff --git a/effect_controler.v b/effect_controler.v index 4a321d4..89abe14 100644 --- a/effect_controler.v +++ b/effect_controler.v @@ -1,47 +1,56 @@ module effect_controler #( parameter d_width = 24, // data width address_width = 4, // - ram_depth = 16 // + ram_depth = 16, // + memory_d_width = 16 // )( input clk, input reset, input signed [d_width-1: 0] i_l_data, - input signed [d_width-1: 0] i_r_data, + input signed [d_width-1: 0] i_r_data, // not used output signed [d_width-1: 0] o_l_data, output signed [d_width-1: 0] o_r_data ); +wire signed [memory_d_width: 0] w_o_data; +wire w_empty, w_full; +wire [address_width:0] w_data_fill; + +assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler +assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left sync_fifo #( .ram_depth(ram_depth), // ram memory depth .address_width(address_width), // ram memory address width - .data_width(d_width) // data width + //.data_width(d_width) // data width + .data_width(memory_d_width) // memory data width ) fifo_l ( - .data_out(o_l_data), - .full(), - .empty(), - .data_in(i_l_data), + .data_out(w_o_data), + .full(w_full), + .empty(w_empty), + .data_fill(w_data_fill), + .data_in(i_l_data[ d_width-1 : d_width-memory_d_width ]), .clk(clk), .rst_a(reset), - .wr_en(1'b1), - .rd_en(1'b1) + .wr_en( w_full ? 1'b0 : 1'b1 ), + .rd_en((w_empty & (w_data_fill > 1 )) ? 1'b0 : 1'b1) ); -sync_fifo #( - .ram_depth(ram_depth), // ram memory depth - .address_width(address_width), // ram memory address width - .data_width(d_width) // data width -) fifo_r ( - .data_out(o_r_data), - .full(), - .empty(), - .data_in(i_r_data), - .clk(clk), - .rst_a(reset), - .wr_en(1'b1), - .rd_en(1'b1) -); +// sync_fifo #( +// .ram_depth(ram_depth), // ram memory depth +// .address_width(address_width), // ram memory address width +// .data_width(d_width) // data width +// ) fifo_r ( +// .data_out(o_r_data), +// .full(), +// .empty(), +// .data_in(i_r_data), +// .clk(clk), +// .rst_a(reset), +// .wr_en(1'b1), +// .rd_en(1'b1) +// ); // always@* begin diff --git a/sync_fifo.v b/sync_fifo.v index da787fc..12787aa 100644 --- a/sync_fifo.v +++ b/sync_fifo.v @@ -11,6 +11,7 @@ module sync_fifo #( parameter output reg signed [data_width-1:0] data_out, output full, output empty, + output [address_width:0] data_fill, input signed [data_width-1:0] data_in, input clk, input rst_a, @@ -19,10 +20,9 @@ module sync_fifo #( parameter //--------------internal register declaration -reg [address_width-1:0] wr_pointer; -reg [address_width-1:0] rd_pointer; -reg [address_width :0] status_count; -reg signed [data_width-1:0] data_out ; +reg [address_width-1:0] wr_pointer = 0; +reg [address_width-1:0] rd_pointer = 0; +reg [address_width :0] status_count = 0; wire signed [data_width-1:0] data_ram ; @@ -66,8 +66,9 @@ wire signed [data_width-1:0] data_ram ; assign full = (status_count == (ram_depth)); assign empty = (status_count == 0); +assign data_fill = status_count; // how full are FIFO -blockram #( +rams_tdp_rf_rf #( .DEPTH(ram_depth), .ADDR_WIDTH(address_width), .DATA_WIDTH(data_width) diff --git a/top.v b/top.v index 2d1b65e..ec4ea4f 100644 --- a/top.v +++ b/top.v @@ -6,7 +6,8 @@ module top #( parameter sclk_ws_ratio = 64, // number of sclk periods per word select period mclk_sclk_ratio = 4, // number of mclk periods per sclk period - d_width = 24 // data width + d_width = 24, // data width for I2S + memory_d_width = 16 // data width for memory (and effects). lower bits are ignored )( input clk, input btnC, @@ -104,7 +105,8 @@ i2s_receicer #( //passing data to effect controler effect_controler #( - .d_width(d_width) //data width + .d_width(d_width), //data width + .memory_d_width(memory_d_width) ) effect_controler ( .reset(reset_n), //asynchronous active high reset .clk(master_clk),