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fifo module now working in loopback mode

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Imants Pulkstenis
2019-11-21 23:01:00 +02:00
parent b8bfb00389
commit 07cfe9893d
3 changed files with 15 additions and 15 deletions
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blockram.v
+4 -4
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@@ -7,16 +7,16 @@
// Dual-Port Block RAM with Two Write Ports // Dual-Port Block RAM with Two Write Ports
// File: blobkram.v // File: blobkram.v
module ram #( parameter module blockram #( parameter
DEPTH = 16, DEPTH = 16,
ADDR_WIDTH = 4, ADDR_WIDTH = 4,
DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob); DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
input clka,clkb,ena,enb,wea,web; input clka,clkb,ena,enb,wea,web;
input [ADDR_WIDTH-1:0] addra,addrb; input [ADDR_WIDTH-1:0] addra,addrb;
input [DATA_WIDTH-1:0] dia,dib; input signed [DATA_WIDTH-1:0] dia,dib;
output [DATA_WIDTH-1:0] doa,dob; output signed [DATA_WIDTH-1:0] doa,dob;
reg [ADDR_WIDTH-1:0] ram [ DEPTH - 1 :0]; reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0];
reg [DATA_WIDTH-1:0] doa,dob; reg [DATA_WIDTH-1:0] doa,dob;
always @(posedge clka) always @(posedge clka)
sync_fifo.v
+9 -9
View File
@@ -1,17 +1,17 @@
// Fifo code source: // Fifo code source:
// https://vlsicoding.blogspot.com/2013/11/verilog-code-for-synchronous-fifo.html // https://vlsicoding.blogspot.com/2013/11/verilog-code-for-synchronous-fifo.html
// //
module sync_fifo #( module sync_fifo #( parameter
//---------------parametre declaration //---------------parametre declaration
parameter data_width = 4, data_width = 4,
parameter address_width = 4, address_width = 4,
parameter ram_depth = 16 ram_depth = 16
)( )(
//--------------input output port declaration //--------------input output port declaration
output reg [data_width-1:0] data_out, output reg signed [data_width-1:0] data_out,
output full, output full,
output empty, output empty,
input [data_width-1:0] data_in, input signed [data_width-1:0] data_in,
input clk, input clk,
input rst_a, input rst_a,
input wr_en, input wr_en,
@@ -22,8 +22,8 @@ module sync_fifo #(
reg [address_width-1:0] wr_pointer; reg [address_width-1:0] wr_pointer;
reg [address_width-1:0] rd_pointer; reg [address_width-1:0] rd_pointer;
reg [address_width :0] status_count; reg [address_width :0] status_count;
reg [data_width-1:0] data_out ; reg signed [data_width-1:0] data_out ;
wire [data_width-1:0] data_ram ; wire signed [data_width-1:0] data_ram ;
@@ -67,7 +67,7 @@ wire [data_width-1:0] data_ram ;
assign full = (status_count == (ram_depth)); assign full = (status_count == (ram_depth));
assign empty = (status_count == 0); assign empty = (status_count == 0);
ram #( blockram #(
.DEPTH(ram_depth), .DEPTH(ram_depth),
.ADDR_WIDTH(address_width), .ADDR_WIDTH(address_width),
.DATA_WIDTH(data_width) .DATA_WIDTH(data_width)