91 lines
2.3 KiB
Verilog
91 lines
2.3 KiB
Verilog
// Fifo code source:
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// https://vlsicoding.blogspot.com/2013/11/verilog-code-for-synchronous-fifo.html
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//
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module sync_fifo #( parameter
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//---------------parametre declaration
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data_width = 4,
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address_width = 4,
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ram_depth = 16
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)(
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//--------------input output port declaration
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output reg signed [data_width-1:0] data_out,
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output full,
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output empty,
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input signed [data_width-1:0] data_in,
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input clk,
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input rst_a,
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input wr_en,
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input rd_en);
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//--------------internal register declaration
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reg [address_width-1:0] wr_pointer;
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reg [address_width-1:0] rd_pointer;
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reg [address_width :0] status_count;
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reg signed [data_width-1:0] data_out ;
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wire signed [data_width-1:0] data_ram ;
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//--------------wr_pointer pointing to write address
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always @ (posedge clk,posedge rst_a)
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begin
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if(rst_a)
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wr_pointer = 0;
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else if(wr_en)
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wr_pointer = wr_pointer+1;
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end
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//-------------rd_pointer points to read address
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always @ (posedge clk,posedge rst_a)
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begin
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if(rst_a)
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rd_pointer = 0;
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else if(rd_en)
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rd_pointer = rd_pointer+1;
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end
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//-------------read from FIFO
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always @ (posedge clk,posedge rst_a)
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begin
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if(rst_a)
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data_out=0;
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else if(rd_en)
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data_out=data_ram;
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end
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//--------------Status pointer for full and empty checking
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always @ (posedge clk,posedge rst_a)
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begin
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if(rst_a)
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status_count = 0;
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else if(wr_en && !rd_en && (status_count != ram_depth))
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status_count = status_count + 1;
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else if(rd_en && !wr_en && (status_count != 0))
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status_count = status_count - 1;
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end // always @ (posedge clk,posedge rst_a)
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assign full = (status_count == (ram_depth));
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assign empty = (status_count == 0);
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blockram #(
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.DEPTH(ram_depth),
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.ADDR_WIDTH(address_width),
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.DATA_WIDTH(data_width)
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) memory1 (
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.addra(wr_pointer),
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.addrb(rd_pointer),
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.dia(data_in),
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.dib(),
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.doa(),
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.dob(data_ram),
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.wea(wr_en),
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.web(1'b0),
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.ena(1'b1),
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.enb(rd_en),
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.clka(clk),
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.clkb(clk)
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);
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endmodule // sync_fifo
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