diff --git a/blockram.v b/blockram.v
index 04667e6..44cb0a2 100644
--- a/blockram.v
+++ b/blockram.v
@@ -7,16 +7,16 @@
 // Dual-Port Block RAM with Two Write Ports
 // File: blobkram.v
 
-module ram #( parameter
+module blockram #( parameter
     DEPTH =  16,
     ADDR_WIDTH = 4, 
     DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
 
 input                       clka,clkb,ena,enb,wea,web;
 input   [ADDR_WIDTH-1:0]    addra,addrb;
-input   [DATA_WIDTH-1:0]    dia,dib;
-output  [DATA_WIDTH-1:0]    doa,dob;
-reg     [ADDR_WIDTH-1:0]    ram     [ DEPTH - 1 :0];
+input  signed [DATA_WIDTH-1:0]    dia,dib;
+output signed [DATA_WIDTH-1:0]    doa,dob;
+reg     [DATA_WIDTH-1:0]    ram     [ DEPTH - 1 :0];
 reg     [DATA_WIDTH-1:0]    doa,dob;
 
 always @(posedge clka)
diff --git a/effect_controler.v b/effect_controler.v
index b4fd634..4a321d4 100644
--- a/effect_controler.v
+++ b/effect_controler.v
@@ -7,8 +7,8 @@ module effect_controler #( parameter
     input                               reset,
     input   signed      [d_width-1: 0]  i_l_data,
     input   signed      [d_width-1: 0]  i_r_data,
-    output   signed  [d_width-1: 0]  o_l_data,
-    output   signed  [d_width-1: 0]  o_r_data
+    output  signed      [d_width-1: 0]  o_l_data,
+    output  signed      [d_width-1: 0]  o_r_data
 );
 
 
diff --git a/sync_fifo.v b/sync_fifo.v
index 4395c07..da787fc 100644
--- a/sync_fifo.v
+++ b/sync_fifo.v
@@ -1,17 +1,17 @@
 // Fifo code source:
 // https://vlsicoding.blogspot.com/2013/11/verilog-code-for-synchronous-fifo.html
 // 
-module sync_fifo #(
+module sync_fifo #( parameter
 //---------------parametre declaration
-   parameter    data_width       = 4,
-   parameter    address_width    = 4,
-   parameter    ram_depth        = 16 
+   data_width       = 4,
+   address_width    = 4,
+   ram_depth        = 16 
 )(
 //--------------input output port declaration
-   output reg  [data_width-1:0]  data_out,
+   output reg signed [data_width-1:0]  data_out,
    output                        full,
    output                        empty,
-   input       [data_width-1:0]  data_in,
+   input     signed  [data_width-1:0]  data_in,
    input                         clk,
    input                         rst_a,
    input                         wr_en,
@@ -22,8 +22,8 @@ module sync_fifo #(
 reg      [address_width-1:0]     wr_pointer;
 reg      [address_width-1:0]     rd_pointer;
 reg      [address_width :0]      status_count;
-reg      [data_width-1:0]        data_out ;
-wire     [data_width-1:0]        data_ram ;
+reg   signed   [data_width-1:0]        data_out ;
+wire  signed   [data_width-1:0]        data_ram ;
 
 
  
@@ -67,7 +67,7 @@ wire     [data_width-1:0]        data_ram ;
 assign full = (status_count == (ram_depth));
 assign empty = (status_count == 0);
  
-ram #( 
+blockram #( 
    .DEPTH(ram_depth),
    .ADDR_WIDTH(address_width),
    .DATA_WIDTH(data_width)