26 lines
655 B
Verilog
26 lines
655 B
Verilog
module lookuptable(
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input [7 :0] in,
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output reg [7 :0] out);
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reg [7 :0] out = 8'h0;
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always@* begin
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case (in)
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8'd0 : out <= 8'b00000000;
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8'd1 : out <= 8'b00011001;
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8'd2 : out <= 8'b00101101;
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8'd3 : out <= 8'b00111011;
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8'd4 : out <= 8'b01000000;
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8'd5 : out <= 8'b00111011;
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8'd6 : out <= 8'b00101101;
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8'd7 : out <= 8'b00011001;
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8'd8 : out <= 8'b00000000;
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8'd9 : out <= 8'b11101000;
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8'd10 : out <= 8'b11010011;
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8'd11 : out <= 8'b11000101;
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8'd12 : out <= 8'b11000000;
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8'd13 : out <= 8'b11000101;
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8'd14 : out <= 8'b11010011;
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8'd15 : out <= 8'b11101000;
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default : out <= 8'b00000000;
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endcase
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end
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endmodule |