32 lines
1.3 KiB
Plaintext
32 lines
1.3 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, the Altera Quartus II License Agreement,
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# the Altera MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Altera and sold by Altera or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
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# Date created = 22:16:23 March 21, 2018
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "15.0"
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DATE = "22:16:23 March 21, 2018"
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# Revisions
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PROJECT_REVISION = "dds_vhdl"
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