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DDS module and test bench finished

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This commit is contained in:
Imants Pulkstenis
2020-04-01 21:35:27 +03:00
parent c8581dbe68
commit 1598022c70
6 changed files with 246 additions and 67 deletions
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ps4/dds_vhdl/dds_vhdl.v
+33 -5
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@@ -26,12 +26,40 @@ module dds_vhdl#( parameter
output [phase_width - 1:0] phase_out,
output [data_width - 1:0] signal_out);
// define inside of the module
reg [phase_width - 1:0] r_phase_incr = 'd0;
reg [phase_width - 1:0] r_phase_out = 'd0;
// Phase increment – determines output frequency
always@(posedge clk)begin
if (rst) begin
r_phase_incr <= 0; end
else begin
r_phase_incr <= phase_incr; end
end
// Phase accumulator – the «counter»
always@(posedge clk)begin
if (rst) begin
r_phase_out <= 0; end
else begin
r_phase_out <= phase_out + phase_incr; end
end
// Look-up table – memory where waveform is stored
lookuptable lookuptable (
.in(),
.out());
.phase( // mux
(control== 0) ? 4'b0 :
(control== 1) ? {2'b0, phase_out[phase_width - 3:0] } :
(control== 2) ? {1'b0, phase_out[phase_width - 2:0] } :
phase_out
// end of MUX
),
.sin(signal_out),
.cos());
assign phase_out = r_phase_out;
endmodule
ps4/dds_vhdl/dds_vhdl_tb.v
+87
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@@ -0,0 +1,87 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 01.04.2020
// Project name - PS04
// Module name - test bench of DDS (direct digital synthesis)
//
// Detailed module description:
// This module generete clk signal for
// top module of dds_vhdl project
// The test is executed using Icarus Verilog!
//
// The result can be evaluated in GTKwave application.
// Code:
// iverilog -o output.vvp dds_vhdl_tb.v && vvp output.vvp
// gtkwave -f wave.vcd
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
//sub modules
`include "lookuptable.v"
//top module
`include "dds_vhdl.v"
//define module and connections to outside
module dds_vhdl_tb #( parameter
phase_width = 4,
data_width = 8
)();
//define inside use signals
reg clk = 1'b0;
reg rst = 1'b0;
reg [1:0] r_control = 'd3;
reg [phase_width - 1:0] r_phase_incr = 'd1;
//---------Test script----------------
// 50% duty cycle clock
always #0.5 clk <= ~clk;
//-----Unit Under test---------------
dds_vhdl #(
.data_width(8)
) unit_under_test (
.clk(clk),
.rst(rst),
.control(r_control),
.phase_incr(r_phase_incr),
.phase_out(),
.signal_out()
);
//---------Test--------------------
initial begin
rst = 1;
#10;
rst = 0;
#100
r_control = 2;
#100
r_control = 1;
#100
r_control = 0;
#100
$finish();
end
initial begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
endmodule
ps4/dds_vhdl/lookuptable.v
+44 -22
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@@ -1,26 +1,48 @@
module lookuptable(
input [7 :0] in,
output reg [7 :0] out);
reg [7 :0] out = 8'h0;
module lookuptable #( parameter phase_width = 4, data_width = 8)(
input [phase_width - 1 :0] phase,
output reg [data_width - 1 :0] sin,
output reg [data_width - 1 :0] cos);
always@* begin
case (in)
8'd0 : out <= 8'b00000000;
8'd1 : out <= 8'b00011001;
8'd2 : out <= 8'b00101101;
8'd3 : out <= 8'b00111011;
8'd4 : out <= 8'b01000000;
8'd5 : out <= 8'b00111011;
8'd6 : out <= 8'b00101101;
8'd7 : out <= 8'b00011001;
8'd8 : out <= 8'b00000000;
8'd9 : out <= 8'b11101000;
8'd10 : out <= 8'b11010011;
8'd11 : out <= 8'b11000101;
8'd12 : out <= 8'b11000000;
8'd13 : out <= 8'b11000101;
8'd14 : out <= 8'b11010011;
8'd15 : out <= 8'b11101000;
default : out <= 8'b00000000;
case (phase[phase_width - 1 : 0])
4'd0 : sin[data_width - 1 : 0] <= 8'b00000000;
4'd1 : sin[data_width - 1 : 0] <= 8'b00011001;
4'd2 : sin[data_width - 1 : 0] <= 8'b00101101;
4'd3 : sin[data_width - 1 : 0] <= 8'b00111011;
4'd4 : sin[data_width - 1 : 0] <= 8'b01000000;
4'd5 : sin[data_width - 1 : 0] <= 8'b00111011;
4'd6 : sin[data_width - 1 : 0] <= 8'b00101101;
4'd7 : sin[data_width - 1 : 0] <= 8'b00011001;
4'd8 : sin[data_width - 1 : 0] <= 8'b00000000;
4'd9 : sin[data_width - 1 : 0] <= 8'b11101000;
4'd10 : sin[data_width - 1 : 0] <= 8'b11010011;
4'd11 : sin[data_width - 1 : 0] <= 8'b11000101;
4'd12 : sin[data_width - 1 : 0] <= 8'b11000000;
4'd13 : sin[data_width - 1 : 0] <= 8'b11000101;
4'd14 : sin[data_width - 1 : 0] <= 8'b11010011;
4'd15 : sin[data_width - 1 : 0] <= 8'b11101000;
default : sin[data_width - 1 : 0] <= 8'b00000000;
endcase
end
always@* begin
case (phase[phase_width - 1 : 0])
4'd0 : cos[data_width - 1 : 0] <= 8'b01000000;
4'd1 : cos[data_width - 1 : 0] <= 8'b00111011;
4'd2 : cos[data_width - 1 : 0] <= 8'b00101101;
4'd3 : cos[data_width - 1 : 0] <= 8'b00011001;
4'd4 : cos[data_width - 1 : 0] <= 8'b00000000;
4'd5 : cos[data_width - 1 : 0] <= 8'b11101000;
4'd6 : cos[data_width - 1 : 0] <= 8'b11010011;
4'd7 : cos[data_width - 1 : 0] <= 8'b11000101;
4'd8 : cos[data_width - 1 : 0] <= 8'b11000000;
4'd9 : cos[data_width - 1 : 0] <= 8'b11000101;
4'd10 : cos[data_width - 1 : 0] <= 8'b11010011;
4'd11 : cos[data_width - 1 : 0] <= 8'b11101000;
4'd12 : cos[data_width - 1 : 0] <= 8'b00000000;
4'd13 : cos[data_width - 1 : 0] <= 8'b00011001;
4'd14 : cos[data_width - 1 : 0] <= 8'b00101101;
4'd15 : cos[data_width - 1 : 0] <= 8'b00111011;
default : cos[data_width - 1 : 0] <= 8'b01000000;
endcase
end
endmodule