87 lines
1.8 KiB
Verilog
87 lines
1.8 KiB
Verilog
/////////////////////////////////////////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 01.04.2020
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// Project name - PS04
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// Module name - test bench of DDS (direct digital synthesis)
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//
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// Detailed module description:
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// This module generete clk signal for
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// top module of dds_vhdl project
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// The test is executed using Icarus Verilog!
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//
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// The result can be evaluated in GTKwave application.
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// Code:
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// iverilog -o output.vvp dds_vhdl_tb.v && vvp output.vvp
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// gtkwave -f wave.vcd
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//
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// Revision:
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// A - initial design
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// B -
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// C -
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//
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///////////////////////////////////////////////////////////////////
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//sub modules
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`include "lookuptable.v"
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//top module
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`include "dds_vhdl.v"
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//define module and connections to outside
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module dds_vhdl_tb #( parameter
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phase_width = 4,
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data_width = 8
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)();
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//define inside use signals
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reg clk = 1'b0;
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reg rst = 1'b0;
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reg [1:0] r_control = 'd3;
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reg [phase_width - 1:0] r_phase_incr = 'd1;
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//---------Test script----------------
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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//-----Unit Under test---------------
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dds_vhdl #(
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.data_width(8)
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) unit_under_test (
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.clk(clk),
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.rst(rst),
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.control(r_control),
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.phase_incr(r_phase_incr),
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.phase_out(),
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.signal_out()
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);
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//---------Test--------------------
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initial begin
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rst = 1;
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#10;
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rst = 0;
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#100
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r_control = 2;
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#100
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r_control = 1;
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#100
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r_control = 0;
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#100
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$finish();
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end
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initial begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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$display("----------------------------------------------");
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$display(" ");
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end
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endmodule |