Imants Pulkstenis
8da9e7da7c
i2s sender and i2s receiver. Also add JXADC_controler for logic analizer.
23 lines
494 B
Verilog
23 lines
494 B
Verilog
module effect_controler #( parameter
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d_width = 24 // data width
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)(
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// input clk,
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input signed [d_width-1: 0] i_l_data,
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input signed [d_width-1: 0] i_r_data,
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output reg signed [d_width-1: 0] o_l_data,
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output reg signed [d_width-1: 0] o_r_data
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);
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always@* begin
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o_l_data <= i_l_data;
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o_r_data <= i_r_data;
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end
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//assign o_l_data = i_l_data;
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//assign o_r_data = i_r_data;
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//assign o_l_data = 24'h000000;
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//assign o_r_data = 24'h400008;
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endmodule |