19 lines
448 B
Verilog
19 lines
448 B
Verilog
module write_pointer(
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output [4:0] wptr,
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output fifo_we,
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input wr,
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input fifo_full,
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input clk,
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input rst_n);
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assign fifo_we = (~fifo_full) & wr;
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always @(posedge clk or negedge rst_n)
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begin
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if(~rst_n) wptr <= 'b0;
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else if(fifo_we)
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wptr <= wptr + 'b1;
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else
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wptr <= wptr;
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end
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endmodule |