61 lines
1.8 KiB
Verilog
61 lines
1.8 KiB
Verilog
module status_signal(
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output fifo_full,
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output fifo_empty,
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output fifo_threshold,
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output fifo_overflow,
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output fifo_underflow,
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input wr,
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input rd,
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input fifo_we,
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input fifo_rd,
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input [4:0] wptr,
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input [4:0] rptr,
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input clk,
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input rst_n);
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wire fbit_comp,
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overflow_set,
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underflow_set;
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wire pointer_equal;
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wire [4:0] pointer_result;
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reg fifo_full,
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fifo_empty,
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fifo_threshold,
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fifo_overflow,
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fifo_underflow;
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assign fbit_comp = wptr[4] ^ rptr[4];
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assign pointer_equal = (wptr[3:0] - rptr[3:0]) ? 0:1;
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assign pointer_result = wptr[4:0] - rptr[4:0];
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assign overflow_set = fifo_full & wr;
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assign underflow_set = fifo_empty&rd;
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always @(*)
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begin
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fifo_full =fbit_comp & pointer_equal;
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fifo_empty = (~fbit_comp) & pointer_equal;
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fifo_threshold = (pointer_result[4]||pointer_result[3]) ? 1:0;
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end
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always @(posedge clk or negedge rst_n)
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begin
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if(~rst_n) fifo_overflow <=0;
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else if((overflow_set==1)&&(fifo_rd==0))
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fifo_overflow <=1;
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else if(fifo_rd)
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fifo_overflow <=0;
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else
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fifo_overflow <= fifo_overflow;
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end
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always @(posedge clk or negedge rst_n)
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begin
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if(~rst_n) fifo_underflow <=0;
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else if((underflow_set==1)&&(fifo_we==0))
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fifo_underflow <=1;
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else if(fifo_we)
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fifo_underflow <=0;
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else
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fifo_underflow <= fifo_underflow;
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end
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endmodule
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