20 lines
450 B
Verilog
20 lines
450 B
Verilog
module memory_array(
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output [7:0] data_out,
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input [7:0] data_in,
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input clk,
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input fifo_we,
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input [4:0] wptr,
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input [4:0] rptr
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);
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reg [7:0] data_out2 [15:0];
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wire [7:0] data_out;
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always @(posedge clk)
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begin
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if(fifo_we)
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data_out2[wptr[3:0]] <=data_in ;
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end
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assign data_out = data_out2[rptr[3:0]];
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endmodule
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