65 lines
1.5 KiB
Verilog
65 lines
1.5 KiB
Verilog
// Sample code from https://www.fpga4student.com/2017/01/verilog-code-for-fifo-memory.html
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// with some modifications
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module fifo_mem(
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output [7:0] data_out,
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output fifo_full,
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output fifo_empty,
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output fifo_threshold,
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output fifo_overflow,
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output fifo_underflow,
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input clk,
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input rst_n,
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input wr,
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input rd,
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input [7:0] data_in
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);
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wire [4:0] wptr,
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rptr;
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wire fifo_we,
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fifo_rd;
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// sub modules
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write_pointer write_pointer(
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.wptr(wptr),
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.fifo_we(fifo_we),
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.wr(wr),
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.fifo_full(fifo_full),
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.clk(clk),
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.rst_n(rst_n)
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);
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read_pointer read_pointer(
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.rptr(rptr),
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.fifo_rd(fifo_rd),
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.rd(rd),
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.fifo_empty(fifo_empty),
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.clk(clk),
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.rst_n(rst_n)
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);
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memory_array memory_array(
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.data_out(data_out),
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.data_in(data_in),
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.clk(clk),
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.fifo_we(fifo_we),
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.wptr(wptr),
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.rptr(rptr)
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);
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status_signal status_signal(
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.fifo_full(fifo_full),
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.fifo_empty(fifo_empty),
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.fifo_threshold(),
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.fifo_overflow(fifo_overflow),
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.fifo_underflow(fifo_underflow),
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.wr(wr),
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.rd(rd),
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.fifo_we(fifo_we),
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.fifo_rd(fifo_rd),
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.wptr(wptr),
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.rptr(rptr),
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.clk(clk),
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.rst_n(rst_n)
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);
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endmodule
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