75 lines
3.0 KiB
Verilog
75 lines
3.0 KiB
Verilog
module effect_controler #( parameter
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d_width = 24, // data width
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address_width = 4, //
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ram_depth = 16, //
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memory_d_width = 16 //
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)(
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input mclk, // io_module clock
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input clk, // main clock
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input reset,
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input signed [d_width-1: 0] i_l_data,
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input signed [d_width-1: 0] i_r_data, // not used
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output signed [d_width-1: 0] o_l_data,
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output signed [d_width-1: 0] o_r_data,
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output signed [memory_d_width-1: 0] o_data_to_eff, // Data output to effects module
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output o_data_valid, // data valid to read (FIFO not empty). data valid signal to effect module
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input i_read_enable,
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input signed [memory_d_width-1: 0] i_data_from_eff, // Data output to effects module
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input i_dv_from_eff // data valid to read (FIFO not empty). data valid signal to effect module
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);
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wire signed [memory_d_width-1: 0] w_o_data; //output data to io_module
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//wire signed [memory_d_width-1: 0] w_o_data_eff; //output data to effects module
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wire w_empty_in, w_full_in;
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wire w_empty_out, w_full_out;
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wire [address_width-1:0] w_data_fill_input; // shows how full are in FIFO memmory for intput
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wire [address_width-1:0] w_data_fill_output; // shows how full are in FIFO memmory for output
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assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler
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assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left
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assign o_data_valid = ~w_empty_in;
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// Input FIFO
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sync_fifo #(
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.ram_depth(ram_depth), // ram memory depth
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.address_width(address_width), // ram memory address width
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.data_width(memory_d_width) // memory data width
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) fifo_input (
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.data_out(o_data_to_eff),
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.full(w_full_in),
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.empty(w_empty_in),
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.data_fill(w_data_fill_input),
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.data_in(i_l_data[ d_width-1 : d_width - memory_d_width ]),
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.w_clk(mclk),
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.r_clk(clk),
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.reset(reset),
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.wr_en( w_full_in ? 1'b0 : 1'b1 ), // checking is FIFO full
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.rd_en( w_empty_in ? 1'b0 : i_read_enable ) // checking is FIFO empty
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);
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// Output FIFO
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sync_fifo #(
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.ram_depth(ram_depth), // ram memory depth
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.address_width(address_width), // ram memory address width
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.data_width(memory_d_width) // memory data width
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) fifo_output (
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.data_out(w_o_data),
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.full(w_full_out),
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.empty(w_empty_out),
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.data_fill(w_data_fill),
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.data_in(i_data_from_eff),
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.w_clk(clk),
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.r_clk(mclk),
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.reset(reset),
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.wr_en( w_full_out ? 1'b0 : i_dv_from_eff ), // checking is FIFO full
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.rd_en( w_empty_out ? 1'b0 : 1'b1 ) // checking is FIFO empty
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);
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endmodule |