46 lines
740 B
Verilog
46 lines
740 B
Verilog
// TOP module
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//
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//
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// `include "clock_divider_param.v"
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// `include "clock_enable_param.v"
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module top #( parameter
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//pattern generator paremater
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SPEED = 300,
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//enable signal parameters
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WAIT = 1,
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WAIT_WIDTH = 2,
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)(
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input clk
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);
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//------internal wires and registers--------
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wire w_enable;
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wire clk50;
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//-----sub modules--------------------------
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clock_enable_param #(
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.WAIT(WAIT),
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.WIDTH(WAIT_WIDTH)
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) clock_enable1 (
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.clk(clk),
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.enable(w_enable)
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);
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clock_divider #(
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.DIVIDER(1),
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.WIDTH(3)
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) clk50mhz_gen (
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.clk(clk),
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.clk_out(clk50)
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);
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debounce_switch debounce_switch_reset(
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.clk(clk),
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.i_switch(),
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.o_switch()
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);
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endmodule |