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merge into: imants/audio_effects_FPGA:master
Branches Tags
imants/audio_effects_FPGA:master imants/audio_effects_FPGA:Audio_to_FFT imants/audio_effects_FPGA:plain_audio_loopback
...
pull from: imants/audio_effects_FPGA:Audio_to_FFT
Branches Tags
imants/audio_effects_FPGA:Audio_to_FFT imants/audio_effects_FPGA:master imants/audio_effects_FPGA:plain_audio_loopback
3 Commits
master ... Audio_to_FFT
Author SHA1 Message Date
Imants Pulkstenis ad59f40a9d Changes to Matlab model 2020-04-04 16:06:23 +03:00
Imants Pulkstenis 5f98346282 Add VGA module 2020-04-04 01:40:11 +03:00
Imants Pulkstenis ab92a0c8a8 Initial commit for new branch 2020-04-04 00:16:44 +03:00
36 changed files with 774 additions and 2190 deletions
Expand all files Collapse all files
.gitignore
-2
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@@ -1,2 +0,0 @@
*.asv
matlab/sample_code_.m
Basys3_Master.xdc
+54 -54
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@@ -83,33 +83,33 @@ set_property PACKAGE_PIN L1 [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##7 segment display
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
#7 segment display
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
#set_property PACKAGE_PIN V7 [get_ports dp]
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property PACKAGE_PIN V7 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports dp]
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
##Buttons
@@ -237,35 +237,35 @@ set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
##VGA Connector
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
#set_property PACKAGE_PIN P19 [get_ports Hsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
#set_property PACKAGE_PIN R19 [get_ports Vsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
#VGA Connector
set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
set_property PACKAGE_PIN P19 [get_ports Hsync]
set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
set_property PACKAGE_PIN R19 [get_ports Vsync]
set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
##USB-RS232 Interface
JXADC_controler.v
+16
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@@ -1,5 +1,21 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - JXADC PMOD connector output
//
// Detailed module description:
// This module outputs signals to JXADC PMOD
// where logic analyzer are conected.
// Port is connected to logic analizer
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module JXADC_controler (
input ch0,
README.md
+2 -17
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@@ -2,25 +2,10 @@
![GitHub commit activity](https://img.shields.io/github/commit-activity/m/clockfix/audio_effects_FPGA?style=plastic)
![GitHub last commit](https://img.shields.io/github/last-commit/clockfix/audio_effects_FPGA?style=plastic)
![GitHub contributors](https://img.shields.io/github/contributors/clockfix/audio_effects_FPGA?style=plastic)
# Audio effects on FPGA
# Audio FFT on FPGA
Audio effect synthesizer on FPGA
Audio FFT on FPGA
Audio hardware
![PMOD_I2S2](https://euborw.bl.files.1drv.com/y4mwscr7u3Q0WJKuOjfrLSFswmMhJFcQz_qvUDQmWPsWANUPPx3s-RrdHahplWN4MPxWtFJAZCzZokzS9oG3hJRHTa8-hztUF-5ix6DoEZ3FbW79HuWuWykaC6-vPQCz_jN-qtZzENmEM_CL7x6Fu-V3fVBwSbUUZ1B4FpyTJbHc2y09jmmIoznP9JKdHkloQC22fRvzkGEwn-uEL7m5GIYtg/pmod_i2s2.jpg) ![PMOD_I2S2_package](https://jhuenw.bl.files.1drv.com/y4mh-JRwzfInJGsB7npvB02QFP4E8O0fYseJrh7mCKZPhDtrRKAkyIU4vrSgIPZ57SPrRugP-CoS5pu-_W9fq1E2gV9SOYeyPc2In_a5uqQzCtwXbUYRvOQnHEt-zomphOLXn2Uw7RpaKbKLNvgQfF-pJNqbiX5LAaW5zODYNF66IESQ3uHqDSOCEtjt620oITZFzO71EyDkpSPB3bvZ61J6Q/pmod_i2s2_package.png)
i2s timing diagram from PulseView
![i2s timing diagram](https://jxuqnw.ch.files.1drv.com/y4m-dZeGZ7098LnxNfhcXYLc_boX5bUNKolrZoOikvJ15bhmx83OEfjXsL0DOx4bJQwo9Nj8JhPdbH3-p2_NsPtkQLQMjqqvHQD1aoTLU4iCGlzmuDkeRaJ4hOWEjlSxfPTpLuJmFxd3Co8m7PUNAHw-lSomMgNqrO4Sw_8E4K-vfiS2ijUOfIdlW4VUDLv0Dku1zcMel3jQGcMSIH0GiQyRA/i2s-loopback.png?psid=1)
Top module
![Top module_sh](https://sqtelw.ch.files.1drv.com/y4mxBDwlvgiYYZpsOjIUey0ctL7StvY-ymQdAxhs5_GToLB8sdDlbh9qd3IBUiguuYbraYpqDg2BVUclm8n7UIdIcLIz0468d-e_VIgsLgY13Z839dn2THBu_PKbq3MLZOmwJNjH0Jz8qq0SNr2UjZkyJjSmdmESf44Qv5DrNMVEhvl6jLvw0FxN23E7dme2MloArlCMLJ9PznU9qzNhD2RLw/top-audio-effects.png?psid=1)
Edited effect control module - now it has input and output FIFO memory
![efect_controler](https://pgow6w.ch.files.1drv.com/y4mG--fP9LI78p-SQYukYLlqkbHOkXCmfO6cLVgHcND0Z5G7J7-75dlO2Yva33k0KdAt6DBWdQDT_TH_6L_pjNxXHaczVTaUecui2-qpfOD4EW0GP8TtewGPuC7wsESNzd0Nsl4QSDfLzFV8uZZWeq2_VTadlnqPmQRSfs9115fiK8yLqdl17fzZZ4Q0LuhbOlbFV0aOpUqC0zBi6_FxK_xtw/efect_controler.png?psid=1)
IO module
![io_module](https://b6w9pw.ch.files.1drv.com/y4mgPXnMZOMUJWVUBhbHNP217wE84t29_bt9uDZ7lbozZTPFiq3Ncan_uSvk7YjRzmkIPma5t_dcwxAvLgd8ZV5n1GBIzJ5cCEiS1gCR0y7y4x5brYBBRXjJh5VXI0ITpQRCvlggTSzNZE4b7Ux8hvzoxa586RGty8d-a1eblClQE3GD4QAiPMV0CrT-ROt7axdN_ArKMn0HKHCYomtW3Gu4A/io_module.png?psid=4)
Effects module with one clipping effect
![io_module](https://py4mqq.ch.files.1drv.com/y4m3dgfUf1rxceMtUYiJ-Y9GBDS-E2vBBSFrZIh3-UEhRQifIn5Lq2OAAWUWKqsSTMDNNwTtkgEVy9ThtV3UNbjI1OdDDeFvC1tHPhXdbbpdPpasInNJgWDzTLhCE88uy48NYx_IRecy4zoXUrYg9_SaEWggmjloEwWd4KuSFBtSyopP0pHQ07nnUMuo4OyEhdZOfptzF-PS-J2ufYQSEVheg/effect_module.png?psid=1)
blockram.v
+16 -5
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@@ -1,11 +1,22 @@
// Code from:
// Vivado Design Suite
// User Guide
// Synthesis
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Dual-Port Block RAM
//
// Detailed module description:
// Code from: Vivado Design Suite User Guide Synthesis
// UG901 (v2018.3) December 19, 2018
//
// Dual-Port Block RAM with Two Write Ports
// File: blobkram.v
// File: blobkram.v
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module rams_tdp_rf_rf #( parameter
DEPTH = 16,
clipping.v
-107
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@@ -1,107 +0,0 @@
module clipping_effect #( parameter
data_width = 16 // data width
)(
input clk,
input reset,
input signed [data_width-1: 0] i_data,
output signed [data_width-1: 0] o_data,
input signed [data_width-1: 0] i_treshhold,
input i_read_done,
output o_read_enable,
output o_data_valid,
input i_data_ready
);
//-------------Internal Constants---------------------------
localparam [1:0] IDLE = 'd0,
CLIP = 'd1,
OUTPUT = 'd2,
CLEAR = 'd3;
reg [1:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0;
reg [data_width-1: 0] r_treshhold_p = 'b0;
reg [data_width-1: 0] r_treshhold_n = 'b0;
reg r_read_enable = 0;
reg r_data_valid = 0;
assign o_read_enable = r_read_enable;
assign o_data_valid = r_data_valid;
assign o_data = r_data;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (~reset) begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always @(posedge clk ) begin
if (reset) begin
r_next <= IDLE;
r_read_enable <= 0; // redy to read data
r_data_valid <= 0;
end
else begin
case(r_state)
IDLE : begin
if (i_data_ready == 1) begin
r_next <= CLIP;
r_data <= i_data;
r_treshhold_p <= i_treshhold;
r_treshhold_n <= (~i_treshhold) + 1; // two compliment
r_read_enable <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_enable <= 1; // redy to read data
r_data_valid <= 0;
end
end
CLIP : begin
case (r_data[data_width-1])
0 : begin // positive number
if (r_data > r_treshhold_p) begin
r_data <= r_treshhold_p; end
end
1 : begin // negative number
if (r_data < r_treshhold_n) begin
r_data <= r_treshhold_n; end
end
endcase
r_next <= OUTPUT;
r_data_valid <= 0;
r_read_enable <= 0; // read disable
end
OUTPUT : begin
if (i_read_done == 1) begin
r_next <= CLEAR;
r_data_valid <= 0;
r_read_enable <= 0;
end
else begin
r_next <= OUTPUT;
r_data_valid <= 1;
r_read_enable <= 0; // read disable
end
end
CLEAR : begin
r_next <= IDLE;
r_data_valid <= 0;
r_read_enable <= 1;
end
default: begin
r_next <= IDLE; // on error
end
endcase
end
end
endmodule
clipping_tb.v
-85
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@@ -1,85 +0,0 @@
// This file is Test Bench for clipping module
//
//
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
//sub modules
`include "clipping.v"
module clipping_tb#( parameter
data_width = 16 // data width
)();
reg clk = 1'b0;
reg signed [data_width-1 : 0] i_data = 'b0;
reg i_read_done = 0;
reg i_data_ready = 0;
// 50% duty cycle clock
always #0.5 clk <= ~clk;
clipping_effect #(
.data_width(data_width) // data width
) UUT (
.clk(clk),
.reset(1'b0),
.i_treshhold( 16'haff ),
.i_data(i_data),
.i_read_done(i_read_done), // read done from effects controler
.i_data_ready(i_data_ready),
.o_data(),
.o_read_enable(),
.o_data_valid()
);
initial begin
#030;
i_data = 'haaa;
#005;
i_data_ready = 1;
#005;
i_data = 'h0fa;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
#005;
i_data = -16'd3000;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
#005;
i_data = 852;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
end
initial begin
#030_000;
$display("*");
$display(" ");
$display("Use this command to open timing diagram:");
$display("gtkwave -f wave.vcd");
$display("----------------------------------------------");
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
end
endmodule
clock_divider_param.v → clock_divider.v
+15 -2
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@@ -1,11 +1,24 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - clock divider
//
// Detailed module description:
// This module devide FPGA input clock
// by DIVIDER. Result is 50% duty cicle
// pulses.
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module clock_divider #(
parameter DIVIDER =2,
parameter WIDTH =2
parameter WIDTH =2,
parameter DIVIDER =(2**WIDTH)
) (
input clk_in,
output clk_out);
clock_divider_param_tb.v
-40
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@@ -1,40 +0,0 @@
// `timescale [time unit] / [time precision]
`timescale 10 ps / 1 ps
`include "clock_divider_param.v"
module clock_divider_param_tb ();
reg clk = 1'b0;
wire enable;
always #1 clk <= ~clk;
initial
begin
#100;
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
clock_divider #(
.DIVIDER(2),
.WIDTH(2)
) test_unit1 (
.clk(clk),
.enable(enable)
);
endmodule
clock_enable_param.v
-31
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@@ -1,31 +0,0 @@
// This module devide FPGA input clock
// by DIVIDER.
//
//
module clock_enable_param #(
parameter WAIT =1,
parameter WIDTH =1
) (
input clk,
output enable);
reg state=1'b0;
reg [WIDTH-1:0] counter = 1'b0 ;
always@(posedge clk)begin
if(counter == 0)begin
if (state == 1) begin
state <= 0;
counter <= WAIT - 1;
end
else begin
state <= 1;
counter <= 0;
end
end
else counter <= counter -1;
end
assign enable = state;
endmodule
clock_enable_tb.v
-61
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@@ -1,61 +0,0 @@
`include "clock_enable_param.v"
module clock_enable_tb();
reg clk = 1'b0;
wire enable0;
wire enable1;
wire enable2;
wire enable3;
always #1 clk <= ~clk;
initial
begin
#100;
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
clock_enable_param test_unit0(
.clk(clk),
.enable(enable0)
);
clock_enable_param #(
.WAIT(2),
.WIDTH(4)
) test_unit1(
.clk(clk),
.enable(enable1)
);
clock_enable_param #(
.WAIT(3),
.WIDTH(8)
)test_unit2(
.clk(clk),
.enable(enable2)
);
clock_enable_param #(
.WAIT(9),
.WIDTH(8)
)test_unit3(
.clk(clk),
.enable(enable3)
);
endmodule
d_flip-flop.v
+15
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@@ -1,3 +1,18 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Flip-Flop
//
// Detailed module description:
// Simple Flip-Flop
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module d_flipflop_sync_rst(
input D,
output reg Q,
debounce_switch.v
+17 -1
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@@ -1,4 +1,20 @@
module debounce_switch(
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Debounce switch
//
// Detailed module description:
// This is Debounce switch module.
// It toggles output only when input is in
// HIGH or LOW state atleast for 10ms
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////module debounce_switch(
input clk,
input i_switch,
output o_switch);
debounce_switch_tb.v
+15 -2
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@@ -1,6 +1,19 @@
// This file is Test Bench for top_vga_mem module
//
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Test Bench for debounce switch
//
// Detailed module description:
// This file is Test Bench for debounce switch module
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
effect_controler.v
-108
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@@ -1,108 +0,0 @@
module effect_controler #( parameter
d_width = 24, // data width
address_width = 4, //
ram_depth = 16, //
memory_d_width = 16 //
)(
input mclk, // io_module clock
input clk, // main clock
input reset,
input signed [d_width-1: 0] i_l_data,
input signed [d_width-1: 0] i_r_data, // not used
output signed [d_width-1: 0] o_l_data,
output signed [d_width-1: 0] o_r_data,
output o_read_done, // read done from effects module
output o_read_ready, // ready read from effects module
input [1:0] sw, // effect control swiches
output signed [memory_d_width-1: 0] o_data_to_eff, // Data output to effects module
output o_data_valid, // data valid to read (FIFO not empty). data valid signal to effect module
input i_read_enable, // enable read from input fifo
input signed [memory_d_width-1: 0] i_data_from_eff_sw0, // Data output to effects module
input signed [memory_d_width-1: 0] i_data_from_eff_sw1, // Data output to effects module
input i_dv_from_eff // data valid to read (FIFO not empty). data valid signal to effect module
);
wire signed [memory_d_width-1: 0] w_o_data; //output data to io_module
//wire signed [memory_d_width-1: 0] w_o_data_eff; //output data to effects module
wire w_empty_in, w_full_in;
wire w_empty_out, w_full_out;
wire [memory_d_width-1:0] w_data_to_fifo; // wire connets mixer to output fifo
wire [address_width-1:0] w_data_fill_input; // shows how full are in FIFO memmory for intput
wire [address_width-1:0] w_data_fill_output; // shows how full are in FIFO memmory for output
wire w_data_valid_to_fifo; // data valid to write output FIFO from mixer
assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler
assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left
assign o_data_valid = ~w_empty_in;
// Input FIFO
sync_fifo #(
.ram_depth(ram_depth), // ram memory depth
.address_width(address_width), // ram memory address width
.data_width(memory_d_width) // memory data width
) fifo_input (
.data_out(o_data_to_eff),
.full(w_full_in),
.empty(w_empty_in),
.data_fill(w_data_fill_input),
.data_in(i_l_data[ d_width-1 : d_width - memory_d_width ]),
.w_clk(mclk),
.r_clk(clk),
.reset(reset),
.wr_en( w_full_in ? 1'b0 : 1'b1 ), // checking is FIFO full
.rd_en( w_empty_in ? 1'b0 : i_read_enable ) // checking is FIFO empty
);
// Output FIFO
sync_fifo #(
.ram_depth(ram_depth), // ram memory depth
.address_width(address_width), // ram memory address width
.data_width(memory_d_width) // memory data width
) fifo_output (
.data_out(w_o_data),
.full(w_full_out),
.empty(w_empty_out),
.data_fill(w_data_fill),
.data_in(w_data_to_fifo),
.w_clk(clk),
.r_clk(mclk),
.reset(reset),
.wr_en( w_data_valid_to_fifo ), // checking of FIFO full are performing mixer module
.rd_en( w_empty_out ? 1'b0 : 1'b1 ) // checking is FIFO empty
);
// Effect mixer, performs audio data merging
effect_mixer #(
.data_width(memory_d_width) // memory data width
) effect_mixer (
.sw(sw),
.clk(clk),
.reset(reset),
.i_fifo_full(w_full_out),
.o_read_done(o_read_done), // read from effect module done
.o_read_ready(o_read_ready), // ready to read from effect module
.o_data(w_data_to_fifo), // data to output FIFO memory
.o_data_valid(w_data_valid_to_fifo),
.i_dv_from_eff(i_dv_from_eff),
.i_data_from_eff_sw0(i_data_from_eff_sw0), // Data output to effects module
.i_data_from_eff_sw1(i_data_from_eff_sw1)
);
endmodule
effect_mixer.v
-130
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@@ -1,130 +0,0 @@
module effect_mixer #( parameter
data_width = 16 // data width
)(
input clk,
input [1:0] sw,
input reset,
input i_fifo_full,
output signed [data_width-1: 0] o_data,
output o_read_done, // read from effect module done
output o_read_ready, // ready to read from effect module
output o_data_valid, // data valit to write in FIFO memory
input i_dv_from_eff,
input signed [data_width-1: 0] i_data_from_eff_sw0, // Data output to effects module
input signed [data_width-1: 0] i_data_from_eff_sw1
);
//-------------Internal Constants---------------------------
localparam [2:0] IDLE = 'd0,
ADD = 'd1,
NORM = 'd2,
OUTPUT = 'd3;
reg [2:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data_sw0 = 'b0;
reg signed [data_width-1: 0] r_data_sw1 = 'b0;
reg signed [data_width: 0] r_data_add = 'b0;
reg signed [data_width-1: 0] r_data_norm = 'b0;
reg r_read_done = 0;
reg r_read_ready = 0;
reg r_data_valid = 0;
assign o_read_done = r_read_done;
assign o_data_valid = r_data_valid;
assign o_data = r_data_norm;
assign o_read_ready = r_read_ready;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (reset == 1) begin
// clear state
r_state <= IDLE;
r_next <= IDLE;
end
else begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always @(posedge clk ) begin
case(r_state)
IDLE : begin
if (i_dv_from_eff == 1) begin
r_next <= ADD;
r_data_sw0 <= i_data_from_eff_sw0;
r_data_sw1 <= i_data_from_eff_sw1;
r_data_norm <= 'b0;
r_read_done <= 1;
r_read_ready <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_ready <= 1; // redy to read data
r_data_valid <= 0;
end
end
ADD : begin
case ( sw )
0 : begin // off all sound
r_data_add <= 0;
end
1 : begin // no effect only
r_data_add <= r_data_sw0;
end
2 : begin // clipping effect only
r_data_add <= r_data_sw1;
end
3 : begin // no effect and clipping effect
r_data_add <= r_data_sw0 + r_data_sw1;
end
endcase
r_next <= NORM;
r_read_done <= 0;
end
NORM : begin
case ( sw )
0 : begin // off all sound
r_data_norm <= 0;
end
1 : begin // no effect only
r_data_norm <= r_data_add[data_width-1: 0];
end
2 : begin // clipping effect only
r_data_norm <= r_data_add[data_width-1: 0];
end
3 : begin // no effect and clipping effect
r_data_norm <= r_data_add[data_width : 1] ; // Shift Right
end
endcase
r_next <= OUTPUT;
end
OUTPUT : begin
if ((i_fifo_full == 1) & (i_dv_from_eff == 1)) begin // wait for FIFO memory and data valid in effect module
r_next <= OUTPUT;
r_read_done <= 0;
r_read_ready <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_ready <= 0; // redy to read data
r_data_valid <= 1; // data valid to write in FIFO
end
end
default: r_next <= IDLE; // on error
endcase
end
endmodule
effect_module.v
-73
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@@ -1,73 +0,0 @@
module effect_module #( parameter
d_width = 16 // data width
)(
input clk,
input reset,
input [1:0] sw, // effect control switches
input [13:0] i_treshhold, // treshhold from switches
input i_data_ready, // data ready to read
input signed [d_width-1: 0] i_data, // data input form effect controler
input i_read_done, // read done from effects controler
output o_data_valid,
output o_read_enable,
// SW0 no effect
output signed [d_width-1: 0] o_data_sw0, // data output form effect controler
// SW1 clipping effect
output signed [d_width-1: 0] o_data_sw1 // data output form effect controler
);
// Wires for cliping effect
wire signed [d_width-1: 0] w_data_sw0;
wire w_read_enable_sw0;
wire w_data_valid_sw0;
wire signed [d_width-1: 0] w_data_sw1;
wire w_read_enable_sw1;
wire w_data_valid_sw1;
// asynchronous logic ---------------------------------------
assign o_data_sw0 = w_data_sw0;
assign o_data_sw1 = w_data_sw1;
assign o_read_enable = w_read_enable_sw0 & w_read_enable_sw1;
assign o_data_valid = w_data_valid_sw0 & w_data_valid_sw1;
// Individual effect modules -----------------------------
// no effect SW0
no_effect #(
.data_width(d_width) // data width
) no_effect (
.clk(clk),
.reset(reset),
.i_data(i_data),
.i_read_done(i_read_done), // read done from effects controler
.i_data_ready(i_data_ready),
.o_data(w_data_sw0),
.o_read_enable(w_read_enable_sw0),
.o_data_valid(w_data_valid_sw0)
);
// clipping effect SW1
clipping_effect #(
.data_width(d_width) // data width
) clipping_effect (
.clk(clk),
.reset(reset),
.i_treshhold( {2'b00, i_treshhold } ),
.i_data(i_data),
.i_read_done(i_read_done), // read done from effects controler
.i_data_ready(i_data_ready),
.o_data(w_data_sw1),
.o_read_enable(w_read_enable_sw1),
.o_data_valid(w_data_valid_sw1)
);
endmodule
effects_tb.v
-95
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@@ -1,95 +0,0 @@
// This file is Test Bench for clipping module
//
//
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
//sub modules
`include "clipping.v"
`include "no_effect.v"
//top module
`include "effect_module.v"
module effect_tb#( parameter
data_width = 16 // data width
)();
reg clk = 1'b0;
reg signed [data_width-1 : 0] i_data = 'b0;
reg i_read_done = 0;
reg i_data_ready = 0;
reg [1 : 0] sw = 2'b01;
// 50% duty cycle clock
always #0.5 clk <= ~clk;
//Effect module contains all individual effects
effect_module #(
.d_width(data_width) // data width
) effect_module (
.clk(clk),
.reset(1'b0),
.sw(sw), // effect control swiches
.i_treshhold(14'h0ff),
.i_data_ready(i_data_ready), // data ready to read
.i_read_done(i_read_done), // read done from effects controler
.i_data(i_data), // data input form effect controler
.o_read_enable(), // enable data reading
.o_data_valid(),
.o_data_sw0(),
.o_data_sw1()
);
initial begin
#030;
i_data = 'haaa;
#005;
i_data_ready = 1;
#005;
i_data = 'h0fa;
i_data_ready = 0;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
#005;
i_data = -16'd3000;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
#005;
i_data = 852;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
end
initial begin
#030_000;
$display("*");
$display(" ");
$display("Use this command to open timing diagram:");
$display("gtkwave -f wave.vcd");
$display("----------------------------------------------");
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
end
endmodule
horizontal_counter.v
+89
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@@ -0,0 +1,89 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - horizontal counter
//
// Detailed module description:
//
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module horizontal_counter #(
parameter
HSYNC_CLKS = 800,
HSYNC_DISPLAY = 640,
HSYNC_PULSE = 96,
HSYNC_FRONT_PORCH = 16,
HSYNC_BACK_PORCH = 48
)(
input clk,
output o_Hsync,
output o_h_display,
output [9:0] o_h_pixel
);
//----------Internal registers, constants and wariables-----
reg hsync_reg = 1'b1;
reg [9:0] counter_reg = 'h0;
reg [9:0] counter_pixel_reg = 'h0;
reg [2:0] r_state=HS_FRONT_PORCH, r_next=HS_FRONT_PORCH;
localparam [2:0] HS_FRONT_PORCH = 'h0,
HS_PULSE = 'h1,
HS_BACK_PORCH = 'h2,
HS_DISPLAY = 'h3;
//---------state register sequential always block-----------
always @(posedge clk ) begin
r_state <= r_next;
end
//----next state & outputs, combinational always block------
always@(posedge clk) begin
counter_reg <= counter_reg + 1;
case (r_state)
HS_FRONT_PORCH: begin
hsync_reg <= 1'b1;
if(counter_reg == HSYNC_FRONT_PORCH - 2)
r_next <= HS_PULSE;
end
HS_PULSE:begin
hsync_reg <= 1'b0;
if(counter_reg == HSYNC_FRONT_PORCH +
HSYNC_PULSE - 2)
r_next <= HS_BACK_PORCH;
end
HS_BACK_PORCH:begin
hsync_reg <= 1'b1;
if(counter_reg == HSYNC_FRONT_PORCH +
HSYNC_PULSE +
HSYNC_BACK_PORCH - 2) begin
r_next <= HS_DISPLAY;
counter_pixel_reg <= 'h0;
end
end
HS_DISPLAY:begin
hsync_reg <= 1'b1;
counter_pixel_reg <= counter_pixel_reg + 1;
if(counter_reg == HSYNC_FRONT_PORCH +
HSYNC_PULSE +
HSYNC_BACK_PORCH +
HSYNC_DISPLAY - 1) begin
r_next <= HS_FRONT_PORCH;
counter_reg <= 'h0;
end
end
endcase
end
assign o_Hsync = hsync_reg;
assign o_h_display = (counter_pixel_reg >= 1 && counter_pixel_reg <= HSYNC_DISPLAY) ? 1'b1 : 1'b0 ;
assign o_h_pixel = counter_pixel_reg - 1 ;
endmodule
i2s_receiver.v
+14 -1
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@@ -1,3 +1,10 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - i2s receiver
//
// Detailed module description:
// This I2S design uses the common 44.1 kHz
// sampling frequency.
// From Figure 2 in Section 4.1.1 of the CS5343
@@ -19,8 +26,14 @@
//
// Module is created from sample provided by
// Digilent
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module i2s_receicer #( parameter
sclk_ws_ratio = 64, // number of sclk periods per word select period
i2s_sender.v
+15 -1
View File
@@ -1,4 +1,11 @@
// This I2S Playback design uses the common 44.1 kHz
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - i2s sender
//
// Detailed module description:
// This I2S design uses the common 44.1 kHz
// sampling frequency.
// From Figure 2 in Section 4.1.1 of the CS5343
// Datasheet, it is appropriate to use an SCLK/LRCK
@@ -19,7 +26,14 @@
//
// Module is created from sample provided by
// Digilent
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module i2s_sender #( parameter
io_module.v
+17 -24
View File
@@ -20,15 +20,15 @@ module io_module #( parameter
input reset,
// // inputs to logic analyzer
// input ch0,
// input ch1,
// input ch2,
// input ch3,
// input ch4,
// input ch5,
// input ch6,
// input ch7,
// inputs to logic analyzer
input ch0,
input ch1,
input ch2,
input ch3,
input ch4,
input ch5,
input ch6,
input ch7,
output [7: 0] JXADC // output for logic analizer
@@ -69,22 +69,15 @@ i2s_receicer #(
// connecting signals to JXADC PMOD to monitor them with signal analyzer
JXADC_controler JXADC_controler(
.ch0(mclk),
.ch1(ad_sclk),
.ch2(ad_ws),
.ch3(sd_rx), // serial data in
.ch4(mclk),
.ch5(da_sclk),
.ch6(da_ws),
.ch7(sd_tx), // serial data out
.ch0(ch0),
.ch1(ch1),
.ch2(ch2),
.ch3(ch3), // serial data in
.ch4(ch4),
.ch5(ch5),
.ch6(ch6),
.ch7(ch7), // serial data out
.JXADC(JXADC) // output for logic analizer
);
// // debounce reset button
// debounce_switch debounce_switch_reset(
// .clk(mclk),
// .i_switch(btnC),
// .o_switch(reset_n)
// );
endmodule
matlab/fourier_aprox.m
-23
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@@ -1,23 +0,0 @@
dt = 0.01;
T = 1;
t = [0:dt:T]' ;
omega0 = 2 * pi /T;
N = length (t);
N2 = round (N/2);
x = ones(N, 1);
x (N2 + 1:N) = -1 * ones(N - N2, 1);
a(1) = 1/T * ( sum (x) * dt);
xfs = a(1) * ones( size(x));
for k = 1:10
ck = cos (k * omega0 * t); % cosine component
a(k + 1) = 2/T * ( sum (x.* ck) * dt);
sk = sin (k * omega0 * t); % sine component
b(k + 1) = 2/T * ( sum (x.* sk) * dt);
% Fourier series approximation
xfs = xfs + a(k + 1) * cos (k * omega0 * t) + b(k + 1) * sin (k * omega0 * t);
plot (t, x, '-' , t, xfs, ':' );
legend ( ' desired ' , ' approximated ' );
drawnow ;
pause (1);
end
matlab/gong.wav
BIN
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matlab/handel.wav
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matlab/myfft.m
-294
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@@ -1,294 +0,0 @@
%% FFT algoritm
clear; % clear all data from memmory
start_time = 0;
number_of_samples = 32;
end_time = number_of_samples - 1;
n = linspace(start_time, end_time , number_of_samples );
f1 = 2;
a1 = 0.2;
f2 = 2;
a2 = 00;
f3 = 1;
a3 = 00;
comp1 = a1 * cos( f1 *2*pi*n/number_of_samples);
comp2 = a2 * sin( f2 *2*pi*n/number_of_samples);
comp3 = a3 * sin( f3 *2*pi*n/number_of_samples);
data = comp1 + comp2 + comp3;
figure(1)
plot (n, comp1, '-');
hold on;
plot (n, comp2, '-');
plot (n, comp3, '-');
hold off;
figure(2)
plot (n, data);
figure(3)
X_matlab = fft(data, number_of_samples);
stem (n,abs(X_matlab))
%% My FFT
% W_N vector calculation
% W = zeros(1,number_of_samples); % complex
% Wr = zeros(1,number_of_samples); % real
% Wi = zeros(1,number_of_samples); % imag
% for i = 1 : number_of_samples
% W(i) = exp(-j * (i-1) * 2 * pi/ number_of_samples );
% Wr(i) = real(W(i));
% Wi(i) = imag(W(i));
% end
% reverse bit calulation
bits = length(dec2bin( number_of_samples - 1 ));
rev_bit_dec = zeros(1,number_of_samples);
for i=1:number_of_samples
bin_num = dec2bin(i-1 , bits);
rev_bit = [];
for k=bits:-1:1
rev_bit = [rev_bit , bin_num(k)];
end
rev_bit_dec(i) = bin2dec(rev_bit) + 1; % add 1 to match Matlab numbering
end
% First stage of FFT
stage = zeros(bits,number_of_samples);
for i=1:number_of_samples
stage(1,i) = data((i));
end
stage(2,1) = stage(1,1) + stage(1,2);
stage(2,2) = stage(1,1) - stage(1,2) ;
stage(2,3) = (stage(1,3) + stage(1,4)) * exp(-j * 0 * 2 * pi/ 4 );
stage(2,4) = (stage(1,3) - stage(1,4)) * exp(-j * 1 * 2 * pi/ 4 );
stage(2,5) = stage(1,5) + stage(1,6);
stage(2,6) = stage(1,5) - stage(1,6);
stage(2,7) = (stage(1,7) + stage(1,8)) * exp(-j * 0 * 2 * pi/ 4 );
stage(2,8) = (stage(1,7) - stage(1,8)) * exp(-j * 1 * 2 * pi/ 4 );
stage(2,9) = stage(1,9) + stage(1,10);
stage(2,10) = stage(1,9) - stage(1,10);
stage(2,11) = (stage(1,11) + stage(1,12)) * exp(-j * 0 * 2 * pi/ 4 );
stage(2,12) = (stage(1,11) - stage(1,12)) * exp(-j * 1 * 2 * pi/ 4 );
stage(2,13) = stage(1,13) + stage(1,14);
stage(2,14) = stage(1,13) - stage(1,14);
stage(2,15) = (stage(1,15) + stage(1,16)) * exp(-j * 0 * 2 * pi/ 4 );
stage(2,16) = (stage(1,15) - stage(1,16)) * exp(-j * 1 * 2 * pi/ 4 );
stage(2,17) = stage(1,17) + stage(1,18);
stage(2,18) = (stage(1,17) - stage(1,18)) * exp(-j * 1 * 2 * pi/ 4 );
stage(2,19) = stage(1,19) + stage(1,20);
stage(2,20) = (stage(1,19) - stage(1,20)) * exp(-j * 1 * 2 * pi/ 4 );
stage(2,21) = stage(1,21) + stage(1,22);
stage(2,22) = stage(1,21) - stage(1,22);
stage(2,23) = stage(1,23) + stage(1,24);
stage(2,24) = stage(1,23) - stage(1,24);
stage(2,25) = stage(1,25) + stage(1,26);
stage(2,26) = stage(1,25) - stage(1,26);
stage(2,27) = stage(1,27) + stage(1,28);
stage(2,28) = stage(1,27) - stage(1,28);
stage(2,29) = stage(1,29) + stage(1,30);
stage(2,30) = stage(1,29) - stage(1,30);
stage(2,31) = stage(1,31) + stage(1,32);
stage(2,32) = stage(1,31) - stage(1,32);
% stage,
% Second stage
stage(2,1) = stage(1,1) + stage(1,3);
stage(2,2) = stage(1,2) + stage(1,4);
stage(2,3) = stage(1,1) - stage(1,3);
stage(2,4) = stage(1,2) - stage(1,4);
stage(2,5) = (stage(1,5) + stage(1,7)) * exp(-j * 0 * 2 * pi/ 8 );
stage(2,6) = (stage(1,6) + stage(1,8)) * exp(-j * 1 * 2 * pi/ 8 );
stage(2,7) = (stage(1,5) - stage(1,7)) * exp(-j * 2 * 2 * pi/ 8 );
stage(2,8) = (stage(1,6) - stage(1,8)) * exp(-j * 3 * 2 * pi/ 8 );
stage(2,9) = stage(1,9) + stage(1,11);
stage(2,10) = stage(1,10) + stage(1,12);
stage(2,11) = stage(1,9) - stage(1,11);
stage(2,12) = stage(1,10) - stage(1,12);
stage(2,13) = (stage(1,13) + stage(1,15)) * exp(-j * 0 * 2 * pi/ 8 );
stage(2,14) = (stage(1,14) + stage(1,16)) * exp(-j * 1 * 2 * pi/ 8 );
stage(2,15) = (stage(1,13) - stage(1,15)) * exp(-j * 2 * 2 * pi/ 8 );
stage(2,16) = (stage(1,14) - stage(1,16)) * exp(-j * 3 * 2 * pi/ 8 );
stage(2,17) = stage(1,17) + 1 * stage(1,19);
stage(2,18) = stage(1,18) + 1 * stage(1,20);
stage(2,19) = stage(1,19) - W1(1) * stage(1,17);
stage(2,20) = stage(1,20) - W1(2) * stage(1,18);
stage(2,21) = stage(1,21) + 1 * stage(1,23);
stage(2,22) = stage(1,22) + 1 * stage(1,24);
stage(2,23) = stage(1,23) - W1(1) * stage(1,21);
stage(2,24) = stage(1,24) - W1(2) * stage(1,22);
stage(2,25) = stage(1,25) + 1 * stage(1,27);
stage(2,26) = stage(1,26) + 1 * stage(1,28);
stage(2,27) = stage(1,27) - W1(1) * stage(1,25);
stage(2,28) = stage(1,28) - W1(2) * stage(1,26);
stage(2,29) = stage(1,29) + 1 * stage(1,31);
stage(2,30) = stage(1,30) + 1 * stage(1,32);
stage(2,31) = stage(1,31) - W1(1) * stage(1,29);
stage(2,32) = stage(1,32) - W1(2) * stage(1,30);
% theard stage
stage(3,1) = stage(2,1) + stage(2,5);
stage(3,2) = stage(2,2) + stage(2,6);
stage(3,3) = stage(2,3) + stage(2,7);
stage(3,4) = stage(2,4) + stage(2,8);
stage(3,5) = stage(2,1) - stage(2,5);
stage(3,6) = stage(2,2) - stage(2,6);
stage(3,7) = stage(2,3) - stage(2,7);
stage(3,8) = stage(2,4) - stage(2,8);
stage(3,9) = (stage(2,9) + stage(2,13)) * exp(-j * 0 * 2 * pi/ 16 );
stage(3,10) = (stage(2,10) + stage(2,14)) * exp(-j * 1 * 2 * pi/ 16 );
stage(3,11) = (stage(2,11) + stage(2,15)) * exp(-j * 2 * 2 * pi/ 16 );
stage(3,12) = (stage(2,12) + stage(2,16)) * exp(-j * 3 * 2 * pi/ 16 );
stage(3,13) = (stage(2,9) - stage(2,13)) * exp(-j * 4 * 2 * pi/ 16 );
stage(3,14) = (stage(2,10) - stage(2,14)) * exp(-j * 5 * 2 * pi/ 16 );
stage(3,15) = (stage(2,11) - stage(2,15)) * exp(-j * 6 * 2 * pi/ 16 );
stage(3,16) = (stage(2,12) - stage(2,16)) * exp(-j * 7 * 2 * pi/ 16 );
stage(3,17) = stage(2,17) + W2(1) * stage(2,21);
stage(3,18) = stage(2,18) + W2(2) * stage(2,22);
stage(3,19) = stage(2,19) + W2(3) * stage(2,23);
stage(3,20) = stage(2,20) + W2(4) * stage(2,24);
stage(3,21) = stage(2,21) - W2(1) * stage(2,17);
stage(3,22) = stage(2,22) - W2(2) * stage(2,18);
stage(3,23) = stage(2,23) - W2(3) * stage(2,19);
stage(3,24) = stage(2,24) - W2(4) * stage(2,20);
stage(3,25) = stage(2,25) + W2(1) * stage(2,29);
stage(3,26) = stage(2,26) + W2(2) * stage(2,30);
stage(3,27) = stage(2,27) + W2(3) * stage(2,31);
stage(3,28) = stage(2,28) + W2(4) * stage(2,32);
stage(3,29) = stage(2,29) - W2(1) * stage(2,25);
stage(3,30) = stage(2,30) - W2(2) * stage(2,26);
stage(3,31) = stage(2,31) - W2(3) * stage(2,27);
stage(3,32) = stage(2,32) - W2(4) * stage(2,28);
% Fourt stage
%
stage(4,1) = stage(3,1) + stage(3,9);
stage(4,2) = stage(3,2) + stage(3,10);
stage(4,3) = stage(3,3) + stage(3,11);
stage(4,4) = stage(3,4) + stage(3,12);
stage(4,5) = stage(3,5) + stage(3,13);
stage(4,6) = stage(3,6) + stage(3,14);
stage(4,7) = stage(3,7) + stage(3,15);
stage(4,8) = stage(3,8) + stage(3,16);
stage(4,9) = stage(3,1) - stage(3,9);
stage(4,10) = stage(3,2) - stage(3,10);
stage(4,11) = stage(3,3) - stage(3,11);
stage(4,12) = stage(3,4) - stage(3,12);
stage(4,13) = stage(3,5) - stage(3,13);
stage(4,14) = stage(3,6) - stage(3,14);
stage(4,15) = stage(3,7) - stage(3,15);
stage(4,16) = stage(3,8) - stage(3,16);
stage(4,17) = stage(3,17) + W3(1) * stage(3,25);
stage(4,18) = stage(3,18) + W3(2) * stage(3,26);
stage(4,19) = stage(3,19) + W3(3) * stage(3,27);
stage(4,20) = stage(3,20) + W3(4) * stage(3,28);
stage(4,21) = stage(3,21) + W3(5) * stage(3,29);
stage(4,22) = stage(3,22) + W3(6) * stage(3,30);
stage(4,23) = stage(3,23) + W3(7) * stage(3,31);
stage(4,24) = stage(3,24) + W3(8) * stage(3,32);
stage(4,25) = stage(3,25) - W3(1) * stage(3,17);
stage(4,26) = stage(3,26) - W3(2) * stage(3,18);
stage(4,27) = stage(3,27) - W3(3) * stage(3,19);
stage(4,28) = stage(3,28) - W3(4) * stage(3,20);
stage(4,29) = stage(3,29) - W3(5) * stage(3,21);
stage(4,30) = stage(3,30) - W3(6) * stage(3,22);
stage(4,31) = stage(3,31) - W3(7) * stage(3,23);
stage(4,32) = stage(3,32) - W3(8) * stage(3,24);
% Fifth stage
W4 = zeros(1,32); % complex
for i = 1 : 32
W4(i) = exp(-j * (i-1) * 2 * pi/ 32 );
end
stage(5,1) = stage(4,1) + W4(1) * stage(4,17);
stage(5,2) = stage(4,2) + W4(2) * stage(4,18);
stage(5,3) = stage(4,3) + W4(3) * stage(4,19);
stage(5,4) = stage(4,4) + W4(4) * stage(4,20);
stage(5,5) = stage(4,5) + W4(5) * stage(4,21);
stage(5,6) = stage(4,6) + W4(6) * stage(4,22);
stage(5,7) = stage(4,7) + W4(7) * stage(4,23);
stage(5,8) = stage(4,8) + W4(8) * stage(4,24);
stage(5,9) = stage(4,9) + W4(9) * stage(4,25);
stage(5,10) = stage(4,10) + W4(10) * stage(4,26);
stage(5,11) = stage(4,11) + W4(11) * stage(4,27);
stage(5,12) = stage(4,12) + W4(12) * stage(4,28);
stage(5,13) = stage(4,13) + W4(13) * stage(4,29);
stage(5,14) = stage(4,14) + W4(14) * stage(4,30);
stage(5,15) = stage(4,15) + W4(15) * stage(4,31);
stage(5,16) = stage(4,16) + W4(16) * stage(4,32);
stage(5,17) = stage(4,17) - W4(1) * stage(4,1);
stage(5,18) = stage(4,18) - W4(2) * stage(4,2);
stage(5,19) = stage(4,19) - W4(3) * stage(4,3);
stage(5,20) = stage(4,20) - W4(4) * stage(4,4);
stage(5,21) = stage(4,21) - W4(5) * stage(4,5);
stage(5,22) = stage(4,22) - W4(6) * stage(4,6);
stage(5,23) = stage(4,23) - W4(7) * stage(4,7);
stage(5,24) = stage(4,24) - W4(8) * stage(4,8);
stage(5,25) = stage(4,25) - W4(9) * stage(4,9);
stage(5,26) = stage(4,26) - W4(10) * stage(4,10);
stage(5,27) = stage(4,27) - W4(11) * stage(4,11);
stage(5,28) = stage(4,28) - W4(12) * stage(4,12);
stage(5,29) = stage(4,29) - W4(13) * stage(4,13);
stage(5,30) = stage(4,30) - W4(14) * stage(4,14);
stage(5,31) = stage(4,31) - W4(15) * stage(4,15);
stage(5,32) = stage(4,32) - W4(16) * stage(4,16);
figure(4)
stem(n, abs( stage(bits,:) ) )
matlab/myfft2.m
-510
View File
@@ -1,510 +0,0 @@
%% FFT algoritm
clear; % clears all previus values from memory
clc; % clear command window
fs = 44100; % samplinf freq.
fftLength=512; % windowlength
% signal frequencies
max = 2048 - 1 ;
f1 = 430;
a1 = 0;
f2 = 8000;
a2 = 0;
f3 = 8000;
a3 = max/2;
% calculating signals
comp1 = a1 * sin(2*pi*f1*[0:1/fs:1]);
comp2 = a2 * sin(2*pi*f2*[0:1/fs:1]);
comp3 = a3 * sin(2*pi*f3*[0:1/fs:1]);
% calculatin vector values for step function
d1 = ones(1, 24);
d2 = 0.*ones(1, 1000 );
%data = [ d1 , d2]; % creates vector with step function
data = comp1 + comp2 + comp3; % creates vector from 3 sin functions
figure(1) % plots separete sin functions
plot ( comp1, '-');
hold on;
plot ( comp2, '-');
plot ( comp3, '-');
xlim([1 50])
title('Separete SIN functions')
ylabel('magnitude'), xlabel('time')
hold off;
figure(2) % plots signal for fft
plot ( data);
title('Signal for FFT analysis FFT')
ylabel('magnitude'), xlabel('time')
xlim([1 100])
figure(3) % plots resultinf fft from Matlab functions
ft =fft(data,fftLength);
%ftMag=abs(ft(1:fftLength/2));
ftMag=abs(ft);
plot (ftMag)
title('Linear Magnitude FFT')
ylabel('magnitude'), xlabel('kHz')
xt = xticks; % returns the current x-axis tick values as a vector
fstep = fs/fftLength; % tick of f axis in f domain
xtnew = round(xt*fstep/1000, 1) ; % calculate new tick in kHz
xticklabels(xtnew) % set new tick labels
figure(4) % plots resultinf fft(in dB) from Matlab functions
ft =fft(data,fftLength);
%ftMag=abs(ft(1:fftLength/2));
ftMag=abs(ft);
plot (20*log10(ftMag))
title('dB Magnitude')
ylabel('dB'), xlabel('kHz')
xt = xticks; % returns the current x-axis tick values as a vector
fstep = fs/fftLength; % tick of f axis in f domain
xtnew = round(xt*fstep/1000, 1) ; % calculate new tick in kHz
xticklabels(xtnew) % set new tick labels
%% Data preparation for FFT
% reverse bit calulation
bits = length(dec2bin( fftLength - 1 )); % how many bits in binary number
rev_bit_dec = zeros(1,fftLength); % create vektor size of fftlength
for i=1:fftLength
bin_num = dec2bin(i-1 , bits); % converting to binary number
rev_bit = []; % create empty vector
for k=bits:-1:1
rev_bit = [rev_bit , bin_num(k)];
end
rev_bit_dec(i) = bin2dec(rev_bit) + 1; % add 1 to match Matlab numbering
end
% creating array
real_n = zeros(bits+1,fftLength); % create empty array to store values in reverse bit order
imag_n = zeros(bits+1,fftLength);
stage = zeros(bits+1,fftLength);
%sfi_data = sfi(data,16,0);
for i=1:fftLength
real_n(1,i) = data(rev_bit_dec(i)+1);
stage(1,i) = data(rev_bit_dec(i)+1);
end
% % W_N vector calculation
% W = zeros(1,fftLength); % complex
% Wr = zeros(1,fftLength); % real
% Wi = zeros(1,fftLength); % imag
% for i = 1 : fftLength
% W(i) = exp(-j * (i-1) * 2 * pi/ fftLength );
% Wr(i) = sfi(real(W(i)),16,15);
% Wi(i) = sfi(imag(W(i)),16,15);
% end
%
% % W(30) = - W(30+256)
% % or
% % W(x) = - W(x + fftLength/2)
% new W_N vector calculation this time only half
W = zeros(1,fftLength/2); % complex
Wr = zeros(1,fftLength/2); % real
Wi = zeros(1,fftLength/2); % imag
for i = 1 : fftLength/2
W(i) = exp(-j * (i-1) * 2 * pi/ fftLength );
Wr(i) = real(W(i));%sfi(real(W(i)),16,15);
Wi(i) = imag(W(i));%sfi(imag(W(i)),16,15);
end
%% FFT FSM
%% First stage
for i = 1 : 2^1 : fftLength
% % % Even
% % stage(2,i) = stage(1,i) + stage(1,i+1);
% % % Odd
% % stage(2,i+1) = stage(1,i) - stage(1,i+1);
% Even
real_n(2,i) = real_n(1,i) + real_n(1,i+1);
% Odd
real_n(2,i+1) = real_n(1,i) - real_n(1,i+1);
end
%% Second stage
% % % Calculating W twiddling factor
% % for i = 1 : 2
% % Wn(i) = exp(-j * (i-1) * 2 * pi/ 4 );
% % end
% %
% % % calculate next stage values
% % for i = 1 : 2^2 : fftLength
% % % Even pair
% % stage(3,i+0) = stage(2,i+0) + Wn(1)*stage(2,i+2);
% % stage(3,i+1) = stage(2,i+1) + Wn(2)*stage(2,i+3);
% % % Odd par
% % stage(3,i+2) = stage(2,i+0) - Wn(1)*stage(2,i+2);
% % stage(3,i+3) = stage(2,i+1) - Wn(2)*stage(2,i+3);
% % end
% Multiply odd pairs with W twiddling factor
for i = 1 : 1 : fftLength
i_bin = dec2bin(i-1, bits); % calculates "i" in binary
if i_bin(bits - 1:bits) == '11' % Odd pair odd number(every fourth)
imag_n(2,i) = -real_n(2,i);
real_n(2,i) = 0;
% c= real_n(2,i) + j * imag_n(2,i),
end
end
% calculate next stage values
for i = 1 : 2^2 : fftLength
% Even pair
real_n(3,i+0) = real_n(2,i+0) + real_n(2,i+2);
real_n(3,i+1) = real_n(2,i+1) + real_n(2,i+3);
imag_n(3,i+0) = imag_n(2,i+0) + imag_n(2,i+2);
imag_n(3,i+1) = imag_n(2,i+1) + imag_n(2,i+3);
% Odd par
real_n(3,i+2) = real_n(2,i+0) - real_n(2,i+2);
real_n(3,i+3) = real_n(2,i+1) - real_n(2,i+3);
imag_n(3,i+2) = imag_n(2,i+0) - imag_n(2,i+2);
imag_n(3,i+3) = imag_n(2,i+1) - imag_n(2,i+3);
end
%% Therd stage
% % % Calculating W twiddling factor
% % for i = 1 : 4
% % Wn(i) = exp(-j * (i-1) * 2 * pi/ 8 );
% % end
% %
% % % calculate next stage values
% % for i = 1 : 2^3 : fftLength
% % for k = 0 : 3
% % % Even pair
% % stage(4,i+k) = stage(3,i+k) + Wn(k+1)*stage(3,i+k+4);
% % % Odd par
% % stage(4,i+k+4) = stage(3,i+k) - Wn(k+1)*stage(3,i+k+4);
% % end
% % end
% Multiply odd pairs with W twiddling factor
for i = 1 : 1 : fftLength
i_bin = dec2bin(i-1, bits); % calculates "i" in binary
if i_bin(bits - 2) == '1' %
if i_bin(bits - 1: bits) == '00'
% real_n(3,i) = real_n(3,i);
% imag_n(3,i) = imag_n(3,i);
end
if i_bin(bits - 1: bits) == '01'
real_x = real_n(3,i)*Wr(65) - imag_n(3,i)*Wi(65);
imag_x = real_n(3,i)*Wi(65) + Wr(65)*imag_n(3,i);
real_n(3,i) = real_x;
imag_n(3,i) = imag_x;
end
if i_bin(bits - 1: bits) == '10'
real_x = real_n(3,i)*Wr(129) - imag_n(3,i)*Wi(129);
imag_x = real_n(3,i)*Wi(129) + Wr(129)*imag_n(3,i);
real_n(3,i) = real_x;
imag_n(3,i) = imag_x;
end
if i_bin(bits - 1: bits) == '11'
real_x = real_n(3,i)*Wr(193) - imag_n(3,i)*Wi(193);
imag_x = real_n(3,i)*Wi(193) + Wr(193)*imag_n(3,i);
real_n(3,i) = real_x;
imag_n(3,i) = imag_x;
end
end
end
% calculate next stage values
for i = 1 : 2^3 : fftLength
for k = 0 : 3
% Even pair
real_n(4,i+k) = real_n(3,i+k) + real_n(3,i+k+4);
imag_n(4,i+k) = imag_n(3,i+k) + imag_n(3,i+k+4);
% Odd par
real_n(4,i+k+4) = real_n(3,i+k) - real_n(3,i+k+4);
imag_n(4,i+k+4) = imag_n(3,i+k) - imag_n(3,i+k+4);
end
end
%% 4th stage
% % % Calculating W twiddling factor
% % for i = 1 : 8
% % Wn(i) = exp(-j * (i-1) * 2 * pi/ 16 );
% % end
% %
% % % calculate next stage values
% % for i = 1 : 2^4 : fftLength
% % for k = 0 : 7
% % % Even pair
% % stage(5,i+k) = stage(4,i+k) + Wn(k+1)*stage(4,i+k+8);
% % % Odd par
% % stage(5,i+k+8) = stage(4,i+k) - Wn(k+1)*stage(4,i+k+8);
% % end
% % end
% Multiply odd pairs with W twiddling factor
for i = 1 : 1 : fftLength
i_bin = dec2bin(i-1, bits); % calculates "i" in binary
if i_bin(bits - 3) == '1' %
n = bin2dec(i_bin(bits - 2:bits)); % converting last 3 bits to decimal
real_x = real_n(4,i)*Wr(n*32+1) - imag_n(4,i)*Wi(n*32+1);
imag_x = real_n(4,i)*Wi(n*32+1) + imag_n(4,i)*Wr(n*32+1);
real_n(4,i) = real_x;
imag_n(4,i) = imag_x;
end
end
% calculate next stage values
for i = 1 : 2^4 : fftLength
for k = 0 : 7
%Even pair
real_n(5,i+k) = real_n(4,i+k) + real_n(4,i+k+8);
imag_n(5,i+k) = imag_n(4,i+k) + imag_n(4,i+k+8);
%Odd par
real_n(5,i+k+8) = real_n(4,i+k) - real_n(4,i+k+8);
imag_n(5,i+k+8) = imag_n(4,i+k) - imag_n(4,i+k+8);
end
end
%% 5th stage
% % % Calculating W twiddling factor
% % for i = 1 : 16
% % Wn(i) = exp(-j * (i-1) * 2 * pi/ 32 );
% % end
% %
% % % calculate next stage values
% % for i = 1 : 2^5 : fftLength
% % for k = 0 : 15
% % % Even pair
% % stage(6,i+k) = stage(5,i+k) + Wn(k+1)*stage(5,i+k+16);
% % % Odd par
% % stage(6,i+k+16) = stage(5,i+k) - Wn(k+1)*stage(5,i+k+16);
% % end
% % end
% Multiply odd pairs with W twiddling factor
for i = 1 : 1 : fftLength
i_bin = dec2bin(i-1, bits); % calculates "i" in binary
if i_bin(bits - 4) == '1' %
n = bin2dec(i_bin(bits - 3:bits)); % converting last 4 bits to decimal
real_x = real_n(5,i)*Wr(n*16+1) - imag_n(5,i)*Wi(n*16+1);
imag_x = real_n(5,i)*Wi(n*16+1) + imag_n(5,i)*Wr(n*16+1);
real_n(5,i) = real_x;
imag_n(5,i) = imag_x;
end
end
% calculate next stage values
for i = 1 : 2^5 : fftLength
for k = 0 : 15
% Even pair
real_n(6,i+k) = real_n(5,i+k) + real_n(5,i+k+16);
imag_n(6,i+k) = imag_n(5,i+k) + imag_n(5,i+k+16);
% Odd par
real_n(6,i+k+16)= real_n(5,i+k) - real_n(5,i+k+16);
imag_n(6,i+k+16)= imag_n(5,i+k) - imag_n(5,i+k+16);
end
end
%% 6th stage
% % % Calculating W twiddling factor
% % for i = 1 : 32
% % Wn(i) = exp(-j * (i-1) * 2 * pi/ 64 );
% % end
% %
% % % calculate next stage values
% % for i = 1 : 2^6 : fftLength
% % for k = 0 : 31
% % % Even pair
% % stage(7,i+k) = stage(6,i+k) + Wn(k+1)*stage(6,i+k+32);
% % % Odd par
% % stage(7,i+k+32) = stage(6,i+k) - Wn(k+1)*stage(6,i+k+32);
% % end
% % end
% Multiply odd pairs with W twiddling factor
for i = 1 : 1 : fftLength
i_bin = dec2bin(i-1, bits); % calculates "i" in binary
if i_bin(bits - 5) == '1' %
n = bin2dec(i_bin(bits - 4:bits)); % converting last 5 bits to decimal
real_x = real_n(6,i)*Wr(n*8+1) - imag_n(6,i)*Wi(n*8+1);
imag_x = real_n(6,i)*Wi(n*8+1) + imag_n(6,i)*Wr(n*8+1);
real_n(6,i) = real_x;
imag_n(6,i) = imag_x;
end
end
% calculate next stage values
for i = 1 : 2^6 : fftLength
for k = 0 : 31
% Even pair
real_n(7,i+k) = real_n(6,i+k) + real_n(6,i+k+32);
imag_n(7,i+k) = imag_n(6,i+k) + imag_n(6,i+k+32);
% Odd par
real_n(7,i+k+32)= real_n(6,i+k) - real_n(6,i+k+32);
imag_n(7,i+k+32)= imag_n(6,i+k) - imag_n(6,i+k+32);
end
end
%% 7th stage
% % % Calculating W twiddling factor
% % for i = 1 : 64
% % Wn(i) = exp(-j * (i-1) * 2 * pi/ 128 );
% % end
% %
% % % calculate next stage values
% % for i = 1 : 2^7 : fftLength
% % for k = 0 : 63
% % % Even pair
% % stage(8,i+k) = stage(7,i+k) + Wn(k+1)*stage(7,i+k+64);
% % % Odd par
% % stage(8,i+k+64) = stage(7,i+k) - Wn(k+1)*stage(7,i+k+64);
% % end
% % end
% Multiply odd pairs with W twiddling factor
for i = 1 : 1 : fftLength
i_bin = dec2bin(i-1, bits); % calculates "i" in binary
if i_bin(bits - 6) == '1' %
n = bin2dec(i_bin(bits - 5:bits)); % converting last 6 bits to decimal
real_x = real_n(7,i)*Wr(n*4+1) - imag_n(7,i)*Wi(n*4+1);
imag_x = real_n(7,i)*Wi(n*4+1) + imag_n(7,i)*Wr(n*4+1);
real_n(7,i) = real_x;
imag_n(7,i) = imag_x;
end
end
% calculate next stage values
for i = 1 : 2^7 : fftLength
for k = 0 : 63
% Even pair
real_n(8,i+k) = real_n(7,i+k) + real_n(7,i+k+64);
imag_n(8,i+k) = imag_n(7,i+k) + imag_n(7,i+k+64);
% Odd par
real_n(8,i+k+64)= real_n(7,i+k) - real_n(7,i+k+64);
imag_n(8,i+k+64)= imag_n(7,i+k) - imag_n(7,i+k+64);
end
end
%% 8th stage
% % % Calculating W twiddling factor
% % for i = 1 : 128
% % Wn(i) = exp(-j * (i-1) * 2 * pi/ 256 );
% % end
% %
% % % calculate next stage values
% % for i = 1 : 2^8 : fftLength
% % for k = 0 : 127
% % % Even pair
% % stage(9,i+k) = stage(8,i+k) + Wn(k+1)*stage(8,i+k+128);
% % % Odd par
% % stage(9,i+k+128) = stage(8,i+k) - Wn(k+1)*stage(8,i+k+128);
% % end
% % end
% Multiply odd pairs with W twiddling factor
for i = 1 : 1 : fftLength
i_bin = dec2bin(i-1, bits); % calculates "i" in binary
if i_bin(bits - 7) == '1' %
n = bin2dec(i_bin(bits - 6:bits)); % converting last 7 bits to decimal
real_x = real_n(8,i)*Wr(n*2+1) - imag_n(8,i)*Wi(n*2+1);
imag_x = real_n(8,i)*Wi(n*2+1) + imag_n(8,i)*Wr(n*2+1);
real_n(8,i) = real_x;
imag_n(8,i) = imag_x;
end
end
% calculate next stage values
for i = 1 : 2^8 : fftLength
for k = 0 : 127
% Even pair
real_n(9,i+k) = real_n(8,i+k) + real_n(8,i+k+128);
imag_n(9,i+k) = imag_n(8,i+k) + imag_n(8,i+k+128);
% Odd par
real_n(9,i+k+128)= real_n(8,i+k) - real_n(8,i+k+128);
imag_n(9,i+k+128)= imag_n(8,i+k) - imag_n(8,i+k+128);
end
end
%% 9th stage
% % % Calculating W twiddling factor
% % for i = 1 : 256
% % Wn(i) = exp(-j * (i-1) * 2 * pi/ 512 );
% % end
% %
% % % calculate next stage values
% % for i = 1 : 2^9 : fftLength
% % for k = 0 : 255
% % % Even pair
% % stage(10,i+k) = stage(9,i+k) + Wn(k+1)*stage(9,i+k+256);
% % % Odd par
% % stage(10,i+k+256) = stage(9,i+k) - Wn(k+1)*stage(9,i+k+256);
% % end
% % end
% Multiply odd pairs with W twiddling factor
for i = 1 : 1 : fftLength
i_bin = dec2bin(i-1, bits); % calculates "i" in binary
if i_bin(bits - 8) == '1' %
n = bin2dec(i_bin(bits - 7:bits)); % converting last 8 bits to decimal
real_x = real_n(8,i)*Wr(n*1+1) - imag_n(8,i)*Wi(n*1+1);
imag_x = real_n(8,i)*Wi(n*1+1) + imag_n(8,i)*Wr(n*1+1);
real_n(8,i) = real_x;
imag_n(8,i) = imag_x;
end
end
% calculate next stage values
i = 1;
for k = 0 : 255
% Even pair
real_n(10,i+k) = real_n(9,i+k) + real_n(9,i+k+255);
imag_n(10,i+k) = imag_n(9,i+k) + imag_n(9,i+k+255);
% Odd par
real_n(10,i+k+255)= real_n(9,i+k) - real_n(9,i+k+255);
imag_n(10,i+k+255)= imag_n(9,i+k) - imag_n(9,i+k+255);
end
%% Ploting out
% slowly plot result
figure(5)
for i = bits : bits
plot( abs( real_n(i, :) + j.*imag_n(i, :) ) );
% plot( abs( stage(i,:) ) );
% pause(1);
end
xt = xticks; % returns the current x-axis tick values as a vector
fstep = fs/fftLength; % tick of f axis in f domain
xtnew = round(xt*fstep)/1000 ; % calculate new tick in kHz
xticklabels(xtnew) % set new tick labels
matlab/myfft4_real_imag.asv
-144
View File
@@ -1,144 +0,0 @@
%% FFT algoritm
clear; % clears all previus values from memory
clc; % clear command window
fs = 44100; % samplinf freq.
fftLength=512; % windowlength
stage_num = log2(fftLength);
% signal frequencies
max = 2048 - 1 ;
f1 = 430;
a1 = 0;
f2 = 4300;
a2 = 0;
f3 = 8000;
a3 = max/2;
% calculating signals
comp1 = a1 * sin(2*pi*f1*[0:1/fs:1]);
comp2 = a2 * sin(2*pi*f2*[0:1/fs:1]);
comp3 = a3 * sin(2*pi*f3*[0:1/fs:1]);
Length = length(comp3);
% calculatin vector values for step function
d1 = ones(1, 24);
d2 = 0.*ones(1, 1000 );
%data = [ d1 , d2]; % creates vector with step function
data = comp1 + comp2 + comp3; % creates vector from 3 sin functions
%data = comp3;
% Grafika nobiides
bin_vals = [0 : fftLength-1];
N_2 = ceil(fftLength/2);
fax_kHz = (bin_vals-N_2)*fs/fftLength/1000;
freq3 = ceil(-(fftLength)/2:1:(fftLength)/2).*(fs/fftLength)/1000;
figure(1) % plots separete sin functions
hold off,
%plot ( comp1, '-');
hold on;
%plot ( comp2, '-');
plot ( comp3, '-'), grid minor,;
%xlim([1 50])
title('Separete SIN functions')
ylabel('magnitude'), xlabel('time')
hold off;
figure(2) % plots signal for fft
plot ( data), grid minor,;
xlim([1 50])
title('Signal for FFT analysis FFT')
ylabel('magnitude'), xlabel('time')
%xlim([1 100])
figure(3) % plots resultinf fft from Matlab functions
ft =fft(data,fftLength);
ft1 = fftshift(ft);
ftMag = abs(ft1);
plot (fax_kHz,ftMag), grid minor,
title('Linear Magnitude FFT')
ylabel('magnitude'), xlabel('kHz')
figure(4) % plots resultinf fft(in dB) from Matlab functions
ft = fft(data,fftLength+1);
ftMag = abs(ft(1:fftLength+1));
plot (freq3,20*log10(ftMag)), grid minor,
title('dB Magnitude')
ylabel('dB'), xlabel('kHz')
%% Data preparation for FFT
% reverse bit calulation
bits = length(dec2bin( fftLength - 1 )); % how many bits in binary number
rev_bit_dec = zeros(1,fftLength); % create vektor size of fftlength
stage = 1; %Do it here for stage #1
c = 0:fftLength-1;
c_bin = de2bi(c); % create binary table
rev_bit_dec = bi2de(fliplr(circshift(c_bin',stage-1)')); %Rotate binary table and convert to dec
% creating array
% create empty array to store values in reverse bit order
stage = zeros(bits+1,fftLength);
real_n = zeros(bits+1,fftLength);
imag_n = zeros(bits+1,fftLength);
Wn = zeros(1,fftLength/2); % complex
Wr = zeros(1,fftLength/2); % real
Wi = zeros(1,fftLength/2); % imag
%% New stages
for st = 0 : stage_num;
if st == 0
for tmp=1:fftLength;
stage(st+1,tmp) = data(rev_bit_dec(tmp)+1);
real_n(st+1,tmp) = data(rev_bit_dec(tmp)+1);
end
else st > 0;
for n = 1 : fftLength/2;
Wn(n) = exp(-j * (n-1) * 2 * pi/ 2^(st) );
Wr(n) = real(Wn(n));
Wi(n) = imag(Wn(n));
end
for i = 1 : 2^st : fftLength;
for k = 0 : 2^(st-1)-1;
% Even
stage(st+1,i+k) = stage(st,i+k) + Wn(k+1)*stage(st,i+k+2^(st-1));
real_n(st+1,i+k) = real_n(st,i+k) + Wn(k+1)*real_n(st,i+k+2^(st-1));
imag_n(st+1,i+k) = imag_n(st,i+k) + Wn(k+1)*imag_n(st,i+k+2^(st-1));
% Odd
stage(st+1,i+k+2^(st-1)) = stage(st,i+k) - Wn(k+1)*stage(st,i+k+2^(st-1));
real_n(st+1,i+k+2^(st-1)) = real_n(st,i+k) - Wn(k+1)*real_n(st,i+k+2^(st-1));
imag_n(st+1,i+k+2^(st-1)) = imag_n(st,i+k) - Wn(k+1)*imag_n(st,i+k+2^(st-1));
end
end
end
end
%% Ploting out
% slowly plot result
figure(5)
for i = 1 : bits + 1;
%plot( abs( real_n(i, :) + j.*imag_n(i, :) ) );
%plot( fax_kHz, abs( fftshift( real_n(i, :) + j.*imag_n(i,:) ) ) ), grid minor,;
plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ), grid minor,;
%pause(1);
end
title('Linear Magnitude FFT')
ylabel('magnitude'), xlabel('kHz')
figure(6)
for i = 1 : bits + 1;
%plot( abs( real_n(i, :) + j.*imag_n(i, :) ) );
plot( fax_kHz, abs( fftshift( real_n(i, :) + j.*imag_n(i,:) ) ) ), grid minor,;
%plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ), grid minor,;
%pause(1);
end
title('Linear Magnitude FFT, ploted from Real + Imag')
ylabel('magnitude'), xlabel('kHz')
matlab/myfft4_real_imag.m
+66 -93
View File
@@ -5,75 +5,51 @@
clear; % clears all previus values from memory
clc; % clear command window
fs = 44100; % samplinf freq.
fftLength=256; % windowlength
fftLength=2^9; % windowlength
stage_num = log2(fftLength);
Wn_word = 12; % signed fixed point lenght for Wn (fraction is word-2)
samp_word = 8; % word lenght of samped signal (fraction is word-2)
w_bits = 10; % signed fixed point integer bit lenght
f_bits = 10; % signed fixed point integer bit lenght for calculations
while 1 % Checking for correct "fftLength"-Wondow length value
if ~mod(stage_num,1)==0
error('"fftLength"-Wondow length value must be a numer: 2^x= : 2, 4, 8, 16, 32,...');
break
else
% continue working if value is correct
% signal frequencies
max = 2048 - 1 ;
f1 = 430;
a1 = 0;
f2 = 4300;
a2 = 0;
f3 = 8000;
a3 = max/2;
% calculating signals
comp1 = a1 * sin(2*pi*f1*[0:1/fs:1]);
comp2 = a2 * sin(2*pi*f2*[0:1/fs:1]);
comp3 = a3 * sin(2*pi*f3*[0:1/fs:1]);
Length = length(comp3);
data = comp1 + comp2 + comp3; % creates vector from 3 sin functions
%data = comp3;
% Plot shifting to center
bin_vals = [0 : fftLength-1];
N_2 = ceil(fftLength/2);
fax_kHz = (bin_vals-N_2)*fs/fftLength/1000;
freq3 = ceil(-(fftLength)/2:1:(fftLength)/2).*(fs/fftLength)/1000;
figure(1) % plots separete sin functions
hold off,
%plot ( comp1, '-');
hold on;
%plot ( comp2, '-');
plot (comp3, '-')
xlim([1 50]), grid minor,;
title('Separete SIN functions')
ylabel('magnitude'), xlabel('time')
hold off;
% reading input audio file
% audio samples are from matlab examples
% load handel.mat
% filename = 'handel.wav';
% load gong.mat;
filename = 'gong.wav';
% audiowrite(filename,y,Fs);
[y,fs] = audioread(filename);
data = sfi(y, samp_word, samp_word-2);
m = 7; % alow select section of signal for FFT
data_cut = data(fftLength*m+1:fftLength*m+fftLength);
%sound(data.double,fs);
figure(2) % plots signal for fft
plot (data), grid minor,;
xlim([1 50])
plot (data_cut), grid minor,
% xlim([fftLength*m+1 fftLength*m+fftLength])
title('Signal for FFT analysis FFT')
ylabel('magnitude'), xlabel('time')
bin_vals = [0 : fftLength-1];
figure(3) % plots resultinf fft from Matlab functions
ft = fft(data,fftLength);
ft = fft(data_cut.double,fftLength);
ft1 = fftshift(ft);
ftMag = abs(ft1);
plot (fax_kHz,ftMag), grid minor,
plot (bin_vals,ftMag), grid minor,
title('Linear Magnitude FFT')
ylabel('magnitude'), xlabel('kHz')
ylabel('magnitude'), xlabel(' ')
figure(4) % plots resultinf fft(in dB) from Matlab functions
ft = fft(data,fftLength);
ft1 = fftshift(ft);
ftMag = abs(ft1(1:fftLength));
plot (fax_kHz,20*log10(ftMag)), grid minor,
title('dB Magnitude')
ylabel('dB'), xlabel('kHz')
% figure(4) % plots resultinf fft(in dB) from Matlab functions
% ft = fft(data.double,fftLength);
% ft1 = fftshift(ft);
% ftMag = abs(ft1(1:fftLength));
% plot (bin_vals,20*log10(ftMag)), grid minor,
% title('dB Magnitude')
% ylabel('dB'), xlabel(' ')
%% Data preparation for FFT
@@ -97,67 +73,64 @@ imag_n_sfi = zeros(bits+1,fftLength);
%% Starting stages
for st = 0 : stage_num;
for st = 0 : stage_num
if st == 0
for tmp=1:fftLength;
stage(st+1,tmp) = data(rev_bit_dec(tmp)+1);
real_n(st+1,tmp) = data(rev_bit_dec(tmp)+1);
for tmp=1:fftLength
stage(st+1,tmp) = data_cut(rev_bit_dec(tmp)+1);
real_n(st+1,tmp) = data_cut(rev_bit_dec(tmp)+1);
real_n_sfi(st+1,tmp) = sfi(real_n(st+1,tmp),f_bits + w_bits ,f_bits);
end
else st > 0;
for n = 1 : fftLength/2;
for n = 1 : fftLength/2
Wn(n) = exp(-j * (n-1) * 2 * pi/ 2^(st) );
Wr(n) = real(Wn(n));
Wi(n) = imag(Wn(n));
% Wr(n) = real(Wn(n));
% Wi(n) = imag(Wn(n));
Wr(n) = sfi(real(Wn(n)),Wn_word,Wn_word-2);
Wi(n) = sfi(imag(Wn(n)),Wn_word,Wn_word-2);
end
for i = 1 : 2^st : fftLength;
for k = 0 : 2^(st-1)-1;
for i = 1 : 2^st : fftLength
for k = 0 : 2^(st-1)-1
% Even
stage(st+1,i+k) = stage(st,i+k) + Wn(k+1)*stage(st,i+k+2^(st-1));
real_n(st+1,i+k) = real_n(st,i+k) + Wr(k+1)*real_n(st,i+k+2^(st-1)) - Wi(k+1)*imag_n(st,i+k+2^(st-1));
imag_n(st+1,i+k) = imag_n(st,i+k) + Wi(k+1)*real_n(st,i+k+2^(st-1)) + + Wr(k+1)*imag_n(st,i+k+2^(st-1));
real_n(st+1,i+k) = real_n_sfi(st,i+k) + Wr(k+1)*real_n_sfi(st,i+k+2^(st-1)) - Wi(k+1)*imag_n_sfi(st,i+k+2^(st-1));
imag_n(st+1,i+k) = imag_n_sfi(st,i+k) + Wi(k+1)*real_n_sfi(st,i+k+2^(st-1)) + Wr(k+1)*imag_n_sfi(st,i+k+2^(st-1));
real_n_sfi(st+1,i+k) = sfi(real_n(st+1,i+k),f_bits + w_bits,f_bits);
imag_n_sfi(st+1,i+k) = sfi(imag_n(st+1,i+k),f_bits + w_bits,f_bits);
% Odd
stage(st+1,i+k+2^(st-1)) = stage(st,i+k) - Wn(k+1)*stage(st,i+k+2^(st-1));
real_n(st+1,i+k+2^(st-1)) = real_n(st,i+k) - Wr(k+1)*real_n(st,i+k+2^(st-1)) + Wi(k+1)*imag_n(st,i+k+2^(st-1));
imag_n(st+1,i+k+2^(st-1)) = imag_n(st,i+k) - Wi(k+1)*real_n(st,i+k+2^(st-1)) - Wr(k+1)*imag_n(st,i+k+2^(st-1));
real_n(st+1,i+k+2^(st-1)) = real_n_sfi(st,i+k) - Wr(k+1)*real_n_sfi(st,i+k+2^(st-1)) + Wi(k+1)*imag_n_sfi(st,i+k+2^(st-1));
imag_n(st+1,i+k+2^(st-1)) = imag_n_sfi(st,i+k) - Wi(k+1)*real_n_sfi(st,i+k+2^(st-1)) - Wr(k+1)*imag_n_sfi(st,i+k+2^(st-1));
real_n_sfi(st+1,i+k+2^(st-1)) = sfi(real_n(st+1,i+k+2^(st-1)),f_bits + w_bits,f_bits);
imag_n_sfi(st+1,i+k+2^(st-1)) = sfi(imag_n(st+1,i+k+2^(st-1)),f_bits + w_bits,f_bits);
end
end
end
end
%% Constructing signed fixed-point numeric objects
for n = 1 : fftLength/2;
Wr_sfi(n) = sfi(real(Wn(n)),16);
Wi_sfi(n) = sfi(imag(Wn(n)),16);
end
for n = 1 : fftLength;
for k = 1 : st + 1
real_n_sfi(k,n) = sfi(real_n(k,n),24);
imag_n_sfi(k,n) = sfi(imag_n(k,n),24);
end
end
%% Plotting out
% for slowly result plotting uncomment pause
figure(5)
for i = 1 : bits + 1;
%for i = 1 : bits + 1;
for i = bits+1 : bits + 1
%plot( fax_kHz, abs( fftshift( real_n(i, :) + j.*imag_n(i,:) ) ) ),
plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ),
grid minor, title('Linear Magnitude FFT'), ylabel('magnitude'), xlabel('kHz');
plot( bin_vals, abs( fftshift( stage(i,:) ) ) ),
grid minor, title('Linear Magnitude FFT'), ylabel('magnitude'), xlabel(' ');
%pause(1);
end
figure(6)
for i = 1 : bits + 1;
plot( fax_kHz, abs( fftshift( real_n(i, :) + j.*imag_n(i,:) ) ) ),
grid minor, title('Linear Magnitude FFT, ploted from Real + Imag'), ylabel('magnitude'), xlabel('kHz');
%for i = 1 : bits + 1;
for i = bits+1 : bits + 1
plot( bin_vals, abs( fftshift( real_n_sfi(i, :) + j.*imag_n_sfi(i,:) ) ) ),
grid minor, title('Linear Magnitude FFT, ploted from Real + Imag'), ylabel('magnitude'), xlabel(' ');
%plot( fax_kHz, abs( fftshift( stage(i,:) ) ) ), grid minor,;
%pause(1);
end
break
end
end
figure(7)
dif = abs( fftshift( stage(bits+1,:) ) ) - abs( fftshift( real_n_sfi(bits+1, :) + j.*imag_n_sfi(bits+1,:) ) ) ;
plot( bin_vals, dif )
grid minor, title('Difference in plots'), ylabel('diff magnitude'), xlabel(' ');
no_effect.v
-86
View File
@@ -1,86 +0,0 @@
module no_effect #( parameter
data_width = 16 // data width
)(
input clk,
input reset,
input signed [data_width-1: 0] i_data,
output signed [data_width-1: 0] o_data,
input i_read_done,
output o_read_enable,
output o_data_valid,
input i_data_ready
);
//-------------Internal Constants---------------------------
localparam [1:0] IDLE = 'd0,
OUTPUT = 'd1,
CLEAR = 'd3;
reg [1:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0;
reg r_read_enable = 0;
reg r_data_valid = 0;
assign o_read_enable = r_read_enable;
assign o_data_valid = r_data_valid;
assign o_data = r_data;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (~reset) begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always @(posedge clk ) begin
if (reset) begin
r_next <= IDLE;
r_read_enable <= 0; // redy to read data
r_data_valid <= 0;
end
else begin
case(r_state)
IDLE : begin
if (i_data_ready == 1) begin
r_next <= OUTPUT;
r_data <= i_data;
r_read_enable <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_enable <= 1; // redy to read data
r_data_valid <= 0;
end
end
OUTPUT : begin
if (i_read_done == 1) begin
r_next <= CLEAR;
r_data_valid <= 0;
r_read_enable <= 0;
end
else begin
r_next <= OUTPUT;
r_data_valid <= 1;
r_read_enable <= 0; // read disable
end
end
CLEAR : begin
r_next <= IDLE;
r_data_valid <= 0;
r_read_enable <= 1;
end
default: begin
r_next <= IDLE; // on error
end
endcase
end
end
endmodule
segment4x7.v
+146
View File
@@ -0,0 +1,146 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - 7 segmet display module
//
// Detailed module description:
// Outputs information on 7 segmet display
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module segment4x7(
input clk, // 10kHz clock
input [15:0] in, // input
output [6:0] seg, // individual segments of number
output [3:0] an, // anode to select character
output dp // dot on 7segment display
);
//-------------Internal Constants---------------------------
parameter SIZE = 2;
parameter [SIZE-1:0] ONE = 2'b00,
TWO = 2'b01,
THREE = 2'b10,
FOUR = 2'b11;
reg [SIZE-1:0] state=ONE, next=TWO;
reg [3:0] nibble = 'b0 ;
//---------State register sequential always block-----------
always @(posedge clk ) begin
state <= next;
end
//----Next state & outputs, combinational always block------
always@(state or in)begin
case(state)
ONE : begin
next <= TWO;
nibble <= in[3:0];
end
TWO : begin
next <= THREE;
nibble <= in[7:4];
end
THREE : begin
next <= FOUR;
nibble <= in[11:8];
end
FOUR : begin
next <= ONE;
nibble <= in[15:12];
end
endcase
end
assign seg[6] = ( nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hD ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[5] = ( nibble == 4'h0 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[4] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hD ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[3] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hD ||
nibble == 4'hE ) ? 1'b0 : 1'b1;
assign seg[2] = ( nibble == 4'h0 ||
nibble == 4'h1 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hD ) ? 1'b0 : 1'b1;
assign seg[1] = ( nibble == 4'h0 ||
nibble == 4'h1 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hD ) ? 1'b0 : 1'b1;
assign seg[0] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hC ||
nibble == 4'hE ||
nibble == 4'hF) ? 1'b0 : 1'b1;
assign dp = 1'b1; //dot not using
assign an[0] = (state==ONE) ? 1'b0 : 1'b1;
assign an[1] = (state==TWO) ? 1'b0 : 1'b1;
assign an[2] = (state==THREE) ? 1'b0 : 1'b1;
assign an[3] = (state==FOUR) ? 1'b0 : 1'b1;
endmodule
sync_fifo.v
-119
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@@ -1,119 +0,0 @@
// Fifo code source:
// https://vlsicoding.blogspot.com/2013/11/verilog-code-for-synchronous-fifo.html
//
module sync_fifo #( parameter
//---------------parametre declaration
data_width = 4,
address_width = 4,
ram_depth = 16 // must be 2^n
)(
//--------------input output port declaration
output reg signed [data_width-1:0] data_out,
output full,
output empty,
output [address_width-1:0] data_fill,
input signed [data_width-1:0] data_in,
input w_clk, // write clock
input r_clk, // read clock
input reset,
input wr_en,
input rd_en);
//--------------internal register declaration
reg [address_width-1:0] wr_pointer = 0;
reg [address_width-1:0] rd_pointer = 0;
// reg [address_width :0] status_count = 0;
wire signed [data_width-1:0] data_ram ;
// reg addition = 0;
// reg subtractor = 0;
// always@(posedge addition )
// begin
// if (addition ^ subtractor) // if XOR
// begin
// if (status_count != 0)
// status_count = status_count + 1;
// end
// addition = 0; // reset addition
// end
// always@(posedge subtractor)
// begin
// if (addition ^ subtractor) // if XOR
// begin
// if (status_count != 0)
// status_count = status_count - 1;
// end
// subtractor = 0; // reset subtractor
// end
//--------------wr_pointer pointing to write address
always @ (posedge w_clk,posedge reset)
begin
if(reset)
wr_pointer = 0;
else if(wr_en)
wr_pointer = wr_pointer+1;
//addition = 1;
end
//-------------rd_pointer points to read address
always @ (posedge r_clk,posedge reset)
begin
if(reset)
rd_pointer = 0;
else if(rd_en)
rd_pointer = rd_pointer + 1;
//subtractor = 1;
end
//-------------read from FIFO
always @ (posedge r_clk,posedge reset)
begin
if(reset)
data_out=0;
else if(rd_en)
data_out=data_ram;
end
// //--------------Status pointer for full and empty checking
// always @ (posedge w_clk,posedge r_clk,posedge reset)
// begin
// if(reset)
// status_count = 0;
// else if(wr_en && !rd_en && (status_count != ram_depth))
// status_count = status_count + 1;
// else if(rd_en && !wr_en && (status_count != 0))
// status_count = status_count - 1;
// end // always @ (posedge clk,posedge reset)
// assign full = (status_count == (ram_depth));
// assign empty = (status_count == 0);
// assign data_fill = status_count; // how full are FIFO
assign full = (wr_pointer - rd_pointer == ram_depth) ? 1'b1 : 1'b0 ;
assign empty = (wr_pointer - rd_pointer == 0) ? 1'b1 : 1'b0 ;
assign data_fill = wr_pointer - rd_pointer ; // how full are FIFO
rams_tdp_rf_rf #(
.DEPTH(ram_depth),
.ADDR_WIDTH(address_width),
.DATA_WIDTH(data_width)
) memory1 (
.addra(wr_pointer),
.addrb(rd_pointer),
.dia(data_in),
.dib(),
.doa(),
.dob(data_ram),
.wea(wr_en),
.web(1'b0),
.ena(1'b1),
.enb(rd_en),
.clka(w_clk),
.clkb(r_clk)
);
endmodule // sync_fifo
top.v
+82 -81
View File
@@ -1,8 +1,19 @@
// TOP module
//
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Top module
//
// Detailed module description:
//
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module top #( parameter
sclk_ws_ratio = 64, // number of sclk periods per word select period
mclk_sclk_ratio = 4, // number of mclk periods per sclk period
@@ -12,8 +23,18 @@ module top #( parameter
input clk,
input btnC,
output [15:0] led,
// input [1:0] sw, // swiches on board to control effects
input [15:0] sw, // swiches on board to control effects
// 7 segment display
output [6:0] seg,
output dp,
output [3:0] an,
//VGA inputs outputs
output [3:0] vgaRed,
output [3:0] vgaBlue,
output [3:0] vgaGreen,
output Hsync,
output Vsync,
input [15:0] sw, // swiches on board to control effects
output da_mclk,
output ad_mclk,
output da_sclk,
@@ -26,7 +47,7 @@ module top #( parameter
);
//assign output from effect controler to leds
assign led = l_data_tx[d_width-1: d_width-16];
assign led = sw;
assign da_mclk = master_clk; //output master clock to ADC
assign ad_mclk = master_clk; //output master clock to DAC
@@ -35,14 +56,14 @@ assign ad_mclk = master_clk; //output master clock to DAC
//------internal wires and registers--------
wire master_clk; // 11.29 MHz master clock
wire clk_50MHz; // 50 MHz clock
wire clk_25MHz; // 25 MHz clock
wire clk_50MHz; //
wire w_reset, w_reset1, w_reset2;
wire w_reset;
wire w_internal_reset;
wire signed [d_width-1: 0] r_data_tx;
wire signed [d_width-1: 0] l_data_tx;
// wire signed [d_width-1: 0] r_data_tx;
// wire signed [d_width-1: 0] l_data_tx;
wire signed [d_width-1: 0] r_data_rx;
wire signed [d_width-1: 0] l_data_rx;
@@ -71,38 +92,26 @@ wire [d_width-1: 0] w_data_from_eff_sw1;
clk_wiz_0 m_clk(
.clk_in1(clk),
.clk_out1(master_clk), // 11.29 MHz master clock for I2S
.clk_out2(clk_50MHz), // 25MHz main clock
.clk_out2(clk_50MHz), // 50MHz main clock
.clk_out3(clk_25MHz), // 25MHz main clock
.locked(w_internal_reset),
.reset(btnC)
);
// Flip-flops for reset
// Flip-flop for reset
d_flipflop_sync_rst D_flipflop1 (
.D(1'b0),
.Q(w_reset1),
.clk(master_clk),
.reset(~w_internal_reset));
d_flipflop_sync_rst D_flipflop2 (
.D(w_reset1),
.Q(w_reset2),
.clk(master_clk),
.reset(~w_internal_reset));
d_flipflop_sync_rst D_flipflop3 (
.D(w_reset2),
.Q(w_reset),
.clk(master_clk),
.reset(~w_internal_reset));
io_module #(
.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
.d_width(d_width) //data width
) io_module (
//.reset_n(reset_n), //asynchronous active high reset
.reset(reset_n), //asynchronous active high reset
.mclk(master_clk), //master clock
.da_sclk(da_sclk), //serial clock (or bit clock)
.da_ws(da_lrck), //word select (or left-right clock)
@@ -110,8 +119,8 @@ io_module #(
.ad_ws(ad_lrck), //word select (or left-right clock)
.sd_tx(da_sdin), //serial data transmit
.sd_rx(ad_sdout), //serial data receive
.l_data_tx(l_data_tx), //left channel data to transmit
.r_data_tx(r_data_tx), //right channel data to transmit
.l_data_tx(l_data_rx), //left channel data to transmit
.r_data_tx(r_data_rx), //right channel data to transmit
.reset(w_reset), //reset
@@ -119,65 +128,57 @@ io_module #(
.r_data_rx(r_data_rx), //right channel data received
// // inputs to logic analyzer
// .ch0(),
// .ch1(),
// .ch2(),
// .ch3(),
// .ch4(),
// .ch5(),
// .ch6(),
// .ch7(),
// inputs to logic analyzer
.ch0(Hsync),
.ch1(Vsync),
.ch2(),
.ch3(),
.ch4(),
.ch5(),
.ch6(),
.ch7(),
.JXADC(JXADC) // output for logic analizer
);
segment4x7 segment4x7(
.clk(clk10k), // 10kHz clock
.in(sw), // input
.seg(seg), // individual segments of number
.an(an), // anode to select character
.dp(dp) // dot on 7segment display
);
//Effect controler controls effects and perfoms multiplexing and data marging
effect_controler #(
.d_width(d_width), // data width
.memory_d_width(memory_d_width)
) effect_controler (
.reset(w_reset), // asynchronous active high reset
.mclk(master_clk),
.sw(sw[1:0]),
.clk(clk_50MHz),
.i_l_data(l_data_rx), // left channel data received
.i_r_data(r_data_rx), // right channel data received
// .i_l_data({sw[15:2], 10'b0 }), // left channel data received
// .i_r_data({sw[15:2], 10'b0 }), // right channel data received
.o_l_data(l_data_tx), // left channel data to transmit
.o_r_data(r_data_tx), // right channel data to transmit
.o_read_done(w_read_done_eff), // read done from effects controler
.o_read_ready(w_read_ready_eff), // ready read from reefects module
.o_data_to_eff(w_data_to_eff), // Data output to effects module
.o_data_valid(w_dv_to_eff), // data valid to read (FIFO not empty). data valid signal to effect module
.i_read_enable(w_rd_en_from_eff), // read enable from Effect module
.i_dv_from_eff(w_dv_from_eff), // data valid write (FIFO not full). data valid signal from effect module
.i_data_from_eff_sw0(w_data_from_eff_sw0), // Data input from effects module
.i_data_from_eff_sw1(w_data_from_eff_sw1) // Data input from effects module
);
//Effect module contains all individual effects
effect_module #(
.d_width(memory_d_width) // data width
) effect_module (
.clk(clk_50MHz),
.reset(w_reset),
.sw(sw[1:0]), // effect control swiches
.i_treshhold(sw[15:2]),
.i_data_ready(w_dv_to_eff), // data ready to read
.i_read_done(w_read_done_eff), // read done from effects controler
.i_data(w_data_to_eff), // data input form effect controler
.o_read_enable(w_rd_en_from_eff), // enable data reading
.o_data_valid(w_dv_from_eff),
.o_data_sw0(w_data_from_eff_sw0),
.o_data_sw1(w_data_from_eff_sw1)
clock_divider #(.WIDTH(11))
clock_divider7seg (
.clk_in(clk_50MHz),
.clk_out(clk10k)
);
vga_module #(
// .ADDR_WIDTH(ADDR_WIDTH),
// .DATA_WIDTH(DATA_WIDTH),
// .DEPTH(DEPTH),
// .HSYNC_CLKS(HSYNC_CLKS),
// .HSYNC_DISPLAY(HSYNC_DISPLAY),
// .HSYNC_PULSE(HSYNC_PULSE),
// .HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH),
// .HSYNC_BACK_PORCH(HSYNC_BACK_PORCH),
// .VSYNC_LINES(VSYNC_LINES) ,
// .VSYNC_DISPLAY(VSYNC_DISPLAY) ,
// .VSYNC_PULSE(VSYNC_PULSE) ,
// .VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
// .VSYNC_BACK_PORCH(VSYNC_BACK_PORCH)
) vga_module1 (
.clk(clk_25MHz),
.o_vgaRed(vgaRed),
.o_vgaBlue(vgaBlue),
.o_vgaGreen(vgaGreen),
.o_Hsync(Hsync),
.o_Vsync(Vsync),
.o_display(),
.o_addr_rd(),
.i_data_rd()
);
endmodule
top_tb.v
+14 -1
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@@ -1,6 +1,19 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Test Bench for top module
//
// Detailed module description:
// This file is Test Bench for top module
//
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
vertical_counter.v
+89
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@@ -0,0 +1,89 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - vertical counter
//
// Detailed module description:
//
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module vertical_counter #(
parameter
VSYNC_LINES = 521,
VSYNC_DISPLAY = 480,
VSYNC_PULSE = 2,
VSYNC_FRONT_PORCH = 10,
VSYNC_BACK_PORCH = 29
)(
//input clk,
input i_Hsync,
output o_Vsync,
output o_v_display,
output [8:0] o_v_line
);
//----------Internal registers, constants and wariables-----
reg vsync_reg = 1'b1;
reg [9:0] counter_reg = 'h0;
reg [8:0] counter_line_reg = 'h0;
reg [2:0] r_state=VS_FRONT_PORCH, r_next=VS_FRONT_PORCH;
localparam [2:0] VS_FRONT_PORCH = 'h0,
VS_PULSE = 'h1,
VS_BACK_PORCH = 'h2,
VS_DISPLAY = 'h3;
//---------state register sequential always block-----------
always @(posedge i_Hsync ) begin
r_state <= r_next;
end
//----next state & outputs, combinational always block------
always@(posedge i_Hsync) begin
counter_reg <= counter_reg + 1;
case (r_state)
VS_FRONT_PORCH: begin
vsync_reg <= 1'b1;
if(counter_reg == VSYNC_FRONT_PORCH - 2)
r_next <= VS_PULSE;
end
VS_PULSE:begin
vsync_reg <= 1'b0;
if(counter_reg == VSYNC_FRONT_PORCH +
VSYNC_PULSE - 2)
r_next <= VS_BACK_PORCH;
end
VS_BACK_PORCH:begin
vsync_reg <= 1'b1;
if(counter_reg == VSYNC_FRONT_PORCH +
VSYNC_PULSE +
VSYNC_BACK_PORCH - 2) begin
r_next <= VS_DISPLAY;
counter_line_reg <= 'h0;
end
end
VS_DISPLAY:begin
vsync_reg <= 1'b1;
counter_line_reg <= counter_line_reg + 1;
if(counter_reg == VSYNC_FRONT_PORCH +
VSYNC_PULSE +
VSYNC_BACK_PORCH +
VSYNC_DISPLAY - 1) begin
r_next <= VS_FRONT_PORCH;
counter_reg <= 'h0;
end
end
endcase
end
assign o_Vsync = vsync_reg;
assign o_v_display = (counter_line_reg >= 1 && counter_line_reg <= VSYNC_DISPLAY) ? 1'b1 : 1'b0 ;
assign o_v_line = counter_line_reg - 1 ;
endmodule
vga_module.v
+92
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@@ -0,0 +1,92 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - VGA module
//
// Detailed module description:
//
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module vga_module#(
parameter
ADDR_WIDTH = 17,
DATA_WIDTH = 12,
DEPTH = 76_800, // 307_200,//
HSYNC_CLKS = 800,
HSYNC_DISPLAY = 640,
HSYNC_PULSE = 96,
HSYNC_FRONT_PORCH = 16,
HSYNC_BACK_PORCH = 48,
VSYNC_LINES = 521,
VSYNC_DISPLAY = 480,
VSYNC_PULSE = 2,
VSYNC_FRONT_PORCH = 10,
VSYNC_BACK_PORCH = 29
)(
input clk,
output [3:0] o_vgaRed,
output [3:0] o_vgaBlue,
output [3:0] o_vgaGreen,
output o_Hsync,
output o_Vsync,
output o_display,
output [ADDR_WIDTH-1:0] o_addr_rd,
input [DATA_WIDTH-1:0] i_data_rd
);
//-------Internal registers and wires--------------
wire w_v_display;
wire w_h_display;
wire [9:0] pixel;
wire [8:0] line;
//-------sub modules-------------------------------
horizontal_counter #(
.HSYNC_CLKS(HSYNC_CLKS) ,
.HSYNC_DISPLAY(HSYNC_DISPLAY) ,
.HSYNC_PULSE(HSYNC_PULSE) ,
.HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH) ,
.HSYNC_BACK_PORCH(HSYNC_BACK_PORCH)
) horizontal_counter1 (
.clk(clk),
.o_Hsync(o_Hsync),
.o_h_display(w_h_display),
.o_h_pixel(pixel)
);
vertical_counter #(
.VSYNC_LINES(VSYNC_LINES) ,
.VSYNC_DISPLAY(VSYNC_DISPLAY) ,
.VSYNC_PULSE(VSYNC_PULSE) ,
.VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
.VSYNC_BACK_PORCH(VSYNC_BACK_PORCH)
) vertical_counter1 (
//.clk(clk),
.i_Hsync(o_Hsync),
.o_Vsync(o_Vsync),
.o_v_display(w_v_display),
.o_v_line(line)
);
assign o_display = (w_v_display && w_h_display) ;
assign o_vgaRed = o_display ? i_data_rd[11:8] : 4'h0;
assign o_vgaBlue = o_display ? i_data_rd[3:0] : 4'h0;
assign o_vgaGreen = o_display ? i_data_rd[7:4] : 4'h0;
/*
assign o_addr_rd = (((line*HSYNC_DISPLAY) + pixel + 1) == HSYNC_DISPLAY * VSYNC_DISPLAY ) ?
'h0 : ((line[8:1]) * HSYNC_DISPLAY/2 ) + pixel[9:1] + 1 ; // get next pixel
*/
assign o_addr_rd =
((line[8:1]) * 'd320 ) + pixel[9:1];// + 1;
endmodule