update fifo files

fifo.v

@@ -13,15 +13,15 @@ module fifo_mem(
     input           rd, 
     input   [7:0]   data_in
 );  
-    wire    [4:0]   wptr,
+    wire    [4:0]   w_wptr,
-                    rptr;  
+                    w_rptr;  
-    wire            fifo_we,
+    wire            w_fifo_we,
-                    fifo_rd;   
+                    w_fifo_rd;   
 
 // sub modules
     write_pointer write_pointer(
-        .wptr(wptr),
+        .wptr(w_wptr),
-        .fifo_we(fifo_we),
+        .fifo_we(w_fifo_we),
         .wr(wr),
         .fifo_full(fifo_full),
         .clk(clk),
@@ -29,8 +29,8 @@ module fifo_mem(
     );  
 
     read_pointer read_pointer(
-        .rptr(rptr),
+        .rptr(w_rptr),
-        .fifo_rd(fifo_rd),
+        .fifo_rd(w_fifo_rd),
         .rd(rd),
         .fifo_empty(fifo_empty),
         .clk(clk),
@@ -38,10 +38,10 @@ module fifo_mem(
     );  
 
     memory_array memory_array(
-        .data_out(data_out), 
+        .data_out(w_data_out), 
-        .data_in(data_in), 
+        .data_in(w_data_in), 
         .clk(clk),
-        .fifo_we(fifo_we), 
+        .fifo_we(w_fifo_we), 
         .wptr(wptr),
         .rptr(rptr)
     );  
@@ -50,15 +50,15 @@ module fifo_mem(
     status_signal status_signal(
         .fifo_full(fifo_full), 
         .fifo_empty(fifo_empty), 
-        .fifo_threshold(), 
+        .fifo_threshold(fifo_threshold), 
         .fifo_overflow(fifo_overflow), 
         .fifo_underflow(fifo_underflow), 
         .wr(wr), 
         .rd(rd), 
-        .fifo_we(fifo_we), 
+        .fifo_we(w_fifo_we), 
-        .fifo_rd(fifo_rd), 
+        .fifo_rd(w_fifo_rd), 
-        .wptr(wptr),
+        .wptr(w_wptr),
-        .rptr(rptr),
+        .rptr(w_rptr),
         .clk(clk),
         .rst_n(rst_n)
     );  

memory_array.v

@@ -7,14 +7,14 @@ module memory_array(
     input   [4:0]   rptr
 );  
      
-    reg     [7:0]   data_out2   [15:0];  
+    reg     [7:0]   data_array   [15:0];  
     wire    [7:0]   data_out;
 
     always @(posedge clk)  
     begin  
         if(fifo_we)   
-            data_out2[wptr[3:0]] <=data_in ;  
+            data_array[wptr[3:0]] <= data_in ;  
     end  
 
-    assign data_out = data_out2[rptr[3:0]];  
+    assign data_out = data_array[rptr[3:0]];  
 endmodule  

read_pointer.v

@@ -8,7 +8,7 @@ module read_pointer(
    
     reg     [4:0]   rptr;  
     
-    assign fifo_rd = (~fifo_empty)& rd;  
+    assign fifo_rd = (~fifo_empty) & rd;  
 
     always @(posedge clk or negedge rst_n)  
     begin  

status_signal.v

@@ -25,14 +25,14 @@ module status_signal(
             fifo_underflow;  
 
     assign fbit_comp = wptr[4] ^ rptr[4];  
-    assign pointer_equal = (wptr[3:0] - rptr[3:0]) ? 0:1;  
+    assign pointer_equal = (wptr[3:0] - rptr[3:0]) ? 0 : 1;  
     assign pointer_result = wptr[4:0] - rptr[4:0];  
     assign overflow_set = fifo_full & wr;  
-    assign underflow_set = fifo_empty&rd; 
+    assign underflow_set = fifo_empty & rd; 
 
     always @(*)  
     begin  
-        fifo_full =fbit_comp & pointer_equal;  
+        fifo_full = fbit_comp & pointer_equal;  
         fifo_empty = (~fbit_comp) & pointer_equal;  
         fifo_threshold = (pointer_result[4]||pointer_result[3]) ? 1:0;  
     end