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update fifo files

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This commit is contained in:
Imants Pulkstenis
2019-11-21 21:02:10 +02:00
parent 681d20fbf4
commit acef4ab3f2
4 changed files with 23 additions and 23 deletions
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fifo.v
+16 -16
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@@ -13,15 +13,15 @@ module fifo_mem(
input rd, input rd,
input [7:0] data_in input [7:0] data_in
); );
wire [4:0] wptr, wire [4:0] w_wptr,
rptr; w_rptr;
wire fifo_we, wire w_fifo_we,
fifo_rd; w_fifo_rd;
// sub modules // sub modules
write_pointer write_pointer( write_pointer write_pointer(
.wptr(wptr), .wptr(w_wptr),
.fifo_we(fifo_we), .fifo_we(w_fifo_we),
.wr(wr), .wr(wr),
.fifo_full(fifo_full), .fifo_full(fifo_full),
.clk(clk), .clk(clk),
@@ -29,8 +29,8 @@ module fifo_mem(
); );
read_pointer read_pointer( read_pointer read_pointer(
.rptr(rptr), .rptr(w_rptr),
.fifo_rd(fifo_rd), .fifo_rd(w_fifo_rd),
.rd(rd), .rd(rd),
.fifo_empty(fifo_empty), .fifo_empty(fifo_empty),
.clk(clk), .clk(clk),
@@ -38,10 +38,10 @@ module fifo_mem(
); );
memory_array memory_array( memory_array memory_array(
.data_out(data_out), .data_out(w_data_out),
.data_in(data_in), .data_in(w_data_in),
.clk(clk), .clk(clk),
.fifo_we(fifo_we), .fifo_we(w_fifo_we),
.wptr(wptr), .wptr(wptr),
.rptr(rptr) .rptr(rptr)
); );
@@ -50,15 +50,15 @@ module fifo_mem(
status_signal status_signal( status_signal status_signal(
.fifo_full(fifo_full), .fifo_full(fifo_full),
.fifo_empty(fifo_empty), .fifo_empty(fifo_empty),
.fifo_threshold(), .fifo_threshold(fifo_threshold),
.fifo_overflow(fifo_overflow), .fifo_overflow(fifo_overflow),
.fifo_underflow(fifo_underflow), .fifo_underflow(fifo_underflow),
.wr(wr), .wr(wr),
.rd(rd), .rd(rd),
.fifo_we(fifo_we), .fifo_we(w_fifo_we),
.fifo_rd(fifo_rd), .fifo_rd(w_fifo_rd),
.wptr(wptr), .wptr(w_wptr),
.rptr(rptr), .rptr(w_rptr),
.clk(clk), .clk(clk),
.rst_n(rst_n) .rst_n(rst_n)
); );
memory_array.v
+3 -3
View File
@@ -7,14 +7,14 @@ module memory_array(
input [4:0] rptr input [4:0] rptr
); );
reg [7:0] data_out2 [15:0]; reg [7:0] data_array [15:0];
wire [7:0] data_out; wire [7:0] data_out;
always @(posedge clk) always @(posedge clk)
begin begin
if(fifo_we) if(fifo_we)
data_out2[wptr[3:0]] <=data_in ; data_array[wptr[3:0]] <= data_in ;
end end
assign data_out = data_out2[rptr[3:0]]; assign data_out = data_array[rptr[3:0]];
endmodule endmodule