update fifo files

2019-11-21 21:02:10 +02:00
parent 681d20fbf4
commit acef4ab3f2
4 changed files with 23 additions and 23 deletions
@@ -7,14 +7,14 @@ module memory_array(
    input   [4:0]   rptr
 );  
     
-    reg     [7:0]   data_out2   [15:0];  
+    reg     [7:0]   data_array   [15:0];  
    wire    [7:0]   data_out;

    always @(posedge clk)  
    begin  
        if(fifo_we)   
-            data_out2[wptr[3:0]] <=data_in ;  
+            data_array[wptr[3:0]] <= data_in ;  
    end  

-    assign data_out = data_out2[rptr[3:0]];  
+    assign data_out = data_array[rptr[3:0]];  
 endmodule