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Imants Pulkstenis
2020-04-04 00:16:44 +03:00
parent b132a68ca2
commit ab92a0c8a8
26 changed files with 373 additions and 1094 deletions
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.gitignore
-2
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@@ -1,2 +0,0 @@
*.asv
matlab/sample_code_.m
Basys3_Master.xdc
+25 -25
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@@ -83,33 +83,33 @@ set_property PACKAGE_PIN L1 [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##7 segment display
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
#7 segment display
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
#set_property PACKAGE_PIN V7 [get_ports dp]
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property PACKAGE_PIN V7 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports dp]
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
##Buttons
JXADC_controler.v
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@@ -1,5 +1,21 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - JXADC PMOD connector output
//
// Detailed module description:
// This module outputs signals to JXADC PMOD
// where logic analyzer are conected.
// Port is connected to logic analizer
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module JXADC_controler (
input ch0,
README.md
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@@ -2,25 +2,10 @@
![GitHub commit activity](https://img.shields.io/github/commit-activity/m/clockfix/audio_effects_FPGA?style=plastic)
![GitHub last commit](https://img.shields.io/github/last-commit/clockfix/audio_effects_FPGA?style=plastic)
![GitHub contributors](https://img.shields.io/github/contributors/clockfix/audio_effects_FPGA?style=plastic)
# Audio effects on FPGA
# Audio FFT on FPGA
Audio effect synthesizer on FPGA
Audio FFT on FPGA
Audio hardware
![PMOD_I2S2](https://euborw.bl.files.1drv.com/y4mwscr7u3Q0WJKuOjfrLSFswmMhJFcQz_qvUDQmWPsWANUPPx3s-RrdHahplWN4MPxWtFJAZCzZokzS9oG3hJRHTa8-hztUF-5ix6DoEZ3FbW79HuWuWykaC6-vPQCz_jN-qtZzENmEM_CL7x6Fu-V3fVBwSbUUZ1B4FpyTJbHc2y09jmmIoznP9JKdHkloQC22fRvzkGEwn-uEL7m5GIYtg/pmod_i2s2.jpg) ![PMOD_I2S2_package](https://jhuenw.bl.files.1drv.com/y4mh-JRwzfInJGsB7npvB02QFP4E8O0fYseJrh7mCKZPhDtrRKAkyIU4vrSgIPZ57SPrRugP-CoS5pu-_W9fq1E2gV9SOYeyPc2In_a5uqQzCtwXbUYRvOQnHEt-zomphOLXn2Uw7RpaKbKLNvgQfF-pJNqbiX5LAaW5zODYNF66IESQ3uHqDSOCEtjt620oITZFzO71EyDkpSPB3bvZ61J6Q/pmod_i2s2_package.png)
i2s timing diagram from PulseView
![i2s timing diagram](https://jxuqnw.ch.files.1drv.com/y4m-dZeGZ7098LnxNfhcXYLc_boX5bUNKolrZoOikvJ15bhmx83OEfjXsL0DOx4bJQwo9Nj8JhPdbH3-p2_NsPtkQLQMjqqvHQD1aoTLU4iCGlzmuDkeRaJ4hOWEjlSxfPTpLuJmFxd3Co8m7PUNAHw-lSomMgNqrO4Sw_8E4K-vfiS2ijUOfIdlW4VUDLv0Dku1zcMel3jQGcMSIH0GiQyRA/i2s-loopback.png?psid=1)
Top module
![Top module_sh](https://sqtelw.ch.files.1drv.com/y4mxBDwlvgiYYZpsOjIUey0ctL7StvY-ymQdAxhs5_GToLB8sdDlbh9qd3IBUiguuYbraYpqDg2BVUclm8n7UIdIcLIz0468d-e_VIgsLgY13Z839dn2THBu_PKbq3MLZOmwJNjH0Jz8qq0SNr2UjZkyJjSmdmESf44Qv5DrNMVEhvl6jLvw0FxN23E7dme2MloArlCMLJ9PznU9qzNhD2RLw/top-audio-effects.png?psid=1)
Edited effect control module - now it has input and output FIFO memory
![efect_controler](https://pgow6w.ch.files.1drv.com/y4mG--fP9LI78p-SQYukYLlqkbHOkXCmfO6cLVgHcND0Z5G7J7-75dlO2Yva33k0KdAt6DBWdQDT_TH_6L_pjNxXHaczVTaUecui2-qpfOD4EW0GP8TtewGPuC7wsESNzd0Nsl4QSDfLzFV8uZZWeq2_VTadlnqPmQRSfs9115fiK8yLqdl17fzZZ4Q0LuhbOlbFV0aOpUqC0zBi6_FxK_xtw/efect_controler.png?psid=1)
IO module
![io_module](https://b6w9pw.ch.files.1drv.com/y4mgPXnMZOMUJWVUBhbHNP217wE84t29_bt9uDZ7lbozZTPFiq3Ncan_uSvk7YjRzmkIPma5t_dcwxAvLgd8ZV5n1GBIzJ5cCEiS1gCR0y7y4x5brYBBRXjJh5VXI0ITpQRCvlggTSzNZE4b7Ux8hvzoxa586RGty8d-a1eblClQE3GD4QAiPMV0CrT-ROt7axdN_ArKMn0HKHCYomtW3Gu4A/io_module.png?psid=4)
Effects module with one clipping effect
![io_module](https://py4mqq.ch.files.1drv.com/y4m3dgfUf1rxceMtUYiJ-Y9GBDS-E2vBBSFrZIh3-UEhRQifIn5Lq2OAAWUWKqsSTMDNNwTtkgEVy9ThtV3UNbjI1OdDDeFvC1tHPhXdbbpdPpasInNJgWDzTLhCE88uy48NYx_IRecy4zoXUrYg9_SaEWggmjloEwWd4KuSFBtSyopP0pHQ07nnUMuo4OyEhdZOfptzF-PS-J2ufYQSEVheg/effect_module.png?psid=1)
blockram.v
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// Code from:
// Vivado Design Suite
// User Guide
// Synthesis
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Dual-Port Block RAM
//
// Detailed module description:
// Code from: Vivado Design Suite User Guide Synthesis
// UG901 (v2018.3) December 19, 2018
//
// Dual-Port Block RAM with Two Write Ports
// File: blobkram.v
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module rams_tdp_rf_rf #( parameter
DEPTH = 16,
clipping.v
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@@ -1,107 +0,0 @@
module clipping_effect #( parameter
data_width = 16 // data width
)(
input clk,
input reset,
input signed [data_width-1: 0] i_data,
output signed [data_width-1: 0] o_data,
input signed [data_width-1: 0] i_treshhold,
input i_read_done,
output o_read_enable,
output o_data_valid,
input i_data_ready
);
//-------------Internal Constants---------------------------
localparam [1:0] IDLE = 'd0,
CLIP = 'd1,
OUTPUT = 'd2,
CLEAR = 'd3;
reg [1:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0;
reg [data_width-1: 0] r_treshhold_p = 'b0;
reg [data_width-1: 0] r_treshhold_n = 'b0;
reg r_read_enable = 0;
reg r_data_valid = 0;
assign o_read_enable = r_read_enable;
assign o_data_valid = r_data_valid;
assign o_data = r_data;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (~reset) begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always @(posedge clk ) begin
if (reset) begin
r_next <= IDLE;
r_read_enable <= 0; // redy to read data
r_data_valid <= 0;
end
else begin
case(r_state)
IDLE : begin
if (i_data_ready == 1) begin
r_next <= CLIP;
r_data <= i_data;
r_treshhold_p <= i_treshhold;
r_treshhold_n <= (~i_treshhold) + 1; // two compliment
r_read_enable <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_enable <= 1; // redy to read data
r_data_valid <= 0;
end
end
CLIP : begin
case (r_data[data_width-1])
0 : begin // positive number
if (r_data > r_treshhold_p) begin
r_data <= r_treshhold_p; end
end
1 : begin // negative number
if (r_data < r_treshhold_n) begin
r_data <= r_treshhold_n; end
end
endcase
r_next <= OUTPUT;
r_data_valid <= 0;
r_read_enable <= 0; // read disable
end
OUTPUT : begin
if (i_read_done == 1) begin
r_next <= CLEAR;
r_data_valid <= 0;
r_read_enable <= 0;
end
else begin
r_next <= OUTPUT;
r_data_valid <= 1;
r_read_enable <= 0; // read disable
end
end
CLEAR : begin
r_next <= IDLE;
r_data_valid <= 0;
r_read_enable <= 1;
end
default: begin
r_next <= IDLE; // on error
end
endcase
end
end
endmodule
clipping_tb.v
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@@ -1,85 +0,0 @@
// This file is Test Bench for clipping module
//
//
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
//sub modules
`include "clipping.v"
module clipping_tb#( parameter
data_width = 16 // data width
)();
reg clk = 1'b0;
reg signed [data_width-1 : 0] i_data = 'b0;
reg i_read_done = 0;
reg i_data_ready = 0;
// 50% duty cycle clock
always #0.5 clk <= ~clk;
clipping_effect #(
.data_width(data_width) // data width
) UUT (
.clk(clk),
.reset(1'b0),
.i_treshhold( 16'haff ),
.i_data(i_data),
.i_read_done(i_read_done), // read done from effects controler
.i_data_ready(i_data_ready),
.o_data(),
.o_read_enable(),
.o_data_valid()
);
initial begin
#030;
i_data = 'haaa;
#005;
i_data_ready = 1;
#005;
i_data = 'h0fa;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
#005;
i_data = -16'd3000;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
#005;
i_data = 852;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
end
initial begin
#030_000;
$display("*");
$display(" ");
$display("Use this command to open timing diagram:");
$display("gtkwave -f wave.vcd");
$display("----------------------------------------------");
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
end
endmodule
clock_divider_param.v → clock_divider.v
+15 -2
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/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - clock divider
//
// Detailed module description:
// This module devide FPGA input clock
// by DIVIDER. Result is 50% duty cicle
// pulses.
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module clock_divider #(
parameter DIVIDER =2,
parameter WIDTH =2
parameter WIDTH =2,
parameter DIVIDER =(2**WIDTH)
) (
input clk_in,
output clk_out);
clock_divider_param_tb.v
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@@ -1,40 +0,0 @@
// `timescale [time unit] / [time precision]
`timescale 10 ps / 1 ps
`include "clock_divider_param.v"
module clock_divider_param_tb ();
reg clk = 1'b0;
wire enable;
always #1 clk <= ~clk;
initial
begin
#100;
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
clock_divider #(
.DIVIDER(2),
.WIDTH(2)
) test_unit1 (
.clk(clk),
.enable(enable)
);
endmodule
clock_enable_param.v
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@@ -1,31 +0,0 @@
// This module devide FPGA input clock
// by DIVIDER.
//
//
module clock_enable_param #(
parameter WAIT =1,
parameter WIDTH =1
) (
input clk,
output enable);
reg state=1'b0;
reg [WIDTH-1:0] counter = 1'b0 ;
always@(posedge clk)begin
if(counter == 0)begin
if (state == 1) begin
state <= 0;
counter <= WAIT - 1;
end
else begin
state <= 1;
counter <= 0;
end
end
else counter <= counter -1;
end
assign enable = state;
endmodule
clock_enable_tb.v
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@@ -1,61 +0,0 @@
`include "clock_enable_param.v"
module clock_enable_tb();
reg clk = 1'b0;
wire enable0;
wire enable1;
wire enable2;
wire enable3;
always #1 clk <= ~clk;
initial
begin
#100;
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
clock_enable_param test_unit0(
.clk(clk),
.enable(enable0)
);
clock_enable_param #(
.WAIT(2),
.WIDTH(4)
) test_unit1(
.clk(clk),
.enable(enable1)
);
clock_enable_param #(
.WAIT(3),
.WIDTH(8)
)test_unit2(
.clk(clk),
.enable(enable2)
);
clock_enable_param #(
.WAIT(9),
.WIDTH(8)
)test_unit3(
.clk(clk),
.enable(enable3)
);
endmodule
d_flip-flop.v
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@@ -1,3 +1,18 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Flip-Flop
//
// Detailed module description:
// Simple Flip-Flop
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module d_flipflop_sync_rst(
input D,
output reg Q,
debounce_switch.v
+17 -1
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@@ -1,4 +1,20 @@
module debounce_switch(
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Debounce switch
//
// Detailed module description:
// This is Debounce switch module.
// It toggles output only when input is in
// HIGH or LOW state atleast for 10ms
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////module debounce_switch(
input clk,
input i_switch,
output o_switch);
debounce_switch_tb.v
+14 -1
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@@ -1,6 +1,19 @@
// This file is Test Bench for top_vga_mem module
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Test Bench for debounce switch
//
// Detailed module description:
// This file is Test Bench for debounce switch module
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
effect_controler.v
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@@ -1,108 +0,0 @@
module effect_controler #( parameter
d_width = 24, // data width
address_width = 4, //
ram_depth = 16, //
memory_d_width = 16 //
)(
input mclk, // io_module clock
input clk, // main clock
input reset,
input signed [d_width-1: 0] i_l_data,
input signed [d_width-1: 0] i_r_data, // not used
output signed [d_width-1: 0] o_l_data,
output signed [d_width-1: 0] o_r_data,
output o_read_done, // read done from effects module
output o_read_ready, // ready read from effects module
input [1:0] sw, // effect control swiches
output signed [memory_d_width-1: 0] o_data_to_eff, // Data output to effects module
output o_data_valid, // data valid to read (FIFO not empty). data valid signal to effect module
input i_read_enable, // enable read from input fifo
input signed [memory_d_width-1: 0] i_data_from_eff_sw0, // Data output to effects module
input signed [memory_d_width-1: 0] i_data_from_eff_sw1, // Data output to effects module
input i_dv_from_eff // data valid to read (FIFO not empty). data valid signal to effect module
);
wire signed [memory_d_width-1: 0] w_o_data; //output data to io_module
//wire signed [memory_d_width-1: 0] w_o_data_eff; //output data to effects module
wire w_empty_in, w_full_in;
wire w_empty_out, w_full_out;
wire [memory_d_width-1:0] w_data_to_fifo; // wire connets mixer to output fifo
wire [address_width-1:0] w_data_fill_input; // shows how full are in FIFO memmory for intput
wire [address_width-1:0] w_data_fill_output; // shows how full are in FIFO memmory for output
wire w_data_valid_to_fifo; // data valid to write output FIFO from mixer
assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler
assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left
assign o_data_valid = ~w_empty_in;
// Input FIFO
sync_fifo #(
.ram_depth(ram_depth), // ram memory depth
.address_width(address_width), // ram memory address width
.data_width(memory_d_width) // memory data width
) fifo_input (
.data_out(o_data_to_eff),
.full(w_full_in),
.empty(w_empty_in),
.data_fill(w_data_fill_input),
.data_in(i_l_data[ d_width-1 : d_width - memory_d_width ]),
.w_clk(mclk),
.r_clk(clk),
.reset(reset),
.wr_en( w_full_in ? 1'b0 : 1'b1 ), // checking is FIFO full
.rd_en( w_empty_in ? 1'b0 : i_read_enable ) // checking is FIFO empty
);
// Output FIFO
sync_fifo #(
.ram_depth(ram_depth), // ram memory depth
.address_width(address_width), // ram memory address width
.data_width(memory_d_width) // memory data width
) fifo_output (
.data_out(w_o_data),
.full(w_full_out),
.empty(w_empty_out),
.data_fill(w_data_fill),
.data_in(w_data_to_fifo),
.w_clk(clk),
.r_clk(mclk),
.reset(reset),
.wr_en( w_data_valid_to_fifo ), // checking of FIFO full are performing mixer module
.rd_en( w_empty_out ? 1'b0 : 1'b1 ) // checking is FIFO empty
);
// Effect mixer, performs audio data merging
effect_mixer #(
.data_width(memory_d_width) // memory data width
) effect_mixer (
.sw(sw),
.clk(clk),
.reset(reset),
.i_fifo_full(w_full_out),
.o_read_done(o_read_done), // read from effect module done
.o_read_ready(o_read_ready), // ready to read from effect module
.o_data(w_data_to_fifo), // data to output FIFO memory
.o_data_valid(w_data_valid_to_fifo),
.i_dv_from_eff(i_dv_from_eff),
.i_data_from_eff_sw0(i_data_from_eff_sw0), // Data output to effects module
.i_data_from_eff_sw1(i_data_from_eff_sw1)
);
endmodule
effect_mixer.v
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@@ -1,130 +0,0 @@
module effect_mixer #( parameter
data_width = 16 // data width
)(
input clk,
input [1:0] sw,
input reset,
input i_fifo_full,
output signed [data_width-1: 0] o_data,
output o_read_done, // read from effect module done
output o_read_ready, // ready to read from effect module
output o_data_valid, // data valit to write in FIFO memory
input i_dv_from_eff,
input signed [data_width-1: 0] i_data_from_eff_sw0, // Data output to effects module
input signed [data_width-1: 0] i_data_from_eff_sw1
);
//-------------Internal Constants---------------------------
localparam [2:0] IDLE = 'd0,
ADD = 'd1,
NORM = 'd2,
OUTPUT = 'd3;
reg [2:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data_sw0 = 'b0;
reg signed [data_width-1: 0] r_data_sw1 = 'b0;
reg signed [data_width: 0] r_data_add = 'b0;
reg signed [data_width-1: 0] r_data_norm = 'b0;
reg r_read_done = 0;
reg r_read_ready = 0;
reg r_data_valid = 0;
assign o_read_done = r_read_done;
assign o_data_valid = r_data_valid;
assign o_data = r_data_norm;
assign o_read_ready = r_read_ready;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (reset == 1) begin
// clear state
r_state <= IDLE;
r_next <= IDLE;
end
else begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always @(posedge clk ) begin
case(r_state)
IDLE : begin
if (i_dv_from_eff == 1) begin
r_next <= ADD;
r_data_sw0 <= i_data_from_eff_sw0;
r_data_sw1 <= i_data_from_eff_sw1;
r_data_norm <= 'b0;
r_read_done <= 1;
r_read_ready <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_ready <= 1; // redy to read data
r_data_valid <= 0;
end
end
ADD : begin
case ( sw )
0 : begin // off all sound
r_data_add <= 0;
end
1 : begin // no effect only
r_data_add <= r_data_sw0;
end
2 : begin // clipping effect only
r_data_add <= r_data_sw1;
end
3 : begin // no effect and clipping effect
r_data_add <= r_data_sw0 + r_data_sw1;
end
endcase
r_next <= NORM;
r_read_done <= 0;
end
NORM : begin
case ( sw )
0 : begin // off all sound
r_data_norm <= 0;
end
1 : begin // no effect only
r_data_norm <= r_data_add[data_width-1: 0];
end
2 : begin // clipping effect only
r_data_norm <= r_data_add[data_width-1: 0];
end
3 : begin // no effect and clipping effect
r_data_norm <= r_data_add[data_width : 1] ; // Shift Right
end
endcase
r_next <= OUTPUT;
end
OUTPUT : begin
if ((i_fifo_full == 1) & (i_dv_from_eff == 1)) begin // wait for FIFO memory and data valid in effect module
r_next <= OUTPUT;
r_read_done <= 0;
r_read_ready <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_ready <= 0; // redy to read data
r_data_valid <= 1; // data valid to write in FIFO
end
end
default: r_next <= IDLE; // on error
endcase
end
endmodule
effect_module.v
-73
View File
@@ -1,73 +0,0 @@
module effect_module #( parameter
d_width = 16 // data width
)(
input clk,
input reset,
input [1:0] sw, // effect control switches
input [13:0] i_treshhold, // treshhold from switches
input i_data_ready, // data ready to read
input signed [d_width-1: 0] i_data, // data input form effect controler
input i_read_done, // read done from effects controler
output o_data_valid,
output o_read_enable,
// SW0 no effect
output signed [d_width-1: 0] o_data_sw0, // data output form effect controler
// SW1 clipping effect
output signed [d_width-1: 0] o_data_sw1 // data output form effect controler
);
// Wires for cliping effect
wire signed [d_width-1: 0] w_data_sw0;
wire w_read_enable_sw0;
wire w_data_valid_sw0;
wire signed [d_width-1: 0] w_data_sw1;
wire w_read_enable_sw1;
wire w_data_valid_sw1;
// asynchronous logic ---------------------------------------
assign o_data_sw0 = w_data_sw0;
assign o_data_sw1 = w_data_sw1;
assign o_read_enable = w_read_enable_sw0 & w_read_enable_sw1;
assign o_data_valid = w_data_valid_sw0 & w_data_valid_sw1;
// Individual effect modules -----------------------------
// no effect SW0
no_effect #(
.data_width(d_width) // data width
) no_effect (
.clk(clk),
.reset(reset),
.i_data(i_data),
.i_read_done(i_read_done), // read done from effects controler
.i_data_ready(i_data_ready),
.o_data(w_data_sw0),
.o_read_enable(w_read_enable_sw0),
.o_data_valid(w_data_valid_sw0)
);
// clipping effect SW1
clipping_effect #(
.data_width(d_width) // data width
) clipping_effect (
.clk(clk),
.reset(reset),
.i_treshhold( {2'b00, i_treshhold } ),
.i_data(i_data),
.i_read_done(i_read_done), // read done from effects controler
.i_data_ready(i_data_ready),
.o_data(w_data_sw1),
.o_read_enable(w_read_enable_sw1),
.o_data_valid(w_data_valid_sw1)
);
endmodule
effects_tb.v
-95
View File
@@ -1,95 +0,0 @@
// This file is Test Bench for clipping module
//
//
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
//sub modules
`include "clipping.v"
`include "no_effect.v"
//top module
`include "effect_module.v"
module effect_tb#( parameter
data_width = 16 // data width
)();
reg clk = 1'b0;
reg signed [data_width-1 : 0] i_data = 'b0;
reg i_read_done = 0;
reg i_data_ready = 0;
reg [1 : 0] sw = 2'b01;
// 50% duty cycle clock
always #0.5 clk <= ~clk;
//Effect module contains all individual effects
effect_module #(
.d_width(data_width) // data width
) effect_module (
.clk(clk),
.reset(1'b0),
.sw(sw), // effect control swiches
.i_treshhold(14'h0ff),
.i_data_ready(i_data_ready), // data ready to read
.i_read_done(i_read_done), // read done from effects controler
.i_data(i_data), // data input form effect controler
.o_read_enable(), // enable data reading
.o_data_valid(),
.o_data_sw0(),
.o_data_sw1()
);
initial begin
#030;
i_data = 'haaa;
#005;
i_data_ready = 1;
#005;
i_data = 'h0fa;
i_data_ready = 0;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
#005;
i_data = -16'd3000;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
#005;
i_data = 852;
#002;
i_read_done = 1;
#001;
i_read_done = 0;
end
initial begin
#030_000;
$display("*");
$display(" ");
$display("Use this command to open timing diagram:");
$display("gtkwave -f wave.vcd");
$display("----------------------------------------------");
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
end
endmodule
i2s_receiver.v
+14 -1
View File
@@ -1,3 +1,10 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - i2s receiver
//
// Detailed module description:
// This I2S design uses the common 44.1 kHz
// sampling frequency.
// From Figure 2 in Section 4.1.1 of the CS5343
@@ -20,7 +27,13 @@
// Module is created from sample provided by
// Digilent
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module i2s_receicer #( parameter
sclk_ws_ratio = 64, // number of sclk periods per word select period
i2s_sender.v
+15 -1
View File
@@ -1,4 +1,11 @@
// This I2S Playback design uses the common 44.1 kHz
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - i2s sender
//
// Detailed module description:
// This I2S design uses the common 44.1 kHz
// sampling frequency.
// From Figure 2 in Section 4.1.1 of the CS5343
// Datasheet, it is appropriate to use an SCLK/LRCK
@@ -20,6 +27,13 @@
// Module is created from sample provided by
// Digilent
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module i2s_sender #( parameter
io_module.v
+17 -24
View File
@@ -20,15 +20,15 @@ module io_module #( parameter
input reset,
// // inputs to logic analyzer
// input ch0,
// input ch1,
// input ch2,
// input ch3,
// input ch4,
// input ch5,
// input ch6,
// input ch7,
// inputs to logic analyzer
input ch0,
input ch1,
input ch2,
input ch3,
input ch4,
input ch5,
input ch6,
input ch7,
output [7: 0] JXADC // output for logic analizer
@@ -69,22 +69,15 @@ i2s_receicer #(
// connecting signals to JXADC PMOD to monitor them with signal analyzer
JXADC_controler JXADC_controler(
.ch0(mclk),
.ch1(ad_sclk),
.ch2(ad_ws),
.ch3(sd_rx), // serial data in
.ch4(mclk),
.ch5(da_sclk),
.ch6(da_ws),
.ch7(sd_tx), // serial data out
.ch0(ch0),
.ch1(ch1),
.ch2(ch2),
.ch3(ch3), // serial data in
.ch4(ch4),
.ch5(ch5),
.ch6(ch6),
.ch7(ch7), // serial data out
.JXADC(JXADC) // output for logic analizer
);
// // debounce reset button
// debounce_switch debounce_switch_reset(
// .clk(mclk),
// .i_switch(btnC),
// .o_switch(reset_n)
// );
endmodule
no_effect.v
-86
View File
@@ -1,86 +0,0 @@
module no_effect #( parameter
data_width = 16 // data width
)(
input clk,
input reset,
input signed [data_width-1: 0] i_data,
output signed [data_width-1: 0] o_data,
input i_read_done,
output o_read_enable,
output o_data_valid,
input i_data_ready
);
//-------------Internal Constants---------------------------
localparam [1:0] IDLE = 'd0,
OUTPUT = 'd1,
CLEAR = 'd3;
reg [1:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0;
reg r_read_enable = 0;
reg r_data_valid = 0;
assign o_read_enable = r_read_enable;
assign o_data_valid = r_data_valid;
assign o_data = r_data;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (~reset) begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always @(posedge clk ) begin
if (reset) begin
r_next <= IDLE;
r_read_enable <= 0; // redy to read data
r_data_valid <= 0;
end
else begin
case(r_state)
IDLE : begin
if (i_data_ready == 1) begin
r_next <= OUTPUT;
r_data <= i_data;
r_read_enable <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_enable <= 1; // redy to read data
r_data_valid <= 0;
end
end
OUTPUT : begin
if (i_read_done == 1) begin
r_next <= CLEAR;
r_data_valid <= 0;
r_read_enable <= 0;
end
else begin
r_next <= OUTPUT;
r_data_valid <= 1;
r_read_enable <= 0; // read disable
end
end
CLEAR : begin
r_next <= IDLE;
r_data_valid <= 0;
r_read_enable <= 1;
end
default: begin
r_next <= IDLE; // on error
end
endcase
end
end
endmodule
segment4x7.v
+146
View File
@@ -0,0 +1,146 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - 7 segmet display module
//
// Detailed module description:
// Outputs information on 7 segmet display
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module segment4x7(
input clk, // 10kHz clock
input [15:0] in, // input
output [6:0] seg, // individual segments of number
output [3:0] an, // anode to select character
output dp // dot on 7segment display
);
//-------------Internal Constants---------------------------
parameter SIZE = 2;
parameter [SIZE-1:0] ONE = 2'b00,
TWO = 2'b01,
THREE = 2'b10,
FOUR = 2'b11;
reg [SIZE-1:0] state=ONE, next=TWO;
reg [3:0] nibble = 'b0 ;
//---------State register sequential always block-----------
always @(posedge clk ) begin
state <= next;
end
//----Next state & outputs, combinational always block------
always@(state or in)begin
case(state)
ONE : begin
next <= TWO;
nibble <= in[3:0];
end
TWO : begin
next <= THREE;
nibble <= in[7:4];
end
THREE : begin
next <= FOUR;
nibble <= in[11:8];
end
FOUR : begin
next <= ONE;
nibble <= in[15:12];
end
endcase
end
assign seg[6] = ( nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hD ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[5] = ( nibble == 4'h0 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[4] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hD ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[3] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hD ||
nibble == 4'hE ) ? 1'b0 : 1'b1;
assign seg[2] = ( nibble == 4'h0 ||
nibble == 4'h1 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hD ) ? 1'b0 : 1'b1;
assign seg[1] = ( nibble == 4'h0 ||
nibble == 4'h1 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hD ) ? 1'b0 : 1'b1;
assign seg[0] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hC ||
nibble == 4'hE ||
nibble == 4'hF) ? 1'b0 : 1'b1;
assign dp = 1'b1; //dot not using
assign an[0] = (state==ONE) ? 1'b0 : 1'b1;
assign an[1] = (state==TWO) ? 1'b0 : 1'b1;
assign an[2] = (state==THREE) ? 1'b0 : 1'b1;
assign an[3] = (state==FOUR) ? 1'b0 : 1'b1;
endmodule
sync_fifo.v
-119
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@@ -1,119 +0,0 @@
// Fifo code source:
// https://vlsicoding.blogspot.com/2013/11/verilog-code-for-synchronous-fifo.html
//
module sync_fifo #( parameter
//---------------parametre declaration
data_width = 4,
address_width = 4,
ram_depth = 16 // must be 2^n
)(
//--------------input output port declaration
output reg signed [data_width-1:0] data_out,
output full,
output empty,
output [address_width-1:0] data_fill,
input signed [data_width-1:0] data_in,
input w_clk, // write clock
input r_clk, // read clock
input reset,
input wr_en,
input rd_en);
//--------------internal register declaration
reg [address_width-1:0] wr_pointer = 0;
reg [address_width-1:0] rd_pointer = 0;
// reg [address_width :0] status_count = 0;
wire signed [data_width-1:0] data_ram ;
// reg addition = 0;
// reg subtractor = 0;
// always@(posedge addition )
// begin
// if (addition ^ subtractor) // if XOR
// begin
// if (status_count != 0)
// status_count = status_count + 1;
// end
// addition = 0; // reset addition
// end
// always@(posedge subtractor)
// begin
// if (addition ^ subtractor) // if XOR
// begin
// if (status_count != 0)
// status_count = status_count - 1;
// end
// subtractor = 0; // reset subtractor
// end
//--------------wr_pointer pointing to write address
always @ (posedge w_clk,posedge reset)
begin
if(reset)
wr_pointer = 0;
else if(wr_en)
wr_pointer = wr_pointer+1;
//addition = 1;
end
//-------------rd_pointer points to read address
always @ (posedge r_clk,posedge reset)
begin
if(reset)
rd_pointer = 0;
else if(rd_en)
rd_pointer = rd_pointer + 1;
//subtractor = 1;
end
//-------------read from FIFO
always @ (posedge r_clk,posedge reset)
begin
if(reset)
data_out=0;
else if(rd_en)
data_out=data_ram;
end
// //--------------Status pointer for full and empty checking
// always @ (posedge w_clk,posedge r_clk,posedge reset)
// begin
// if(reset)
// status_count = 0;
// else if(wr_en && !rd_en && (status_count != ram_depth))
// status_count = status_count + 1;
// else if(rd_en && !wr_en && (status_count != 0))
// status_count = status_count - 1;
// end // always @ (posedge clk,posedge reset)
// assign full = (status_count == (ram_depth));
// assign empty = (status_count == 0);
// assign data_fill = status_count; // how full are FIFO
assign full = (wr_pointer - rd_pointer == ram_depth) ? 1'b1 : 1'b0 ;
assign empty = (wr_pointer - rd_pointer == 0) ? 1'b1 : 1'b0 ;
assign data_fill = wr_pointer - rd_pointer ; // how full are FIFO
rams_tdp_rf_rf #(
.DEPTH(ram_depth),
.ADDR_WIDTH(address_width),
.DATA_WIDTH(data_width)
) memory1 (
.addra(wr_pointer),
.addrb(rd_pointer),
.dia(data_in),
.dib(),
.doa(),
.dob(data_ram),
.wea(wr_en),
.web(1'b0),
.ena(1'b1),
.enb(rd_en),
.clka(w_clk),
.clkb(r_clk)
);
endmodule // sync_fifo
top.v
+44 -76
View File
@@ -1,8 +1,19 @@
// TOP module
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Top module
//
// Detailed module description:
//
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
module top #( parameter
sclk_ws_ratio = 64, // number of sclk periods per word select period
mclk_sclk_ratio = 4, // number of mclk periods per sclk period
@@ -12,7 +23,11 @@ module top #( parameter
input clk,
input btnC,
output [15:0] led,
// input [1:0] sw, // swiches on board to control effects
output [6:0] seg,
output dp,
output [3:0] an,
input [15:0] sw, // swiches on board to control effects
output da_mclk,
output ad_mclk,
@@ -26,7 +41,7 @@ module top #( parameter
);
//assign output from effect controler to leds
assign led = l_data_tx[d_width-1: d_width-16];
assign led = sw;
assign da_mclk = master_clk; //output master clock to ADC
assign ad_mclk = master_clk; //output master clock to DAC
@@ -38,11 +53,11 @@ wire master_clk; // 11.29 MHz master clock
wire clk_50MHz; //
wire w_reset, w_reset1, w_reset2;
wire w_reset;
wire w_internal_reset;
wire signed [d_width-1: 0] r_data_tx;
wire signed [d_width-1: 0] l_data_tx;
// wire signed [d_width-1: 0] r_data_tx;
// wire signed [d_width-1: 0] l_data_tx;
wire signed [d_width-1: 0] r_data_rx;
wire signed [d_width-1: 0] l_data_rx;
@@ -76,27 +91,14 @@ clk_wiz_0 m_clk(
.reset(btnC)
);
// Flip-flops for reset
// Flip-flop for reset
d_flipflop_sync_rst D_flipflop1 (
.D(1'b0),
.Q(w_reset1),
.clk(master_clk),
.reset(~w_internal_reset));
d_flipflop_sync_rst D_flipflop2 (
.D(w_reset1),
.Q(w_reset2),
.clk(master_clk),
.reset(~w_internal_reset));
d_flipflop_sync_rst D_flipflop3 (
.D(w_reset2),
.Q(w_reset),
.clk(master_clk),
.reset(~w_internal_reset));
io_module #(
.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
@@ -110,8 +112,8 @@ io_module #(
.ad_ws(ad_lrck), //word select (or left-right clock)
.sd_tx(da_sdin), //serial data transmit
.sd_rx(ad_sdout), //serial data receive
.l_data_tx(l_data_tx), //left channel data to transmit
.r_data_tx(r_data_tx), //right channel data to transmit
.l_data_tx(l_data_rx), //left channel data to transmit
.r_data_tx(r_data_rx), //right channel data to transmit
.reset(w_reset), //reset
@@ -119,65 +121,31 @@ io_module #(
.r_data_rx(r_data_rx), //right channel data received
// // inputs to logic analyzer
// .ch0(),
// .ch1(),
// .ch2(),
// .ch3(),
// .ch4(),
// .ch5(),
// .ch6(),
// .ch7(),
// inputs to logic analyzer
.ch0(clk10k),
.ch1(da_sclk),
.ch2(da_lrck),
.ch3(da_sdin),
.ch4(master_clk),
.ch5(ad_sclk),
.ch6(ad_lrck),
.ch7(ad_sdout),
.JXADC(JXADC) // output for logic analizer
);
segment4x7 segment4x7(
.clk(clk10k), // 10kHz clock
.in(sw), // input
.seg(seg), // individual segments of number
.an(an), // anode to select character
.dp(dp) // dot on 7segment display
);
//Effect controler controls effects and perfoms multiplexing and data marging
effect_controler #(
.d_width(d_width), // data width
.memory_d_width(memory_d_width)
) effect_controler (
.reset(w_reset), // asynchronous active high reset
.mclk(master_clk),
.sw(sw[1:0]),
.clk(clk_50MHz),
.i_l_data(l_data_rx), // left channel data received
.i_r_data(r_data_rx), // right channel data received
// .i_l_data({sw[15:2], 10'b0 }), // left channel data received
// .i_r_data({sw[15:2], 10'b0 }), // right channel data received
.o_l_data(l_data_tx), // left channel data to transmit
.o_r_data(r_data_tx), // right channel data to transmit
.o_read_done(w_read_done_eff), // read done from effects controler
.o_read_ready(w_read_ready_eff), // ready read from reefects module
.o_data_to_eff(w_data_to_eff), // Data output to effects module
.o_data_valid(w_dv_to_eff), // data valid to read (FIFO not empty). data valid signal to effect module
.i_read_enable(w_rd_en_from_eff), // read enable from Effect module
.i_dv_from_eff(w_dv_from_eff), // data valid write (FIFO not full). data valid signal from effect module
.i_data_from_eff_sw0(w_data_from_eff_sw0), // Data input from effects module
.i_data_from_eff_sw1(w_data_from_eff_sw1) // Data input from effects module
clock_divider #(.WIDTH(9))
clock_divider7seg (
.clk_in(clk_50MHz),
.clk_out(clk10k)
);
//Effect module contains all individual effects
effect_module #(
.d_width(memory_d_width) // data width
) effect_module (
.clk(clk_50MHz),
.reset(w_reset),
.sw(sw[1:0]), // effect control swiches
.i_treshhold(sw[15:2]),
.i_data_ready(w_dv_to_eff), // data ready to read
.i_read_done(w_read_done_eff), // read done from effects controler
.i_data(w_data_to_eff), // data input form effect controler
.o_read_enable(w_rd_en_from_eff), // enable data reading
.o_data_valid(w_dv_from_eff),
.o_data_sw0(w_data_from_eff_sw0),
.o_data_sw1(w_data_from_eff_sw1)
);
endmodule
top_tb.v
+13
View File
@@ -1,6 +1,19 @@
/////////////////////////////////////////////////////////////////
// Author - Imants Pulkstenis
// Date - 04.04.2020
// Project name - Audio FFT on FPGA
// Module name - Test Bench for top module
//
// Detailed module description:
// This file is Test Bench for top module
//
//
// Revision:
// A - initial design
// B -
// C -
//
///////////////////////////////////////////////////////////////////
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW