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Spliting i2s transceiver in to two modules

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i2s sender and i2s receiver.
Also add JXADC_controler for logic analizer.
This commit is contained in:
Imants Pulkstenis
2019-10-20 18:38:10 +03:00
parent 31f01e93b3
commit 8da9e7da7c
7 changed files with 327 additions and 62 deletions
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i2s_transceiver.v
+19 -16
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@@ -35,21 +35,21 @@ module i2s_transceiver #( parameter
input sd_rx, //serial data receive
input signed [d_width-1: 0] l_data_tx, //left channel data to transmit
input signed [d_width-1: 0] r_data_tx, //right channel data to transmit
output signed [d_width-1: 0] l_data_rx, //left channel data received
output signed [d_width-1: 0] r_data_rx //right channel data received
output reg signed [d_width-1: 0] l_data_rx, //left channel data received
output reg signed [d_width-1: 0] r_data_rx //right channel data received
);
reg sclk_int = 0; //internal serial clock wire
reg ws_int = 0; //internal word select wire
reg signed [d_width-1: 0] l_data_rx_int = 0; //internal left channel rx data buffer
reg signed [d_width-1: 0] r_data_rx_int = 0; //internal right channel rx data buffer
reg signed [d_width-1: 0] l_data_tx_int = 0; //internal left channel tx data buffer
reg signed [d_width-1: 0] r_data_tx_int = 0; //internal right channel tx data buffer
reg signed [d_width-1: 0] l_data_rx_int = 'sb0; //internal left channel rx data buffer
reg signed [d_width-1: 0] r_data_rx_int = 'sb0; //internal right channel rx data buffer
reg signed [d_width-1: 0] l_data_tx_int = 'sb0; //internal left channel tx data buffer
reg signed [d_width-1: 0] r_data_tx_int = 'sb0; //internal right channel tx data buffer
reg r_sd_tx = 0; //internal register
reg signed [d_width-1: 0] reg_r_data_rx = 0;
reg signed [d_width-1: 0] reg_l_data_rx = 0;
reg signed [d_width-1: 0] reg_r_data_rx = 'sb0;
reg signed [d_width-1: 0] reg_l_data_rx = 'sb0;
reg [2: 0] sclk_cnt = 0; //counter of master clocks during half period of serial clock
@@ -64,13 +64,13 @@ always@(posedge mclk, posedge reset_n) begin
ws_cnt <= 'b0; //clear sclk/ws counter
sclk_int <= 0; //clear serial clock signal
ws_int <= 0; //clear word select signal
l_data_rx_int <= 'b0; //clear internal left channel rx data buffer
r_data_rx_int <= 'b0; //clear internal right channel rx data buffer
l_data_tx_int <= 'b0; //clear internal left channel tx data buffer
r_data_tx_int <= 'b0; //clear internal right channel tx data buffer
l_data_rx_int <= 'sb0; //clear internal left channel rx data buffer
r_data_rx_int <= 'sb0; //clear internal right channel rx data buffer
l_data_tx_int <= 'sb0; //clear internal left channel tx data buffer
r_data_tx_int <= 'sb0; //clear internal right channel tx data buffer
r_sd_tx <= 0; //clear serial data transmit output
reg_l_data_rx <= 'b0; //clear left channel received data output
reg_r_data_rx <= 'b0; //clear right channel received data output
//reg_l_data_rx <= 'sb0; //clear left channel received data output
//reg_r_data_rx <= 'sb0; //clear right channel received data output
end
else begin //master clock rising edge
if (sclk_cnt < mclk_sclk_ratio/2-1) begin //less than half period of sclk
@@ -103,6 +103,8 @@ always@(posedge mclk, posedge reset_n) begin
ws_int <= ~ws_int; //toggle word select
// reg_r_data_rx <= r_data_rx_int; //output right channel received data
// reg_l_data_rx <= l_data_rx_int; //output left channel received data
r_data_rx <= r_data_rx_int; //output right channel received data
l_data_rx <= l_data_rx_int; //output left channel received data
r_data_tx_int <= r_data_tx; //latch in right channel data to transmit
l_data_tx_int <= l_data_tx; //latch in left channel data to transmit
end
@@ -115,7 +117,8 @@ assign ws = ws_int; //output word select
assign sd_tx = r_sd_tx; //assign sd_tx
//assign r_data_rx = reg_r_data_rx;
//assign l_data_rx = reg_l_data_rx;
assign r_data_rx = ~(ws_cnt < sclk_ws_ratio - 1)? r_data_rx_int: r_data_rx ;
assign l_data_rx = ~(ws_cnt < sclk_ws_ratio - 1)? l_data_rx_int: l_data_rx ;
//assign r_data_rx = ~(ws_cnt < sclk_ws_ratio - 1)? r_data_rx_int: r_data_rx ;
//assign l_data_rx = ~(ws_cnt < sclk_ws_ratio - 1)? l_data_rx_int: l_data_rx ;
endmodule