add i2s files

i2s_playback.v

@@ -0,0 +1,47 @@
+// This I2S Playback design uses the common 44.1 kHz 
+// sampling frequency.  
+// From Figure 2 in Section 4.1.1 of the CS5343 
+// Datasheet, it is appropriate to use an SCLK/LRCK 
+// ratio of 64 and a MCLK/LRCK ratio of 256.  
+// Therefore, the I2S Transceiver’s generic 
+// parameter sclk_ws_ratio is set to 64.  
+// (LRCK, e.g. left-right clock, and ws, 
+// e.g. word select, are synonymous.)  
+// The generic parameter mclk_sclk_ratio is set to 4, 
+// since MCLK/SCLK = (MCLK/LRCK) / (SCLK/LRCK) = 256/64 = 4.
+
+
+
+module i2c_transceiver #( parameter
+    d_width = 24            // data width
+    mclk_sclk_ratio => 4, 
+    sclk_ws_ratio => 64
+)(
+    input       clock,      // system clock (100 MHz on Basys board)
+    input       reset_n,    // active low asynchronous reset
+    output      mclk,       // master clock
+    output      sclk,       // serial clock (or bit clock)
+    output      ws,         // word select (or left-right clock)
+    input       sd_rx,      // serial data in
+    output      sd_tx       // serial data out
+    );
+
+    wire master_clk;                    //internal master clock signal
+    reg serial_clk = 0;                 //internal serial clock signal
+    reg word_select  = 0;               //internal word select signal
+    wire l_data_rx[d_width-1 : 0];      //left channel data received from I2S Transceiver component
+    wire r_data_rx[d_width-1 : 0];      //right channel data received from I2S Transceiver component
+    wire l_data_tx[d_width-1 : 0];      //left channel data to transmit using I2S Transceiver component
+    wire r_data_tx[d_width-1 : 0];      //right channel data to transmit using I2S Transceiver component
+
+
+//declare PLL to create 11.29 MHz master clock from 100 MHz system clock
+clk_wiz_0 clk_wiz_0(
+    .clk_in1(clock),
+    .clk_out1(master_clk)
+    );
+
+
+
+
+endmodule

i2s_transceiver.v

@@ -0,0 +1,27 @@
+// This I2S Playback design uses the common 44.1 kHz 
+// sampling frequency.  
+// From Figure 2 in Section 4.1.1 of the CS5343 
+// Datasheet, it is appropriate to use an SCLK/LRCK 
+// ratio of 64 and a MCLK/LRCK ratio of 256.  
+// Therefore, the I2S Transceiver’s generic 
+// parameter sclk_ws_ratio is set to 64.  
+// (LRCK, e.g. left-right clock, and ws, 
+// e.g. word select, are synonymous.)  
+// The generic parameter mclk_sclk_ratio is set to 4, 
+// since MCLK/SCLK = (MCLK/LRCK) / (SCLK/LRCK) = 256/64 = 4.
+
+
+
+module i2c_transceiver #( parameter
+    sclk_ws_ratio = 64,
+    mclk_sclk_ratio = 4
+)(
+    output          sclk,
+    input           mclk,
+    output          ws,
+    input           sd_rx,
+    output          sd_tx    );
+
+
+
+endmodule

top.v

@@ -1,5 +1,14 @@
 //      TOP module 
 //       
+// Fs = audio sample frequency
+// I2S bitrate = (#bits/channel) x (#channels) x Fs
+//         Ex: 24-bit stereo (2 channels)
+//         I2S bitrate = 24 x 2 x Fs
+//
+// I2SxCLK source = PLLI2S output or ext. input (I2S_CKIN)
+// Fs = 48kHz, 96kHz or 192kHz
+// Fs = I2SxCLK / [(CF*2) * (2*I2SDIV+ODD)*8)]
+//         CF = channel frame (24 bits)
 //      
 // `include "clock_divider_param.v"
 // `include "clock_enable_param.v"
@@ -16,7 +25,8 @@ module top #( parameter
 
 //------internal wires and registers--------
 // wire w_enable;
-wire clk50;    
+wire clk48k;    
+wire clk25M; 
 
 //-----sub modules--------------------------
 // clock_enable_param #(
@@ -28,11 +38,19 @@ wire clk50;
 // );
 
 clock_divider #(
-    .DIVIDER(1),
-    .WIDTH(3)
-) clk50mhz_gen (
+    .DIVIDER(1042),
+    .WIDTH(11)
+) clk48k_gen (
     .clk(clk),
-    .clk_out(clk50)
+    .clk_out(clk48k) // 48kHz clock 
+);
+
+clock_divider #(
+    .DIVIDER(2),
+    .WIDTH(2)
+) clk25M_gen (
+    .clk(clk),
+    .clk_out(clk25M) // 25MHz clock 
 );
 
 // debounce_switch debounce_switch_reset(