27 lines
753 B
Verilog
27 lines
753 B
Verilog
// This I2S Playback design uses the common 44.1 kHz
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// sampling frequency.
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// From Figure 2 in Section 4.1.1 of the CS5343
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// Datasheet, it is appropriate to use an SCLK/LRCK
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// ratio of 64 and a MCLK/LRCK ratio of 256.
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// Therefore, the I2S Transceiver’s generic
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// parameter sclk_ws_ratio is set to 64.
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// (LRCK, e.g. left-right clock, and ws,
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// e.g. word select, are synonymous.)
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// The generic parameter mclk_sclk_ratio is set to 4,
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// since MCLK/SCLK = (MCLK/LRCK) / (SCLK/LRCK) = 256/64 = 4.
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module i2c_transceiver #( parameter
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sclk_ws_ratio = 64,
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mclk_sclk_ratio = 4
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)(
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output sclk,
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input mclk,
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output ws,
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input sd_rx,
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output sd_tx );
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endmodule |