start
This commit is contained in:
Imants Pulkstenis
+3
-3
@@ -4,9 +4,9 @@
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock signal
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#set_property PACKAGE_PIN W5 [get_ports clk]
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#set_property IOSTANDARD LVCMOS33 [get_ports clk]
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#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
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set_property PACKAGE_PIN W5 [get_ports clk]
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set_property IOSTANDARD LVCMOS33 [get_ports clk]
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
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## Switches
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#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
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@@ -0,0 +1,83 @@
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/*
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//////////////////////////////////////////////////////////////////
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//
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// How do I use the Fully Open Source iCE40 Flow?
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// Synthesis for iCE40 FPGAs can be done with Yosys.
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// Place-and-route can be done with arachne-pnr.
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// Here is an example script for implementing and
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// programming the rot example from arachne-pnr
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// (this example targets the iCEstick development board):
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//
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///////////////////////////////////////////////////////////////////
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yosys -p "synth_ice40 -blif output.blif" blockram.v
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arachne-pnr -d 1k -p output.pcf output.blif -o output.asc
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icepack output.asc output.bin
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iceprog output.bin
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A simple timing analysis report can be generated using the icetime
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utility:
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icetime -tmd hx1k rot.asc
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///////////////////////////////////////////////////////////////
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For Go Board
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yosys -p "read_verilog blockram.v; synth_ice40 -blif output.blif"
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arachne-pnr -d 1k -p constraints.pcf -P vq100 -o output.asc output.blif
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icepack output.asc output.bin
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icetime -d hx1k output.asc
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iceprog output.bin
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*/
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//////////////////////////////////////////////////////////////////////
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// //
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// Icarus Verilog //
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// http://iverilog.wikia.com/wiki/Main_Page //
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//////////////////////////////////////////////////////////////////////
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/*
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// Do this in your test bench
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always #1 r_Clock <= ~r_Clock;
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initial
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begin
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#2_000;
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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$display("----------------------------------------------");
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$display(" ");
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end
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Code:
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iverilog -o output.vvp clock_enable_tb.v
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vvp output.vvp
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gtkwave -f wave.vcd
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Or one line:
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iverilog -o output.vvp top_tb.v && vvp output.vvp && gtkwave -f wave.vcd
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*/
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/////////////////////////////////////////////////////
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//
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// Serial comunication: Linux
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//
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// stty -F /dev/ttyUSB1 115200 # set speed
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// screen /dev/ttyUSB1 115200 # set spped
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//
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//
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// minicom # -s ender setup screen
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// # minicom can send file
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////////////////////////////////////////////////////
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@@ -0,0 +1,23 @@
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dt = 0.01;
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T = 1;
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t = [0:dt:T]' ;
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omega0 = 2 * pi /T;
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N = length (t);
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N2 = round (N/2);
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x = ones(N, 1);
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x (N2 + 1:N) = -1 * ones(N - N2, 1);
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a(1) = 1/T * ( sum (x) * dt);
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xfs = a(1) * ones( size(x));
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for k = 1:10
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ck = cos (k * omega0 * t); % cosine component
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a(k + 1) = 2/T * ( sum (x.* ck) * dt);
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sk = sin (k * omega0 * t); % sine component
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b(k + 1) = 2/T * ( sum (x.* sk) * dt);
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% Fourier series approximation
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xfs = xfs + a(k + 1) * cos (k * omega0 * t) + b(k + 1) * sin (k * omega0 * t);
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plot (t, x, '-' , t, xfs, ':' );
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legend ( ' desired ' , ' approximated ' );
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drawnow ;
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pause (1);
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end
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+227
@@ -0,0 +1,227 @@
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%% FFT algoritm
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start_time = 0;
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number_of_samples = 16;
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end_time = number_of_samples - 1;
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n = linspace(start_time, end_time , number_of_samples );
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f1 = 5;
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a1 = 0.2;
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f2 = 2;
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a2 = 00;
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f3 = 1;
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a3 = 00;
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comp1 = a1 * sin( f1 *2*pi*n/number_of_samples);
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comp2 = a2 * sin( f2 *2*pi*n/number_of_samples);
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comp3 = a3 * sin( f3 *2*pi*n/number_of_samples);
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data = comp1 + comp2 + comp3;
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figure(1)
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plot (n, comp1, '-');
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hold on;
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plot (n, comp2, '-');
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plot (n, comp3, '-');
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hold off;
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figure(2)
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plot (n, data);
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figure(3)
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X_matlab = fft(data, number_of_samples);
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stem (n,abs(X_matlab))
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%% My FFT
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% W_N vector calculation
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% W = zeros(1,number_of_samples); % complex
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% Wr = zeros(1,number_of_samples); % real
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% Wi = zeros(1,number_of_samples); % imag
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% for i = 1 : number_of_samples
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% W(i) = exp(-j * (i-1) * 2 * pi/ number_of_samples );
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% Wr(i) = real(W(i));
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% Wi(i) = imag(W(i));
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% end
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% reverse bit calulation
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bits = length(dec2bin( number_of_samples - 1 ));
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rev_bit_dec = zeros(1,number_of_samples);
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for i=1:number_of_samples
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bin_num = dec2bin(i-1 , bits);
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rev_bit = [];
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for k=bits:-1:1
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rev_bit = [rev_bit , bin_num(k)];
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end
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rev_bit_dec(i) = bin2dec(rev_bit) + 1; % add 1 to match Matlab numbering
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end
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% First stage of FFT
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s_1_2 = zeros(1,number_of_samples);
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stage = zeros(bits,number_of_samples);
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for i=1:number_of_samples
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if rem(i-1,2) == 0 % odd or even
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stage(1,i) = data(rev_bit_dec(i)) + data(rev_bit_dec(i+1));
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else
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stage(1,i) = data(rev_bit_dec(i)) - data(rev_bit_dec(i-1));
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end
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end
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% s_1_2(1) = data(rev_bit_dec(1)) + data(rev_bit_dec(2));
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% s_1_2(2) = data(rev_bit_dec(2)) - data(rev_bit_dec(1));
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%
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% s_1_2(3) = data(rev_bit_dec(3)) + data(rev_bit_dec(4));
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% s_1_2(4) = data(rev_bit_dec(4)) - data(rev_bit_dec(3));
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%
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% s_1_2(5) = data(rev_bit_dec(5)) + data(rev_bit_dec(6));
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% s_1_2(6) = data(rev_bit_dec(6)) - data(rev_bit_dec(5));
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%
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% s_1_2(7) = data(rev_bit_dec(7)) + data(rev_bit_dec(8));
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% s_1_2(8) = data(rev_bit_dec(8)) - data(rev_bit_dec(7));
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%
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% s_1_2(9) = data(rev_bit_dec(9)) + data(rev_bit_dec(10));
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% s_1_2(10) = data(rev_bit_dec(10)) - data(rev_bit_dec(9));
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%
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% s_1_2(11) = data(rev_bit_dec(11)) + data(rev_bit_dec(12));
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% s_1_2(12) = data(rev_bit_dec(12)) - data(rev_bit_dec(11));
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%
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% s_1_2(13) = data(rev_bit_dec(13)) + data(rev_bit_dec(14));
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% s_1_2(14) = data(rev_bit_dec(14)) - data(rev_bit_dec(13));
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%
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% s_1_2(15) = data(rev_bit_dec(15)) + data(rev_bit_dec(16));
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% s_1_2(16) = data(rev_bit_dec(16)) - data(rev_bit_dec(15));
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% s_1_2(1) = data(1) + data(5);
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% s_1_2(2) = data(5) - data(1);
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%
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% s_1_2(3) = data(3) + data(7);
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% s_1_2(4) = data(7) - data(3);
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%
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% s_1_2(5) = data(2) + data(6);
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% s_1_2(6) = data(6) - data(2);
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%
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% s_1_2(7) = data(4) + data(8);
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% s_1_2(8) = data(8) - data(4);
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% s_1_2,
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% stage,
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% Second stage
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s_2_3 = zeros(1,number_of_samples);
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s_2_3(1) = s_1_2(1) + W(1) * s_1_2(3);
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s_2_3(2) = s_1_2(2) + W(3) * s_1_2(4);
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s_2_3(3) = s_1_2(3) + W(5) * s_1_2(1);
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s_2_3(4) = s_1_2(4) + W(7) * s_1_2(2);
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s_2_3(5) = s_1_2(5) + W(1) * s_1_2(7);
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s_2_3(6) = s_1_2(6) + W(3) * s_1_2(8);
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s_2_3(7) = s_1_2(7) + W(5) * s_1_2(5);
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s_2_3(8) = s_1_2(8) + W(7) * s_1_2(6);
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W1 = zeros(1,4); % complex
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for i = 1 : 4
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W1(i) = exp(-j * (i-1) * 2 * pi/ 4 );
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end
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stage(2,1) = stage(1,1) + W1(1) * stage(1,3);
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stage(2,2) = stage(1,2) + W1(2) * stage(1,4);
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stage(2,3) = stage(1,3) - W1(1) * stage(1,1);
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stage(2,4) = stage(1,4) - W1(2) * stage(1,2);
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stage(2,5) = stage(1,5) + W1(1) * stage(1,7);
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stage(2,6) = stage(1,6) + W1(2) * stage(1,8);
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stage(2,7) = stage(1,7) - W1(1) * stage(1,5);
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stage(2,8) = stage(1,8) - W1(2) * stage(1,6);
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stage(2,9) = stage(1,9) + W1(1) * stage(1,11);
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stage(2,10) = stage(1,10) + W1(2) * stage(1,12);
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stage(2,11) = stage(1,11) - W1(1) * stage(1,9);
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stage(2,12) = stage(1,12) - W1(2) * stage(1,10);
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stage(2,13) = stage(1,13) + W1(1) * stage(1,15);
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stage(2,14) = stage(1,14) + W1(2) * stage(1,16);
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stage(2,15) = stage(1,15) - W1(1) * stage(1,13);
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stage(2,16) = stage(1,16) - W1(2) * stage(1,14);
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% theard stage
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s_3_4 = zeros(1,number_of_samples);
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s_3_4(1) = s_2_3(1) + W(1) * s_2_3(5);
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s_3_4(2) = s_2_3(2) + W(2) * s_2_3(6);
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s_3_4(3) = s_2_3(3) + W(3) * s_2_3(7);
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s_3_4(4) = s_2_3(4) + W(4) * s_2_3(8);
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s_3_4(5) = s_2_3(5) + W(5) * s_2_3(1);
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s_3_4(6) = s_2_3(6) + W(6) * s_2_3(2);
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s_3_4(7) = s_2_3(7) + W(7) * s_2_3(3);
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s_3_4(8) = s_2_3(8) + W(8) * s_2_3(4);
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W2 = zeros(1,8); % complex
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for i = 1 : 8
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W2(i) = exp(-j * (i-1) * 2 * pi/ 8 );
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end
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stage(3,1) = stage(2,1) + W2(1) * stage(2,5);
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stage(3,2) = stage(2,2) + W2(2) * stage(2,6);
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stage(3,3) = stage(2,3) + W2(3) * stage(2,7);
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stage(3,4) = stage(2,4) + W2(4) * stage(2,8);
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stage(3,5) = stage(2,5) - W2(1) * stage(2,1);
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stage(3,6) = stage(2,6) - W2(2) * stage(2,2);
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stage(3,7) = stage(2,7) - W2(3) * stage(2,3);
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stage(3,8) = stage(2,8) - W2(4) * stage(2,4);
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stage(3,9) = stage(2,9) + W2(1) * stage(2,13);
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stage(3,10) = stage(2,10) + W2(2) * stage(2,14);
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stage(3,11) = stage(2,11) + W2(3) * stage(2,15);
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stage(3,12) = stage(2,12) + W2(4) * stage(2,16);
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stage(3,13) = stage(2,13) - W2(1) * stage(2,9);
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stage(3,14) = stage(2,14) - W2(2) * stage(2,10);
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stage(3,15) = stage(2,15) - W2(3) * stage(2,11);
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stage(3,16) = stage(2,16) - W2(4) * stage(2,12);
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% Fourt stage
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W3 = zeros(1,16); % complex
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for i = 1 : 16
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W3(i) = exp(-j * (i-1) * 2 * pi/ 16 );
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end
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stage(4,1) = stage(3,1) + W3(1) * stage(3,9);
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stage(4,2) = stage(3,2) + W3(2) * stage(3,10);
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stage(4,3) = stage(3,3) + W3(3) * stage(3,11);
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stage(4,4) = stage(3,4) + W3(4) * stage(3,12);
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stage(4,5) = stage(3,5) + W3(5) * stage(3,13);
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stage(4,6) = stage(3,6) + W3(6) * stage(3,14);
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stage(4,7) = stage(3,7) + W3(7) * stage(3,15);
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stage(4,8) = stage(3,8) + W3(8) * stage(3,16);
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stage(4,9) = stage(3,9) - W3(1) * stage(3,1);
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stage(4,10) = stage(3,10) - W3(2) * stage(3,2);
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stage(4,11) = stage(3,11) - W3(3) * stage(3,3);
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stage(4,12) = stage(3,12) - W3(4) * stage(3,4);
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stage(4,13) = stage(3,13) - W3(5) * stage(3,5);
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stage(4,14) = stage(3,14) - W3(6) * stage(3,6);
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stage(4,15) = stage(3,15) - W3(7) * stage(3,7);
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stage(4,16) = stage(3,16) - W3(8) * stage(3,8);
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figure(4)
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stem(n, abs( stage(4,:) ) )
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@@ -0,0 +1,16 @@
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f = 4000;
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fs = 22050;
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fftLength=1024; %windowlength
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x =sin(2*pi*f*[0:1/fs:1]); %makethesinewave
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ft =fft(x,fftLength); %doFFT,userect.window
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ftMag=abs(ft); %computemagnitude
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% plot the results both in linear and dB magnitudes
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subplot(2, 1, 1), plot(ftMag)
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title('Linear Magnitude')
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ylabel('magnitude'), xlabel('bins')
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subplot(2, 1, 2), plot(20*log10(ftMag))
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title('dB Magnitude')
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ylabel('dB'), xlabel('bins')
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@@ -3,31 +3,29 @@
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//
|
||||
// `include "clock_divider_param.v"
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// `include "clock_enable_param.v"
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||||
// `include "debounce_switch.v"
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||||
|
||||
|
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module top #( parameter
|
||||
//pattern generator paremater
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||||
SPEED = 300,
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||||
//enable signal parameters
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||||
WAIT = 1,
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||||
WAIT_WIDTH = 2,
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||||
WAIT_WIDTH = 2
|
||||
)(
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||||
input clk
|
||||
);
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||||
|
||||
//------internal wires and registers--------
|
||||
wire w_enable;
|
||||
|
||||
// wire w_enable;
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||||
wire clk50;
|
||||
|
||||
//-----sub modules--------------------------
|
||||
clock_enable_param #(
|
||||
.WAIT(WAIT),
|
||||
.WIDTH(WAIT_WIDTH)
|
||||
) clock_enable1 (
|
||||
.clk(clk),
|
||||
.enable(w_enable)
|
||||
);
|
||||
// clock_enable_param #(
|
||||
// .WAIT(WAIT),
|
||||
// .WIDTH(WAIT_WIDTH)
|
||||
// ) clock_enable1 (
|
||||
// .clk(clk),
|
||||
// .enable(w_enable)
|
||||
// );
|
||||
|
||||
clock_divider #(
|
||||
.DIVIDER(1),
|
||||
@@ -37,10 +35,10 @@ clock_divider #(
|
||||
.clk_out(clk50)
|
||||
);
|
||||
|
||||
debounce_switch debounce_switch_reset(
|
||||
.clk(clk),
|
||||
.i_switch(),
|
||||
.o_switch()
|
||||
);
|
||||
// debounce_switch debounce_switch_reset(
|
||||
// .clk(clk),
|
||||
// .i_switch(),
|
||||
// .o_switch()
|
||||
// );
|
||||
|
||||
endmodule
|
||||
@@ -16,21 +16,18 @@
|
||||
//top module
|
||||
`include "top.v"
|
||||
|
||||
module top_vga_mem_tb#( parameter
|
||||
WAIT = 1,
|
||||
WAIT_WIDTH = 2,
|
||||
SPEED = 2,
|
||||
//memory parameters
|
||||
ADDR_WIDTH = 17, //19, //
|
||||
DATA_WIDTH = 12,
|
||||
DEPTH = 307_200//76_800, //
|
||||
)();
|
||||
module top_tb();
|
||||
|
||||
reg clk = 1'b0;
|
||||
|
||||
// 50% duty cycle clock
|
||||
always #0.5 clk <= ~clk;
|
||||
|
||||
top UUT(
|
||||
.clk(clk)
|
||||
);
|
||||
|
||||
|
||||
|
||||
initial begin
|
||||
#030_000;
|
||||
|
||||
Reference in New Issue
Block a user