diff --git a/Basys3_Master.xdc b/Basys3_Master.xdc index f64d631..7e4df19 100644 --- a/Basys3_Master.xdc +++ b/Basys3_Master.xdc @@ -4,9 +4,9 @@ ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock signal -#set_property PACKAGE_PIN W5 [get_ports clk] - #set_property IOSTANDARD LVCMOS33 [get_ports clk] - #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] +set_property PACKAGE_PIN W5 [get_ports clk] + set_property IOSTANDARD LVCMOS33 [get_ports clk] + create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## Switches #set_property PACKAGE_PIN V17 [get_ports {sw[0]}] diff --git a/README.md b/README.md index 5c74f34..7b90f78 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,3 @@ # Audio effects on FPGA + Audio effect synthesizer on FPGA diff --git a/comands.v b/comands.v new file mode 100644 index 0000000..60a969d --- /dev/null +++ b/comands.v @@ -0,0 +1,83 @@ +/* +////////////////////////////////////////////////////////////////// +// +// How do I use the Fully Open Source iCE40 Flow? +// Synthesis for iCE40 FPGAs can be done with Yosys. +// Place-and-route can be done with arachne-pnr. +// Here is an example script for implementing and +// programming the rot example from arachne-pnr +// (this example targets the iCEstick development board): +// +/////////////////////////////////////////////////////////////////// + + yosys -p "synth_ice40 -blif output.blif" blockram.v + arachne-pnr -d 1k -p output.pcf output.blif -o output.asc + icepack output.asc output.bin + iceprog output.bin + +A simple timing analysis report can be generated using the icetime +utility: + + icetime -tmd hx1k rot.asc + +/////////////////////////////////////////////////////////////// +For Go Board + + yosys -p "read_verilog blockram.v; synth_ice40 -blif output.blif" + arachne-pnr -d 1k -p constraints.pcf -P vq100 -o output.asc output.blif + icepack output.asc output.bin + icetime -d hx1k output.asc + iceprog output.bin + +*/ + +////////////////////////////////////////////////////////////////////// +// // +// Icarus Verilog // +// http://iverilog.wikia.com/wiki/Main_Page // +////////////////////////////////////////////////////////////////////// +/* + // Do this in your test bench + + always #1 r_Clock <= ~r_Clock; + + initial + begin + #2_000; + $finish(); + end + + initial + begin + $display(" "); + $display("----------------------------------------------"); + $display(" Starting Testbench..."); + $dumpfile("wave.vcd"); + $dumpvars(0); + $display("----------------------------------------------"); + $display(" "); + end + + +Code: + iverilog -o output.vvp clock_enable_tb.v + vvp output.vvp + gtkwave -f wave.vcd + +Or one line: +iverilog -o output.vvp top_tb.v && vvp output.vvp && gtkwave -f wave.vcd + + +*/ +///////////////////////////////////////////////////// +// +// Serial comunication: Linux +// +// stty -F /dev/ttyUSB1 115200 # set speed +// screen /dev/ttyUSB1 115200 # set spped +// +// +// minicom # -s ender setup screen +// # minicom can send file +//////////////////////////////////////////////////// + diff --git a/matlab/fourier_aprox.m b/matlab/fourier_aprox.m new file mode 100644 index 0000000..913251f --- /dev/null +++ b/matlab/fourier_aprox.m @@ -0,0 +1,23 @@ +dt = 0.01; +T = 1; +t = [0:dt:T]' ; +omega0 = 2 * pi /T; +N = length (t); +N2 = round (N/2); +x = ones(N, 1); +x (N2 + 1:N) = -1 * ones(N - N2, 1); +a(1) = 1/T * ( sum (x) * dt); +xfs = a(1) * ones( size(x)); +for k = 1:10 + ck = cos (k * omega0 * t); % cosine component + a(k + 1) = 2/T * ( sum (x.* ck) * dt); + sk = sin (k * omega0 * t); % sine component + b(k + 1) = 2/T * ( sum (x.* sk) * dt); + + % Fourier series approximation + xfs = xfs + a(k + 1) * cos (k * omega0 * t) + b(k + 1) * sin (k * omega0 * t); + plot (t, x, '-' , t, xfs, ':' ); + legend ( ' desired ' , ' approximated ' ); + drawnow ; + pause (1); +end \ No newline at end of file diff --git a/matlab/myfft.m b/matlab/myfft.m new file mode 100644 index 0000000..42239ab --- /dev/null +++ b/matlab/myfft.m @@ -0,0 +1,227 @@ +%% FFT algoritm +start_time = 0; +number_of_samples = 16; +end_time = number_of_samples - 1; +n = linspace(start_time, end_time , number_of_samples ); + +f1 = 5; +a1 = 0.2; + +f2 = 2; +a2 = 00; + +f3 = 1; +a3 = 00; +comp1 = a1 * sin( f1 *2*pi*n/number_of_samples); +comp2 = a2 * sin( f2 *2*pi*n/number_of_samples); +comp3 = a3 * sin( f3 *2*pi*n/number_of_samples); + +data = comp1 + comp2 + comp3; + + +figure(1) +plot (n, comp1, '-'); +hold on; +plot (n, comp2, '-'); +plot (n, comp3, '-'); +hold off; + +figure(2) +plot (n, data); + +figure(3) +X_matlab = fft(data, number_of_samples); +stem (n,abs(X_matlab)) + +%% My FFT + +% W_N vector calculation +% W = zeros(1,number_of_samples); % complex +% Wr = zeros(1,number_of_samples); % real +% Wi = zeros(1,number_of_samples); % imag +% for i = 1 : number_of_samples +% W(i) = exp(-j * (i-1) * 2 * pi/ number_of_samples ); +% Wr(i) = real(W(i)); +% Wi(i) = imag(W(i)); +% end + +% reverse bit calulation + +bits = length(dec2bin( number_of_samples - 1 )); +rev_bit_dec = zeros(1,number_of_samples); + +for i=1:number_of_samples + bin_num = dec2bin(i-1 , bits); + rev_bit = []; + for k=bits:-1:1 + rev_bit = [rev_bit , bin_num(k)]; + end + rev_bit_dec(i) = bin2dec(rev_bit) + 1; % add 1 to match Matlab numbering +end + +% First stage of FFT + +s_1_2 = zeros(1,number_of_samples); +stage = zeros(bits,number_of_samples); + + +for i=1:number_of_samples + if rem(i-1,2) == 0 % odd or even + stage(1,i) = data(rev_bit_dec(i)) + data(rev_bit_dec(i+1)); + else + stage(1,i) = data(rev_bit_dec(i)) - data(rev_bit_dec(i-1)); + end +end + +% s_1_2(1) = data(rev_bit_dec(1)) + data(rev_bit_dec(2)); +% s_1_2(2) = data(rev_bit_dec(2)) - data(rev_bit_dec(1)); +% +% s_1_2(3) = data(rev_bit_dec(3)) + data(rev_bit_dec(4)); +% s_1_2(4) = data(rev_bit_dec(4)) - data(rev_bit_dec(3)); +% +% s_1_2(5) = data(rev_bit_dec(5)) + data(rev_bit_dec(6)); +% s_1_2(6) = data(rev_bit_dec(6)) - data(rev_bit_dec(5)); +% +% s_1_2(7) = data(rev_bit_dec(7)) + data(rev_bit_dec(8)); +% s_1_2(8) = data(rev_bit_dec(8)) - data(rev_bit_dec(7)); +% +% s_1_2(9) = data(rev_bit_dec(9)) + data(rev_bit_dec(10)); +% s_1_2(10) = data(rev_bit_dec(10)) - data(rev_bit_dec(9)); +% +% s_1_2(11) = data(rev_bit_dec(11)) + data(rev_bit_dec(12)); +% s_1_2(12) = data(rev_bit_dec(12)) - data(rev_bit_dec(11)); +% +% s_1_2(13) = data(rev_bit_dec(13)) + data(rev_bit_dec(14)); +% s_1_2(14) = data(rev_bit_dec(14)) - data(rev_bit_dec(13)); +% +% s_1_2(15) = data(rev_bit_dec(15)) + data(rev_bit_dec(16)); +% s_1_2(16) = data(rev_bit_dec(16)) - data(rev_bit_dec(15)); + +% s_1_2(1) = data(1) + data(5); +% s_1_2(2) = data(5) - data(1); +% +% s_1_2(3) = data(3) + data(7); +% s_1_2(4) = data(7) - data(3); +% +% s_1_2(5) = data(2) + data(6); +% s_1_2(6) = data(6) - data(2); +% +% s_1_2(7) = data(4) + data(8); +% s_1_2(8) = data(8) - data(4); + +% s_1_2, +% stage, + +% Second stage + +s_2_3 = zeros(1,number_of_samples); + +s_2_3(1) = s_1_2(1) + W(1) * s_1_2(3); +s_2_3(2) = s_1_2(2) + W(3) * s_1_2(4); +s_2_3(3) = s_1_2(3) + W(5) * s_1_2(1); +s_2_3(4) = s_1_2(4) + W(7) * s_1_2(2); + +s_2_3(5) = s_1_2(5) + W(1) * s_1_2(7); +s_2_3(6) = s_1_2(6) + W(3) * s_1_2(8); +s_2_3(7) = s_1_2(7) + W(5) * s_1_2(5); +s_2_3(8) = s_1_2(8) + W(7) * s_1_2(6); + + +W1 = zeros(1,4); % complex +for i = 1 : 4 + W1(i) = exp(-j * (i-1) * 2 * pi/ 4 ); +end + +stage(2,1) = stage(1,1) + W1(1) * stage(1,3); +stage(2,2) = stage(1,2) + W1(2) * stage(1,4); +stage(2,3) = stage(1,3) - W1(1) * stage(1,1); +stage(2,4) = stage(1,4) - W1(2) * stage(1,2); + +stage(2,5) = stage(1,5) + W1(1) * stage(1,7); +stage(2,6) = stage(1,6) + W1(2) * stage(1,8); +stage(2,7) = stage(1,7) - W1(1) * stage(1,5); +stage(2,8) = stage(1,8) - W1(2) * stage(1,6); + +stage(2,9) = stage(1,9) + W1(1) * stage(1,11); +stage(2,10) = stage(1,10) + W1(2) * stage(1,12); +stage(2,11) = stage(1,11) - W1(1) * stage(1,9); +stage(2,12) = stage(1,12) - W1(2) * stage(1,10); + +stage(2,13) = stage(1,13) + W1(1) * stage(1,15); +stage(2,14) = stage(1,14) + W1(2) * stage(1,16); +stage(2,15) = stage(1,15) - W1(1) * stage(1,13); +stage(2,16) = stage(1,16) - W1(2) * stage(1,14); + +% theard stage + +s_3_4 = zeros(1,number_of_samples); + +s_3_4(1) = s_2_3(1) + W(1) * s_2_3(5); +s_3_4(2) = s_2_3(2) + W(2) * s_2_3(6); + +s_3_4(3) = s_2_3(3) + W(3) * s_2_3(7); +s_3_4(4) = s_2_3(4) + W(4) * s_2_3(8); + + +s_3_4(5) = s_2_3(5) + W(5) * s_2_3(1); +s_3_4(6) = s_2_3(6) + W(6) * s_2_3(2); + +s_3_4(7) = s_2_3(7) + W(7) * s_2_3(3); +s_3_4(8) = s_2_3(8) + W(8) * s_2_3(4); + +W2 = zeros(1,8); % complex +for i = 1 : 8 + W2(i) = exp(-j * (i-1) * 2 * pi/ 8 ); +end + +stage(3,1) = stage(2,1) + W2(1) * stage(2,5); +stage(3,2) = stage(2,2) + W2(2) * stage(2,6); +stage(3,3) = stage(2,3) + W2(3) * stage(2,7); +stage(3,4) = stage(2,4) + W2(4) * stage(2,8); +stage(3,5) = stage(2,5) - W2(1) * stage(2,1); +stage(3,6) = stage(2,6) - W2(2) * stage(2,2); +stage(3,7) = stage(2,7) - W2(3) * stage(2,3); +stage(3,8) = stage(2,8) - W2(4) * stage(2,4); + +stage(3,9) = stage(2,9) + W2(1) * stage(2,13); +stage(3,10) = stage(2,10) + W2(2) * stage(2,14); +stage(3,11) = stage(2,11) + W2(3) * stage(2,15); +stage(3,12) = stage(2,12) + W2(4) * stage(2,16); +stage(3,13) = stage(2,13) - W2(1) * stage(2,9); +stage(3,14) = stage(2,14) - W2(2) * stage(2,10); +stage(3,15) = stage(2,15) - W2(3) * stage(2,11); +stage(3,16) = stage(2,16) - W2(4) * stage(2,12); + + +% Fourt stage + +W3 = zeros(1,16); % complex +for i = 1 : 16 + W3(i) = exp(-j * (i-1) * 2 * pi/ 16 ); +end + +stage(4,1) = stage(3,1) + W3(1) * stage(3,9); +stage(4,2) = stage(3,2) + W3(2) * stage(3,10); +stage(4,3) = stage(3,3) + W3(3) * stage(3,11); +stage(4,4) = stage(3,4) + W3(4) * stage(3,12); +stage(4,5) = stage(3,5) + W3(5) * stage(3,13); +stage(4,6) = stage(3,6) + W3(6) * stage(3,14); +stage(4,7) = stage(3,7) + W3(7) * stage(3,15); +stage(4,8) = stage(3,8) + W3(8) * stage(3,16); +stage(4,9) = stage(3,9) - W3(1) * stage(3,1); +stage(4,10) = stage(3,10) - W3(2) * stage(3,2); +stage(4,11) = stage(3,11) - W3(3) * stage(3,3); +stage(4,12) = stage(3,12) - W3(4) * stage(3,4); +stage(4,13) = stage(3,13) - W3(5) * stage(3,5); +stage(4,14) = stage(3,14) - W3(6) * stage(3,6); +stage(4,15) = stage(3,15) - W3(7) * stage(3,7); +stage(4,16) = stage(3,16) - W3(8) * stage(3,8); + + +figure(4) +stem(n, abs( stage(4,:) ) ) + + + + + diff --git a/matlab/sample_code_fft.m b/matlab/sample_code_fft.m new file mode 100644 index 0000000..bc8d096 --- /dev/null +++ b/matlab/sample_code_fft.m @@ -0,0 +1,16 @@ +f = 4000; +fs = 22050; +fftLength=1024; %windowlength +x =sin(2*pi*f*[0:1/fs:1]); %makethesinewave +ft =fft(x,fftLength); %doFFT,userect.window +ftMag=abs(ft); %computemagnitude + +% plot the results both in linear and dB magnitudes + +subplot(2, 1, 1), plot(ftMag) +title('Linear Magnitude') +ylabel('magnitude'), xlabel('bins') + +subplot(2, 1, 2), plot(20*log10(ftMag)) +title('dB Magnitude') +ylabel('dB'), xlabel('bins') \ No newline at end of file diff --git a/top.v b/top.v index 0dc51a0..2b4a10a 100644 --- a/top.v +++ b/top.v @@ -3,31 +3,29 @@ // // `include "clock_divider_param.v" // `include "clock_enable_param.v" +// `include "debounce_switch.v" module top #( parameter - //pattern generator paremater - SPEED = 300, //enable signal parameters WAIT = 1, - WAIT_WIDTH = 2, + WAIT_WIDTH = 2 )( input clk ); //------internal wires and registers-------- -wire w_enable; - +// wire w_enable; wire clk50; //-----sub modules-------------------------- -clock_enable_param #( - .WAIT(WAIT), - .WIDTH(WAIT_WIDTH) - ) clock_enable1 ( - .clk(clk), - .enable(w_enable) -); +// clock_enable_param #( +// .WAIT(WAIT), +// .WIDTH(WAIT_WIDTH) +// ) clock_enable1 ( +// .clk(clk), +// .enable(w_enable) +// ); clock_divider #( .DIVIDER(1), @@ -37,10 +35,10 @@ clock_divider #( .clk_out(clk50) ); -debounce_switch debounce_switch_reset( - .clk(clk), - .i_switch(), - .o_switch() -); +// debounce_switch debounce_switch_reset( +// .clk(clk), +// .i_switch(), +// .o_switch() +// ); endmodule \ No newline at end of file diff --git a/top_tb.v b/top_tb.v index 33a8709..fa451b7 100644 --- a/top_tb.v +++ b/top_tb.v @@ -16,21 +16,18 @@ //top module `include "top.v" -module top_vga_mem_tb#( parameter - WAIT = 1, - WAIT_WIDTH = 2, - SPEED = 2, - //memory parameters - ADDR_WIDTH = 17, //19, // - DATA_WIDTH = 12, - DEPTH = 307_200//76_800, // -)(); +module top_tb(); reg clk = 1'b0; // 50% duty cycle clock always #0.5 clk <= ~clk; +top UUT( + .clk(clk) +); + + initial begin #030_000;